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arm64: dts: imx8mp-evk: enable uart1/3 ports
[linux-block.git] / arch / arm64 / boot / dts / freescale / imx8mp-evk.dts
CommitLineData
9e847693
AH		 1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2019 NXP
4 */
5
6/dts-v1/;
7
d5065050 8#include <dt-bindings/phy/phy-imx8-pcie.h>
9e847693
AH		 9#include "imx8mp.dtsi"
10
11/ {
12 model = "NXP i.MX8MPlus EVK board";
13 compatible = "fsl,imx8mp-evk", "fsl,imx8mp";
14
15 chosen {
16 stdout-path = &uart2;
17 };
18
50d336b1
AH		 19 gpio-leds {
20 compatible = "gpio-leds";
21 pinctrl-names = "default";
22 pinctrl-0 = <&pinctrl_gpio_led>;
23
24 status {
25 label = "yellow:status";
26 gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
27 default-state = "on";
28 };
29 };
30
9e847693
AH		 31 memory@40000000 {
32 device_type = "memory";
33 reg = <0x0 0x40000000 0 0xc0000000>,
34 <0x1 0x00000000 0 0xc0000000>;
35 };
36
d5065050
RZ		 37 pcie0_refclk: pcie0-refclk {
38 compatible = "fixed-clock";
39 #clock-cells = <0>;
40 clock-frequency = <100000000>;
41 };
42
3a7d56b3
JZ		 43 reg_can1_stby: regulator-can1-stby {
44 compatible = "regulator-fixed";
45 regulator-name = "can1-stby";
46 pinctrl-names = "default";
47 pinctrl-0 = <&pinctrl_flexcan1_reg>;
48 regulator-min-microvolt = <3300000>;
49 regulator-max-microvolt = <3300000>;
50 gpio = <&gpio5 5 GPIO_ACTIVE_HIGH>;
51 enable-active-high;
52 };
53
54 reg_can2_stby: regulator-can2-stby {
55 compatible = "regulator-fixed";
56 regulator-name = "can2-stby";
57 pinctrl-names = "default";
58 pinctrl-0 = <&pinctrl_flexcan2_reg>;
59 regulator-min-microvolt = <3300000>;
60 regulator-max-microvolt = <3300000>;
61 gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>;
62 enable-active-high;
63 };
64
d5065050
RZ		 65 reg_pcie0: regulator-pcie {
66 compatible = "regulator-fixed";
67 pinctrl-names = "default";
68 pinctrl-0 = <&pinctrl_pcie0_reg>;
69 regulator-name = "MPCIE_3V3";
70 regulator-min-microvolt = <3300000>;
71 regulator-max-microvolt = <3300000>;
72 gpio = <&gpio2 6 GPIO_ACTIVE_HIGH>;
73 enable-active-high;
74 };
75
9e847693
AH		 76 reg_usdhc2_vmmc: regulator-usdhc2 {
77 compatible = "regulator-fixed";
78 pinctrl-names = "default";
79 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
80 regulator-name = "VSD_3V3";
81 regulator-min-microvolt = <3300000>;
82 regulator-max-microvolt = <3300000>;
83 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
84 enable-active-high;
85 };
86};
87
e56fdc60
LS		 88&A53_0 {
89 cpu-supply = <&reg_arm>;
3a7d56b3
JZ		 90};
91
e56fdc60
LS		 92&A53_1 {
93 cpu-supply = <&reg_arm>;
94};
95
96&A53_2 {
97 cpu-supply = <&reg_arm>;
98};
99
100&A53_3 {
101 cpu-supply = <&reg_arm>;
3a7d56b3
JZ		 102};
103
dc6d5dc8
JZ		 104&eqos {
105 pinctrl-names = "default";
106 pinctrl-0 = <&pinctrl_eqos>;
107 phy-mode = "rgmii-id";
108 phy-handle = <&ethphy0>;
0bc3e333
XY		 109 snps,force_thresh_dma_mode;
110 snps,mtl-tx-config = <&mtl_tx_setup>;
111 snps,mtl-rx-config = <&mtl_rx_setup>;
dc6d5dc8
JZ		 112 status = "okay";
113
114 mdio {
115 compatible = "snps,dwmac-mdio";
116 #address-cells = <1>;
117 #size-cells = <0>;
118
119 ethphy0: ethernet-phy@1 {
120 compatible = "ethernet-phy-ieee802.3-c22";
121 reg = <1>;
122 eee-broken-1000t;
e0aa402b
JZ		 123 reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
124 reset-assert-us = <10000>;
125 reset-deassert-us = <80000>;
311ad460 126 realtek,clkout-disable;
dc6d5dc8
JZ		 127 };
128 };
0bc3e333
XY		 129
130 mtl_tx_setup: tx-queues-config {
131 snps,tx-queues-to-use = <5>;
132 snps,tx-sched-sp;
133
134 queue0 {
135 snps,dcb-algorithm;
136 snps,priority = <0x1>;
137 };
138
139 queue1 {
140 snps,dcb-algorithm;
141 snps,priority = <0x2>;
142 };
143
144 queue2 {
145 snps,dcb-algorithm;
146 snps,priority = <0x4>;
147 };
148
149 queue3 {
150 snps,dcb-algorithm;
151 snps,priority = <0x8>;
152 };
153
154 queue4 {
155 snps,dcb-algorithm;
156 snps,priority = <0xf0>;
157 };
158 };
159
160 mtl_rx_setup: rx-queues-config {
161 snps,rx-queues-to-use = <5>;
162 snps,rx-sched-sp;
163
164 queue0 {
165 snps,dcb-algorithm;
166 snps,priority = <0x1>;
167 snps,map-to-dma-channel = <0>;
168 };
169
170 queue1 {
171 snps,dcb-algorithm;
172 snps,priority = <0x2>;
173 snps,map-to-dma-channel = <1>;
174 };
175
176 queue2 {
177 snps,dcb-algorithm;
178 snps,priority = <0x4>;
179 snps,map-to-dma-channel = <2>;
180 };
181
182 queue3 {
183 snps,dcb-algorithm;
184 snps,priority = <0x8>;
185 snps,map-to-dma-channel = <3>;
186 };
187
188 queue4 {
189 snps,dcb-algorithm;
190 snps,priority = <0xf0>;
191 snps,map-to-dma-channel = <4>;
192 };
193 };
dc6d5dc8
JZ		 194};
195
9e847693
AH		 196&fec {
197 pinctrl-names = "default";
198 pinctrl-0 = <&pinctrl_fec>;
199 phy-mode = "rgmii-id";
200 phy-handle = <&ethphy1>;
201 fsl,magic-packet;
202 status = "okay";
203
204 mdio {
205 #address-cells = <1>;
206 #size-cells = <0>;
207
208 ethphy1: ethernet-phy@1 {
209 compatible = "ethernet-phy-ieee802.3-c22";
210 reg = <1>;
211 eee-broken-1000t;
212 reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
798a1807
FE		 213 reset-assert-us = <10000>;
214 reset-deassert-us = <80000>;
311ad460 215 realtek,clkout-disable;
9e847693
AH		 216 };
217 };
218};
219
f5f1e907
UKK		 220&flexcan1 {
221 pinctrl-names = "default";
222 pinctrl-0 = <&pinctrl_flexcan1>;
223 xceiver-supply = <&reg_can1_stby>;
224 status = "okay";
225};
226
227&flexcan2 {
228 pinctrl-names = "default";
229 pinctrl-0 = <&pinctrl_flexcan2>;
230 xceiver-supply = <&reg_can2_stby>;
231 status = "disabled";/* can2 pin conflict with pdm */
232};
233
5497bc2a
UKK		 234&i2c1 {
235 clock-frequency = <400000>;
236 pinctrl-names = "default";
237 pinctrl-0 = <&pinctrl_i2c1>;
238 status = "okay";
239
240 pmic@25 {
241 compatible = "nxp,pca9450c";
242 reg = <0x25>;
243 pinctrl-names = "default";
244 pinctrl-0 = <&pinctrl_pmic>;
245 interrupt-parent = <&gpio1>;
246 interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
247
248 regulators {
249 BUCK1 {
250 regulator-name = "BUCK1";
251 regulator-min-microvolt = <720000>;
252 regulator-max-microvolt = <1000000>;
253 regulator-boot-on;
254 regulator-always-on;
255 regulator-ramp-delay = <3125>;
256 };
257
e56fdc60 258 reg_arm: BUCK2 {
5497bc2a
UKK		 259 regulator-name = "BUCK2";
260 regulator-min-microvolt = <720000>;
261 regulator-max-microvolt = <1025000>;
262 regulator-boot-on;
263 regulator-always-on;
264 regulator-ramp-delay = <3125>;
265 nxp,dvs-run-voltage = <950000>;
266 nxp,dvs-standby-voltage = <850000>;
267 };
268
269 BUCK4 {
270 regulator-name = "BUCK4";
271 regulator-min-microvolt = <3000000>;
272 regulator-max-microvolt = <3600000>;
273 regulator-boot-on;
274 regulator-always-on;
275 };
276
277 BUCK5 {
278 regulator-name = "BUCK5";
279 regulator-min-microvolt = <1650000>;
280 regulator-max-microvolt = <1950000>;
281 regulator-boot-on;
282 regulator-always-on;
283 };
284
285 BUCK6 {
286 regulator-name = "BUCK6";
287 regulator-min-microvolt = <1045000>;
288 regulator-max-microvolt = <1155000>;
289 regulator-boot-on;
290 regulator-always-on;
291 };
292
293 LDO1 {
294 regulator-name = "LDO1";
295 regulator-min-microvolt = <1650000>;
296 regulator-max-microvolt = <1950000>;
297 regulator-boot-on;
298 regulator-always-on;
299 };
300
301 LDO3 {
302 regulator-name = "LDO3";
303 regulator-min-microvolt = <1710000>;
304 regulator-max-microvolt = <1890000>;
305 regulator-boot-on;
306 regulator-always-on;
307 };
308
309 LDO5 {
310 regulator-name = "LDO5";
311 regulator-min-microvolt = <1800000>;
312 regulator-max-microvolt = <3300000>;
313 regulator-boot-on;
314 regulator-always-on;
315 };
316 };
317 };
318};
319
5e4a67ff
AH		 320&i2c3 {
321 clock-frequency = <400000>;
322 pinctrl-names = "default";
323 pinctrl-0 = <&pinctrl_i2c3>;
324 status = "okay";
2dfb4b13
AH		 325
326 pca6416: gpio@20 {
327 compatible = "ti,tca6416";
328 reg = <0x20>;
329 gpio-controller;
330 #gpio-cells = <2>;
9fb35e0d
HV		 331 interrupt-controller;
332 #interrupt-cells = <2>;
333 pinctrl-names = "default";
334 pinctrl-0 = <&pinctrl_pca6416_int>;
335 interrupt-parent = <&gpio1>;
336 interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
6bb691f2
HV		 337 gpio-line-names = "EXT_PWREN1",
338 "EXT_PWREN2",
339 "CAN1/I2C5_SEL",
340 "PDM/CAN2_SEL",
341 "FAN_EN",
342 "PWR_MEAS_IO1",
343 "PWR_MEAS_IO2",
344 "EXP_P0_7",
345 "EXP_P1_0",
346 "EXP_P1_1",
347 "EXP_P1_2",
348 "EXP_P1_3",
349 "EXP_P1_4",
350 "EXP_P1_5",
351 "EXP_P1_6",
352 "EXP_P1_7";
2dfb4b13 353 };
5e4a67ff
AH		 354};
355
8134822d
HV		 356/* I2C on expansion connector J22. */
357&i2c5 {
358 clock-frequency = <100000>; /* Lower clock speed for external bus. */
359 pinctrl-names = "default";
360 pinctrl-0 = <&pinctrl_i2c5>;
361 status = "disabled"; /* can1 pins conflict with i2c5 */
362
363 /* GPIO 2 of PCA6416 is used to switch between CAN1 and I2C5 functions:
364 * LOW: CAN1 (default, pull-down)
365 * HIGH: I2C5
366 * You need to set it to high to enable I2C5 (for example, add gpio-hog
367 * in pca6416 node).
368 */
369};
370
d5065050
RZ		 371&pcie_phy {
372 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
373 clocks = <&pcie0_refclk>;
374 clock-names = "ref";
375 status = "okay";
376};
377
378&pcie {
379 pinctrl-names = "default";
380 pinctrl-0 = <&pinctrl_pcie0>;
381 reset-gpio = <&gpio2 7 GPIO_ACTIVE_LOW>;
382 clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
383 <&clk IMX8MP_CLK_PCIE_ROOT>,
384 <&clk IMX8MP_CLK_HSIO_AXI>;
385 clock-names = "pcie", "pcie_aux", "pcie_bus";
386 assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>;
387 assigned-clock-rates = <10000000>;
388 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>;
389 vpcie-supply = <&reg_pcie0>;
390 status = "okay";
391};
392
2f6f2a0c
CW		 393&pwm1 {
394 pinctrl-names = "default";
395 pinctrl-0 = <&pinctrl_pwm1>;
396 status = "okay";
397};
398
399&pwm2 {
400 pinctrl-names = "default";
401 pinctrl-0 = <&pinctrl_pwm2>;
402 status = "okay";
403};
404
405&pwm4 {
406 pinctrl-names = "default";
407 pinctrl-0 = <&pinctrl_pwm4>;
408 status = "okay";
409};
410
9e847693
AH		 411&snvs_pwrkey {
412 status = "okay";
413};
414
c2f812df
PF		 415&uart1 { /* BT */
416 pinctrl-names = "default";
417 pinctrl-0 = <&pinctrl_uart1>;
418 assigned-clocks = <&clk IMX8MP_CLK_UART1>;
419 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
420 uart-has-rtscts;
421 status = "okay";
422};
423
9e847693
AH		 424&uart2 {
425 /* console */
426 pinctrl-names = "default";
427 pinctrl-0 = <&pinctrl_uart2>;
428 status = "okay";
429};
430
43da4f92
LJ		 431&usb3_phy1 {
432 status = "okay";
433};
434
435&usb3_1 {
436 status = "okay";
437};
438
439&usb_dwc3_1 {
440 pinctrl-names = "default";
441 pinctrl-0 = <&pinctrl_usb1_vbus>;
442 dr_mode = "host";
443 status = "okay";
444};
445
c2f812df
PF		 446&uart3 {
447 pinctrl-names = "default";
448 pinctrl-0 = <&pinctrl_uart3>;
449 assigned-clocks = <&clk IMX8MP_CLK_UART3>;
450 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
451 uart-has-rtscts;
452 status = "okay";
453};
454
9e847693
AH		 455&usdhc2 {
456 assigned-clocks = <&clk IMX8MP_CLK_USDHC2>;
457 assigned-clock-rates = <400000000>;
458 pinctrl-names = "default", "state_100mhz", "state_200mhz";
459 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
460 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
461 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
462 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
463 vmmc-supply = <&reg_usdhc2_vmmc>;
464 bus-width = <4>;
465 status = "okay";
466};
467
468&usdhc3 {
469 assigned-clocks = <&clk IMX8MP_CLK_USDHC3>;
470 assigned-clock-rates = <400000000>;
471 pinctrl-names = "default", "state_100mhz", "state_200mhz";
472 pinctrl-0 = <&pinctrl_usdhc3>;
473 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
474 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
475 bus-width = <8>;
476 non-removable;
477 status = "okay";
478};
479
480&wdog1 {
481 pinctrl-names = "default";
482 pinctrl-0 = <&pinctrl_wdog>;
483 fsl,ext-reset-output;
484 status = "okay";
485};
486
487&iomuxc {
dc6d5dc8
JZ		 488 pinctrl_eqos: eqosgrp {
489 fsl,pins = <
e6e1bc0e
PF		 490 MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2
491 MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2
492 MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90
493 MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90
494 MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90
495 MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90
496 MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90
497 MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90
498 MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16
499 MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16
500 MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16
501 MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16
502 MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16
503 MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16
504 MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x10
dc6d5dc8
JZ		 505 >;
506 };
507
9e847693
AH		 508 pinctrl_fec: fecgrp {
509 fsl,pins = <
95587ecf
PF		 510 MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x2
511 MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x2
512 MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x90
513 MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x90
514 MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x90
515 MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x90
516 MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x90
517 MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x90
518 MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x16
519 MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x16
520 MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x16
521 MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x16
522 MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x16
523 MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x16
524 MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x10
9e847693
AH		 525 >;
526 };
527
3a7d56b3
JZ		 528 pinctrl_flexcan1: flexcan1grp {
529 fsl,pins = <
530 MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x154
531 MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x154
532 >;
533 };
534
535 pinctrl_flexcan2: flexcan2grp {
536 fsl,pins = <
537 MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x154
538 MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x154
539 >;
540 };
541
542 pinctrl_flexcan1_reg: flexcan1reggrp {
543 fsl,pins = <
544 MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x154 /* CAN1_STBY */
545 >;
546 };
547
548 pinctrl_flexcan2_reg: flexcan2reggrp {
549 fsl,pins = <
550 MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x154 /* CAN2_STBY */
551 >;
552 };
553
50d336b1
AH		 554 pinctrl_gpio_led: gpioledgrp {
555 fsl,pins = <
b838582a 556 MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x140
50d336b1
AH		 557 >;
558 };
559
5497bc2a
UKK		 560 pinctrl_i2c1: i2c1grp {
561 fsl,pins = <
05a7f434
PF		 562 MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2
563 MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2
5497bc2a
UKK		 564 >;
565 };
566
5e4a67ff
AH		 567 pinctrl_i2c3: i2c3grp {
568 fsl,pins = <
0836de51
PF		 569 MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2
570 MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2
5e4a67ff
AH		 571 >;
572 };
573
8134822d
HV		 574 pinctrl_i2c5: i2c5grp {
575 fsl,pins = <
8c214b78
PF		 576 MX8MP_IOMUXC_SPDIF_RX__I2C5_SDA 0x400001c2
577 MX8MP_IOMUXC_SPDIF_TX__I2C5_SCL 0x400001c2
8134822d
HV		 578 >;
579 };
580
d5065050
RZ		 581 pinctrl_pcie0: pcie0grp {
582 fsl,pins = <
583 MX8MP_IOMUXC_I2C4_SCL__PCIE_CLKREQ_B 0x61 /* open drain, pull up */
584 MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07 0x41
585 >;
586 };
587
588 pinctrl_pcie0_reg: pcie0reggrp {
589 fsl,pins = <
590 MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x41
591 >;
592 };
593
5497bc2a
UKK		 594 pinctrl_pmic: pmicgrp {
595 fsl,pins = <
596 MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x000001c0
597 >;
598 };
599
9fb35e0d
HV		 600 pinctrl_pca6416_int: pca6416_int_grp {
601 fsl,pins = <
602 MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x146 /* Input pull-up. */
603 >;
604 };
605
2f6f2a0c
CW		 606 pinctrl_pwm1: pwm1grp {
607 fsl,pins = <
608 MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT 0x116
609 >;
610 };
611
612 pinctrl_pwm2: pwm2grp {
613 fsl,pins = <
614 MX8MP_IOMUXC_GPIO1_IO11__PWM2_OUT 0x116
615 >;
616 };
617
618 pinctrl_pwm4: pwm4grp {
619 fsl,pins = <
620 MX8MP_IOMUXC_SAI5_RXFS__PWM4_OUT 0x116
621 >;
622 };
623
7124b34f 624 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
9e847693 625 fsl,pins = <
01785f1f 626 MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x40
9e847693
AH		 627 >;
628 };
629
c2f812df
PF		 630 pinctrl_uart1: uart1grp {
631 fsl,pins = <
632 MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140
633 MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140
634 MX8MP_IOMUXC_UART3_RXD__UART1_DCE_CTS 0x140
635 MX8MP_IOMUXC_UART3_TXD__UART1_DCE_RTS 0x140
636 >;
637 };
638
9e847693
AH		 639 pinctrl_uart2: uart2grp {
640 fsl,pins = <
2d4fb72b
SS		 641 MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140
642 MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x140
9e847693
AH		 643 >;
644 };
645
43da4f92
LJ		 646 pinctrl_usb1_vbus: usb1grp {
647 fsl,pins = <
e2c00820 648 MX8MP_IOMUXC_GPIO1_IO14__USB2_OTG_PWR 0x10
43da4f92
LJ		 649 >;
650 };
651
c2f812df
PF		 652 pinctrl_uart3: uart3grp {
653 fsl,pins = <
654 MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX 0x140
655 MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX 0x140
656 MX8MP_IOMUXC_ECSPI1_SS0__UART3_DCE_RTS 0x140
657 MX8MP_IOMUXC_ECSPI1_MISO__UART3_DCE_CTS 0x140
658 >;
659 };
660
9e847693
AH		 661 pinctrl_usdhc2: usdhc2grp {
662 fsl,pins = <
663 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190
664 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0
665 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0
666 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0
667 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0
668 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0
01785f1f 669 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
9e847693
AH		 670 >;
671 };
672
7124b34f 673 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
9e847693
AH		 674 fsl,pins = <
675 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194
676 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4
677 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4
678 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4
679 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4
680 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4
01785f1f 681 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
9e847693
AH		 682 >;
683 };
684
7124b34f 685 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
9e847693
AH		 686 fsl,pins = <
687 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196
688 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6
689 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6
690 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6
691 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6
692 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6
01785f1f 693 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
9e847693
AH		 694 >;
695 };
696
7124b34f 697 pinctrl_usdhc2_gpio: usdhc2gpiogrp {
9e847693
AH		 698 fsl,pins = <
699 MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4
700 >;
701 };
702
703 pinctrl_usdhc3: usdhc3grp {
704 fsl,pins = <
705 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190
706 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0
707 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0
708 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0
709 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0
710 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0
711 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0
712 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0
713 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0
714 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0
715 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190
716 >;
717 };
718
7124b34f 719 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
9e847693
AH		 720 fsl,pins = <
721 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194
722 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4
723 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4
724 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4
725 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4
726 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4
727 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4
728 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4
729 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4
730 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4
731 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194
732 >;
733 };
734
7124b34f 735 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
9e847693
AH		 736 fsl,pins = <
737 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196
738 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6
739 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6
740 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6
741 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6
742 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6
743 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6
744 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6
745 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6
746 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6
747 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196
748 >;
749 };
750
751 pinctrl_wdog: wdoggrp {
752 fsl,pins = <
fa15cec9 753 MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x166
9e847693
AH		 754 >;
755 };
756};
Linux 6.x block layer and io_uring tree(s)