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arm64: dts: Add Librem5 Evergreen
[linux-2.6-block.git] / arch / arm64 / boot / dts / freescale / imx8mn.dtsi
CommitLineData
6c3debcb
AH		 1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2019 NXP
4 */
5
6#include <dt-bindings/clock/imx8mn-clock.h>
7#include <dt-bindings/gpio/gpio.h>
8#include <dt-bindings/input/input.h>
9#include <dt-bindings/interrupt-controller/arm-gic.h>
819779a9 10#include <dt-bindings/thermal/thermal.h>
6c3debcb
AH		 11
12#include "imx8mn-pinfunc.h"
13
14/ {
6c3debcb
AH		 15 interrupt-parent = <&gic>;
16 #address-cells = <2>;
17 #size-cells = <2>;
18
19 aliases {
20 ethernet0 = &fec1;
21 gpio0 = &gpio1;
22 gpio1 = &gpio2;
23 gpio2 = &gpio3;
24 gpio3 = &gpio4;
25 gpio4 = &gpio5;
26 i2c0 = &i2c1;
27 i2c1 = &i2c2;
28 i2c2 = &i2c3;
29 i2c3 = &i2c4;
30 mmc0 = &usdhc1;
31 mmc1 = &usdhc2;
32 mmc2 = &usdhc3;
33 serial0 = &uart1;
34 serial1 = &uart2;
35 serial2 = &uart3;
36 serial3 = &uart4;
37 spi0 = &ecspi1;
38 spi1 = &ecspi2;
39 spi2 = &ecspi3;
40 };
41
42 cpus {
43 #address-cells = <1>;
44 #size-cells = <0>;
45
df844a9a
AH		 46 idle-states {
47 entry-method = "psci";
48
49 cpu_pd_wait: cpu-pd-wait {
50 compatible = "arm,idle-state";
51 arm,psci-suspend-param = <0x0010033>;
52 local-timer-stop;
53 entry-latency-us = <1000>;
54 exit-latency-us = <700>;
55 min-residency-us = <2700>;
56 };
57 };
58
6c3debcb
AH		 59 A53_0: cpu@0 {
60 device_type = "cpu";
61 compatible = "arm,cortex-a53";
62 reg = <0x0>;
63 clock-latency = <61036>;
64 clocks = <&clk IMX8MN_CLK_ARM>;
65 enable-method = "psci";
66 next-level-cache = <&A53_L2>;
01c49314
AH		 67 operating-points-v2 = <&a53_opp_table>;
68 nvmem-cells = <&cpu_speed_grade>;
69 nvmem-cell-names = "speed_grade";
df844a9a 70 cpu-idle-states = <&cpu_pd_wait>;
819779a9 71 #cooling-cells = <2>;
6c3debcb
AH		 72 };
73
74 A53_1: cpu@1 {
75 device_type = "cpu";
76 compatible = "arm,cortex-a53";
77 reg = <0x1>;
78 clock-latency = <61036>;
79 clocks = <&clk IMX8MN_CLK_ARM>;
80 enable-method = "psci";
81 next-level-cache = <&A53_L2>;
01c49314 82 operating-points-v2 = <&a53_opp_table>;
df844a9a 83 cpu-idle-states = <&cpu_pd_wait>;
819779a9 84 #cooling-cells = <2>;
6c3debcb
AH		 85 };
86
87 A53_2: cpu@2 {
88 device_type = "cpu";
89 compatible = "arm,cortex-a53";
90 reg = <0x2>;
91 clock-latency = <61036>;
92 clocks = <&clk IMX8MN_CLK_ARM>;
93 enable-method = "psci";
94 next-level-cache = <&A53_L2>;
01c49314 95 operating-points-v2 = <&a53_opp_table>;
df844a9a 96 cpu-idle-states = <&cpu_pd_wait>;
819779a9 97 #cooling-cells = <2>;
6c3debcb
AH		 98 };
99
100 A53_3: cpu@3 {
101 device_type = "cpu";
102 compatible = "arm,cortex-a53";
103 reg = <0x3>;
104 clock-latency = <61036>;
105 clocks = <&clk IMX8MN_CLK_ARM>;
106 enable-method = "psci";
107 next-level-cache = <&A53_L2>;
01c49314 108 operating-points-v2 = <&a53_opp_table>;
df844a9a 109 cpu-idle-states = <&cpu_pd_wait>;
819779a9 110 #cooling-cells = <2>;
6c3debcb
AH		 111 };
112
113 A53_L2: l2-cache0 {
114 compatible = "cache";
115 };
116 };
117
01c49314
AH		 118 a53_opp_table: opp-table {
119 compatible = "operating-points-v2";
120 opp-shared;
121
122 opp-1200000000 {
123 opp-hz = /bits/ 64 <1200000000>;
8c30e7ca 124 opp-microvolt = <850000>;
01c49314
AH		 125 opp-supported-hw = <0xb00>, <0x7>;
126 clock-latency-ns = <150000>;
127 opp-suspend;
128 };
129
130 opp-1400000000 {
131 opp-hz = /bits/ 64 <1400000000>;
132 opp-microvolt = <950000>;
133 opp-supported-hw = <0x300>, <0x7>;
134 clock-latency-ns = <150000>;
135 opp-suspend;
136 };
137
138 opp-1500000000 {
139 opp-hz = /bits/ 64 <1500000000>;
140 opp-microvolt = <1000000>;
141 opp-supported-hw = <0x100>, <0x3>;
142 clock-latency-ns = <150000>;
143 opp-suspend;
144 };
145 };
146
6c3debcb
AH		 147 osc_32k: clock-osc-32k {
148 compatible = "fixed-clock";
149 #clock-cells = <0>;
150 clock-frequency = <32768>;
151 clock-output-names = "osc_32k";
152 };
153
154 osc_24m: clock-osc-24m {
155 compatible = "fixed-clock";
156 #clock-cells = <0>;
157 clock-frequency = <24000000>;
158 clock-output-names = "osc_24m";
159 };
160
161 clk_ext1: clock-ext1 {
162 compatible = "fixed-clock";
163 #clock-cells = <0>;
164 clock-frequency = <133000000>;
165 clock-output-names = "clk_ext1";
166 };
167
168 clk_ext2: clock-ext2 {
169 compatible = "fixed-clock";
170 #clock-cells = <0>;
171 clock-frequency = <133000000>;
172 clock-output-names = "clk_ext2";
173 };
174
175 clk_ext3: clock-ext3 {
176 compatible = "fixed-clock";
177 #clock-cells = <0>;
178 clock-frequency = <133000000>;
179 clock-output-names = "clk_ext3";
180 };
181
182 clk_ext4: clock-ext4 {
183 compatible = "fixed-clock";
184 #clock-cells = <0>;
185 clock-frequency= <133000000>;
186 clock-output-names = "clk_ext4";
187 };
188
c13a7d84
JB		 189 pmu {
190 compatible = "arm,cortex-a53-pmu";
191 interrupts = <GIC_PPI 7
192 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
193 interrupt-affinity = <&A53_0>, <&A53_1>, <&A53_2>, <&A53_3>;
194 };
195
6c3debcb
AH		 196 psci {
197 compatible = "arm,psci-1.0";
198 method = "smc";
199 };
200
819779a9
AH		 201 thermal-zones {
202 cpu-thermal {
203 polling-delay-passive = <250>;
204 polling-delay = <2000>;
205 thermal-sensors = <&tmu>;
206 trips {
207 cpu_alert0: trip0 {
208 temperature = <85000>;
209 hysteresis = <2000>;
210 type = "passive";
211 };
212
213 cpu_crit0: trip1 {
214 temperature = <95000>;
215 hysteresis = <2000>;
216 type = "critical";
217 };
218 };
219
220 cooling-maps {
221 map0 {
222 trip = <&cpu_alert0>;
223 cooling-device =
224 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
225 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
226 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
227 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
228 };
229 };
230 };
231 };
232
6c3debcb
AH		 233 timer {
234 compatible = "arm,armv8-timer";
0656e37a
KK		 235 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
236 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
237 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
238 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
6c3debcb
AH		 239 clock-frequency = <8000000>;
240 arm,no-tick-in-suspend;
241 };
242
243 soc@0 {
ce58459d 244 compatible = "fsl,imx8mn-soc", "simple-bus";
6c3debcb
AH		 245 #address-cells = <1>;
246 #size-cells = <1>;
247 ranges = <0x0 0x0 0x0 0x3e000000>;
cbff2379
AG		 248 nvmem-cells = <&imx8mn_uid>;
249 nvmem-cell-names = "soc_unique_id";
6c3debcb
AH		 250
251 aips1: bus@30000000 {
dc3efc6f 252 compatible = "fsl,aips-bus", "simple-bus";
921a6845 253 reg = <0x30000000 0x400000>;
6c3debcb
AH		 254 #address-cells = <1>;
255 #size-cells = <1>;
256 ranges;
257
970406ea
AF		 258 spba: bus@30000000 {
259 compatible = "fsl,spba-bus", "simple-bus";
260 #address-cells = <1>;
261 #size-cells = <1>;
262 reg = <0x30000000 0x100000>;
263 ranges;
264
9e986006
AF		 265 sai2: sai@30020000 {
266 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
267 reg = <0x30020000 0x10000>;
268 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
269 clocks = <&clk IMX8MN_CLK_SAI2_IPG>,
270 <&clk IMX8MN_CLK_DUMMY>,
271 <&clk IMX8MN_CLK_SAI2_ROOT>,
272 <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>;
273 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
274 dmas = <&sdma2 2 2 0>, <&sdma2 3 2 0>;
275 dma-names = "rx", "tx";
276 status = "disabled";
277 };
278
279 sai3: sai@30030000 {
280 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
281 reg = <0x30030000 0x10000>;
282 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
283 clocks = <&clk IMX8MN_CLK_SAI3_IPG>,
284 <&clk IMX8MN_CLK_DUMMY>,
285 <&clk IMX8MN_CLK_SAI3_ROOT>,
286 <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>;
287 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
288 dmas = <&sdma2 4 2 0>, <&sdma2 5 2 0>;
289 dma-names = "rx", "tx";
290 status = "disabled";
291 };
292
293 sai5: sai@30050000 {
294 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
295 reg = <0x30050000 0x10000>;
296 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
297 clocks = <&clk IMX8MN_CLK_SAI5_IPG>,
298 <&clk IMX8MN_CLK_DUMMY>,
299 <&clk IMX8MN_CLK_SAI5_ROOT>,
300 <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>;
301 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
302 dmas = <&sdma2 8 2 0>, <&sdma2 9 2 0>;
303 dma-names = "rx", "tx";
304 fsl,shared-interrupt;
305 fsl,dataline = <0 0xf 0xf>;
306 status = "disabled";
307 };
308
309 sai6: sai@30060000 {
310 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
311 reg = <0x30060000 0x10000>;
312 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
313 clocks = <&clk IMX8MN_CLK_SAI6_IPG>,
314 <&clk IMX8MN_CLK_DUMMY>,
315 <&clk IMX8MN_CLK_SAI6_ROOT>,
316 <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>;
317 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
318 dmas = <&sdma2 10 2 0>, <&sdma2 11 2 0>;
319 dma-names = "rx", "tx";
320 status = "disabled";
321 };
322
cca69ef6
AF		 323 micfil: audio-controller@30080000 {
324 compatible = "fsl,imx8mm-micfil";
325 reg = <0x30080000 0x10000>;
326 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
327 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
328 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
329 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
330 clocks = <&clk IMX8MN_CLK_PDM_IPG>,
331 <&clk IMX8MN_CLK_PDM_ROOT>,
332 <&clk IMX8MN_AUDIO_PLL1_OUT>,
333 <&clk IMX8MN_AUDIO_PLL2_OUT>,
334 <&clk IMX8MN_CLK_EXT3>;
335 clock-names = "ipg_clk", "ipg_clk_app",
336 "pll8k", "pll11k", "clkext3";
337 dmas = <&sdma2 24 25 0x80000000>;
338 dma-names = "rx";
339 status = "disabled";
340 };
341
b9cf7d3b
AF		 342 spdif1: spdif@30090000 {
343 compatible = "fsl,imx35-spdif";
344 reg = <0x30090000 0x10000>;
345 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
346 clocks = <&clk IMX8MN_CLK_AUDIO_AHB>, /* core */
347 <&clk IMX8MN_CLK_24M>, /* rxtx0 */
348 <&clk IMX8MN_CLK_SPDIF1>, /* rxtx1 */
349 <&clk IMX8MN_CLK_DUMMY>, /* rxtx2 */
350 <&clk IMX8MN_CLK_DUMMY>, /* rxtx3 */
351 <&clk IMX8MN_CLK_DUMMY>, /* rxtx4 */
352 <&clk IMX8MN_CLK_AUDIO_AHB>, /* rxtx5 */
353 <&clk IMX8MN_CLK_DUMMY>, /* rxtx6 */
354 <&clk IMX8MN_CLK_DUMMY>, /* rxtx7 */
355 <&clk IMX8MN_CLK_DUMMY>; /* spba */
356 clock-names = "core", "rxtx0",
357 "rxtx1", "rxtx2",
358 "rxtx3", "rxtx4",
359 "rxtx5", "rxtx6",
360 "rxtx7", "spba";
361 dmas = <&sdma2 28 18 0>, <&sdma2 29 18 0>;
362 dma-names = "rx", "tx";
363 status = "disabled";
364 };
365
9e986006
AF		 366 sai7: sai@300b0000 {
367 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
368 reg = <0x300b0000 0x10000>;
369 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
370 clocks = <&clk IMX8MN_CLK_SAI7_IPG>,
371 <&clk IMX8MN_CLK_DUMMY>,
372 <&clk IMX8MN_CLK_SAI7_ROOT>,
373 <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>;
374 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
375 dmas = <&sdma2 12 2 0>, <&sdma2 13 2 0>;
376 dma-names = "rx", "tx";
377 status = "disabled";
378 };
379
970406ea
AF		 380 easrc: easrc@300c0000 {
381 compatible = "fsl,imx8mn-easrc";
382 reg = <0x300c0000 0x10000>;
383 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
384 clocks = <&clk IMX8MN_CLK_ASRC_ROOT>;
385 clock-names = "mem";
386 dmas = <&sdma2 16 23 0> , <&sdma2 17 23 0>,
387 <&sdma2 18 23 0> , <&sdma2 19 23 0>,
388 <&sdma2 20 23 0> , <&sdma2 21 23 0>,
389 <&sdma2 22 23 0> , <&sdma2 23 23 0>;
390 dma-names = "ctx0_rx", "ctx0_tx",
391 "ctx1_rx", "ctx1_tx",
392 "ctx2_rx", "ctx2_tx",
393 "ctx3_rx", "ctx3_tx";
394 firmware-name = "imx/easrc/easrc-imx8mn.bin";
395 fsl,asrc-rate = <8000>;
396 fsl,asrc-format = <2>;
397 status = "disabled";
398 };
399 };
400
6c3debcb
AH		 401 gpio1: gpio@30200000 {
402 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
403 reg = <0x30200000 0x10000>;
404 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
405 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
406 clocks = <&clk IMX8MN_CLK_GPIO1_ROOT>;
407 gpio-controller;
408 #gpio-cells = <2>;
409 interrupt-controller;
410 #interrupt-cells = <2>;
ee8696be 411 gpio-ranges = <&iomuxc 0 10 30>;
6c3debcb
AH		 412 };
413
414 gpio2: gpio@30210000 {
415 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
416 reg = <0x30210000 0x10000>;
417 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
418 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
419 clocks = <&clk IMX8MN_CLK_GPIO2_ROOT>;
420 gpio-controller;
421 #gpio-cells = <2>;
422 interrupt-controller;
423 #interrupt-cells = <2>;
ee8696be 424 gpio-ranges = <&iomuxc 0 40 21>;
6c3debcb
AH		 425 };
426
427 gpio3: gpio@30220000 {
428 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
429 reg = <0x30220000 0x10000>;
430 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
431 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
432 clocks = <&clk IMX8MN_CLK_GPIO3_ROOT>;
433 gpio-controller;
434 #gpio-cells = <2>;
435 interrupt-controller;
436 #interrupt-cells = <2>;
ee8696be 437 gpio-ranges = <&iomuxc 0 61 26>;
6c3debcb
AH		 438 };
439
440 gpio4: gpio@30230000 {
441 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
442 reg = <0x30230000 0x10000>;
443 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
444 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
445 clocks = <&clk IMX8MN_CLK_GPIO4_ROOT>;
446 gpio-controller;
447 #gpio-cells = <2>;
448 interrupt-controller;
449 #interrupt-cells = <2>;
ee8696be 450 gpio-ranges = <&iomuxc 21 108 11>;
6c3debcb
AH		 451 };
452
453 gpio5: gpio@30240000 {
454 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
455 reg = <0x30240000 0x10000>;
456 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
457 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
458 clocks = <&clk IMX8MN_CLK_GPIO5_ROOT>;
459 gpio-controller;
460 #gpio-cells = <2>;
461 interrupt-controller;
462 #interrupt-cells = <2>;
ee8696be 463 gpio-ranges = <&iomuxc 0 119 30>;
6c3debcb
AH		 464 };
465
819779a9
AH		 466 tmu: tmu@30260000 {
467 compatible = "fsl,imx8mn-tmu", "fsl,imx8mm-tmu";
468 reg = <0x30260000 0x10000>;
469 clocks = <&clk IMX8MN_CLK_TMU_ROOT>;
470 #thermal-sensor-cells = <0>;
471 };
472
6c3debcb
AH		 473 wdog1: watchdog@30280000 {
474 compatible = "fsl,imx8mn-wdt", "fsl,imx21-wdt";
475 reg = <0x30280000 0x10000>;
476 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
477 clocks = <&clk IMX8MN_CLK_WDOG1_ROOT>;
478 status = "disabled";
479 };
480
481 wdog2: watchdog@30290000 {
482 compatible = "fsl,imx8mn-wdt", "fsl,imx21-wdt";
483 reg = <0x30290000 0x10000>;
484 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
485 clocks = <&clk IMX8MN_CLK_WDOG2_ROOT>;
486 status = "disabled";
487 };
488
489 wdog3: watchdog@302a0000 {
490 compatible = "fsl,imx8mn-wdt", "fsl,imx21-wdt";
491 reg = <0x302a0000 0x10000>;
492 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
493 clocks = <&clk IMX8MN_CLK_WDOG3_ROOT>;
494 status = "disabled";
495 };
496
497 sdma3: dma-controller@302b0000 {
958c6014 498 compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma";
6c3debcb
AH		 499 reg = <0x302b0000 0x10000>;
500 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
501 clocks = <&clk IMX8MN_CLK_SDMA3_ROOT>,
502 <&clk IMX8MN_CLK_SDMA3_ROOT>;
503 clock-names = "ipg", "ahb";
504 #dma-cells = <3>;
505 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
506 };
507
508 sdma2: dma-controller@302c0000 {
958c6014 509 compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma";
6c3debcb
AH		 510 reg = <0x302c0000 0x10000>;
511 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
512 clocks = <&clk IMX8MN_CLK_SDMA2_ROOT>,
513 <&clk IMX8MN_CLK_SDMA2_ROOT>;
514 clock-names = "ipg", "ahb";
515 #dma-cells = <3>;
516 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
517 };
518
519 iomuxc: pinctrl@30330000 {
520 compatible = "fsl,imx8mn-iomuxc";
521 reg = <0x30330000 0x10000>;
522 };
523
524 gpr: iomuxc-gpr@30340000 {
525 compatible = "fsl,imx8mn-iomuxc-gpr", "syscon";
526 reg = <0x30340000 0x10000>;
527 };
528
12fa1078 529 ocotp: efuse@30350000 {
2bad8c48 530 compatible = "fsl,imx8mn-ocotp", "fsl,imx8mm-ocotp", "syscon";
6c3debcb
AH		 531 reg = <0x30350000 0x10000>;
532 clocks = <&clk IMX8MN_CLK_OCOTP_ROOT>;
01c49314
AH		 533 #address-cells = <1>;
534 #size-cells = <1>;
535
cbff2379
AG		 536 imx8mn_uid: unique-id@410 {
537 reg = <0x4 0x8>;
538 };
539
01c49314
AH		 540 cpu_speed_grade: speed-grade@10 {
541 reg = <0x10 4>;
542 };
066438ae
JZ		 543
544 fec_mac_address: mac-address@90 {
545 reg = <0x90 6>;
546 };
6c3debcb
AH		 547 };
548
549 anatop: anatop@30360000 {
550 compatible = "fsl,imx8mn-anatop", "fsl,imx8mm-anatop",
0f93eb28 551 "syscon";
6c3debcb
AH		 552 reg = <0x30360000 0x10000>;
553 };
554
555 snvs: snvs@30370000 {
556 compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd";
557 reg = <0x30370000 0x10000>;
558
559 snvs_rtc: snvs-rtc-lp {
560 compatible = "fsl,sec-v4.0-mon-rtc-lp";
561 regmap = <&snvs>;
562 offset = <0x34>;
563 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
564 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
42ef961b 565 clocks = <&clk IMX8MN_CLK_SNVS_ROOT>;
6c3debcb
AH		 566 clock-names = "snvs-rtc";
567 };
568
569 snvs_pwrkey: snvs-powerkey {
570 compatible = "fsl,sec-v4.0-pwrkey";
571 regmap = <&snvs>;
572 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
c2a2f446
AH		 573 clocks = <&clk IMX8MN_CLK_SNVS_ROOT>;
574 clock-names = "snvs-pwrkey";
6c3debcb
AH		 575 linux,keycode = <KEY_POWER>;
576 wakeup-source;
577 status = "disabled";
578 };
579 };
580
581 clk: clock-controller@30380000 {
582 compatible = "fsl,imx8mn-ccm";
583 reg = <0x30380000 0x10000>;
584 #clock-cells = <1>;
585 clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>,
586 <&clk_ext3>, <&clk_ext4>;
587 clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
588 "clk_ext3", "clk_ext4";
9e6337e6
PF		 589 assigned-clocks = <&clk IMX8MN_CLK_A53_SRC>,
590 <&clk IMX8MN_CLK_A53_CORE>,
591 <&clk IMX8MN_CLK_NOC>,
53458f86
PF		 592 <&clk IMX8MN_CLK_AUDIO_AHB>,
593 <&clk IMX8MN_CLK_IPG_AUDIO_ROOT>,
26442c79
SW		 594 <&clk IMX8MN_SYS_PLL3>,
595 <&clk IMX8MN_AUDIO_PLL1>,
596 <&clk IMX8MN_AUDIO_PLL2>;
9e6337e6
PF		 597 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_800M>,
598 <&clk IMX8MN_ARM_PLL_OUT>,
599 <&clk IMX8MN_SYS_PLL3_OUT>,
53458f86 600 <&clk IMX8MN_SYS_PLL1_800M>;
9e6337e6 601 assigned-clock-rates = <0>, <0>, <0>,
53458f86
PF		 602 <400000000>,
603 <400000000>,
26442c79
SW		 604 <600000000>,
605 <393216000>,
606 <361267200>;
6c3debcb
AH		 607 };
608
609 src: reset-controller@30390000 {
23b80c20 610 compatible = "fsl,imx8mn-src", "fsl,imx8mq-src", "syscon";
6c3debcb
AH		 611 reg = <0x30390000 0x10000>;
612 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
613 #reset-cells = <1>;
614 };
615 };
616
617 aips2: bus@30400000 {
dc3efc6f 618 compatible = "fsl,aips-bus", "simple-bus";
921a6845 619 reg = <0x30400000 0x400000>;
6c3debcb
AH		 620 #address-cells = <1>;
621 #size-cells = <1>;
622 ranges;
623
624 pwm1: pwm@30660000 {
625 compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm";
626 reg = <0x30660000 0x10000>;
627 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
628 clocks = <&clk IMX8MN_CLK_PWM1_ROOT>,
629 <&clk IMX8MN_CLK_PWM1_ROOT>;
630 clock-names = "ipg", "per";
631 #pwm-cells = <2>;
632 status = "disabled";
633 };
634
635 pwm2: pwm@30670000 {
636 compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm";
637 reg = <0x30670000 0x10000>;
638 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
639 clocks = <&clk IMX8MN_CLK_PWM2_ROOT>,
640 <&clk IMX8MN_CLK_PWM2_ROOT>;
641 clock-names = "ipg", "per";
642 #pwm-cells = <2>;
643 status = "disabled";
644 };
645
646 pwm3: pwm@30680000 {
647 compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm";
648 reg = <0x30680000 0x10000>;
649 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
650 clocks = <&clk IMX8MN_CLK_PWM3_ROOT>,
651 <&clk IMX8MN_CLK_PWM3_ROOT>;
652 clock-names = "ipg", "per";
653 #pwm-cells = <2>;
654 status = "disabled";
655 };
656
657 pwm4: pwm@30690000 {
658 compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm";
659 reg = <0x30690000 0x10000>;
660 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
661 clocks = <&clk IMX8MN_CLK_PWM4_ROOT>,
662 <&clk IMX8MN_CLK_PWM4_ROOT>;
663 clock-names = "ipg", "per";
664 #pwm-cells = <2>;
665 status = "disabled";
666 };
c4a21269
AH		 667
668 system_counter: timer@306a0000 {
669 compatible = "nxp,sysctr-timer";
670 reg = <0x306a0000 0x20000>;
671 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
672 clocks = <&osc_24m>;
673 clock-names = "per";
674 };
6c3debcb
AH		 675 };
676
677 aips3: bus@30800000 {
dc3efc6f 678 compatible = "fsl,aips-bus", "simple-bus";
921a6845 679 reg = <0x30800000 0x400000>;
6c3debcb
AH		 680 #address-cells = <1>;
681 #size-cells = <1>;
682 ranges;
683
684 ecspi1: spi@30820000 {
685 compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi";
686 #address-cells = <1>;
687 #size-cells = <0>;
688 reg = <0x30820000 0x10000>;
689 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
690 clocks = <&clk IMX8MN_CLK_ECSPI1_ROOT>,
691 <&clk IMX8MN_CLK_ECSPI1_ROOT>;
692 clock-names = "ipg", "per";
693 dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
694 dma-names = "rx", "tx";
695 status = "disabled";
696 };
697
698 ecspi2: spi@30830000 {
699 compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi";
700 #address-cells = <1>;
701 #size-cells = <0>;
702 reg = <0x30830000 0x10000>;
703 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
704 clocks = <&clk IMX8MN_CLK_ECSPI2_ROOT>,
705 <&clk IMX8MN_CLK_ECSPI2_ROOT>;
706 clock-names = "ipg", "per";
707 dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;
708 dma-names = "rx", "tx";
709 status = "disabled";
710 };
711
712 ecspi3: spi@30840000 {
713 compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi";
714 #address-cells = <1>;
715 #size-cells = <0>;
716 reg = <0x30840000 0x10000>;
717 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
718 clocks = <&clk IMX8MN_CLK_ECSPI3_ROOT>,
719 <&clk IMX8MN_CLK_ECSPI3_ROOT>;
720 clock-names = "ipg", "per";
721 dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;
722 dma-names = "rx", "tx";
723 status = "disabled";
724 };
725
726 uart1: serial@30860000 {
727 compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
728 reg = <0x30860000 0x10000>;
729 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
730 clocks = <&clk IMX8MN_CLK_UART1_ROOT>,
731 <&clk IMX8MN_CLK_UART1_ROOT>;
732 clock-names = "ipg", "per";
733 dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;
734 dma-names = "rx", "tx";
735 status = "disabled";
736 };
737
738 uart3: serial@30880000 {
739 compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
740 reg = <0x30880000 0x10000>;
741 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
742 clocks = <&clk IMX8MN_CLK_UART3_ROOT>,
743 <&clk IMX8MN_CLK_UART3_ROOT>;
744 clock-names = "ipg", "per";
745 dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;
746 dma-names = "rx", "tx";
747 status = "disabled";
748 };
749
750 uart2: serial@30890000 {
751 compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
752 reg = <0x30890000 0x10000>;
753 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
754 clocks = <&clk IMX8MN_CLK_UART2_ROOT>,
755 <&clk IMX8MN_CLK_UART2_ROOT>;
756 clock-names = "ipg", "per";
757 status = "disabled";
758 };
759
aad24175
HG		 760 crypto: crypto@30900000 {
761 compatible = "fsl,sec-v4.0";
762 #address-cells = <1>;
763 #size-cells = <1>;
764 reg = <0x30900000 0x40000>;
765 ranges = <0 0x30900000 0x40000>;
766 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
767 clocks = <&clk IMX8MN_CLK_AHB>,
768 <&clk IMX8MN_CLK_IPG_ROOT>;
769 clock-names = "aclk", "ipg";
770
f5ff5a21 771 sec_jr0: jr@1000 {
aad24175
HG		 772 compatible = "fsl,sec-v4.0-job-ring";
773 reg = <0x1000 0x1000>;
774 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
775 };
776
f5ff5a21 777 sec_jr1: jr@2000 {
aad24175
HG		 778 compatible = "fsl,sec-v4.0-job-ring";
779 reg = <0x2000 0x1000>;
780 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
781 };
782
f5ff5a21 783 sec_jr2: jr@3000 {
aad24175
HG		 784 compatible = "fsl,sec-v4.0-job-ring";
785 reg = <0x3000 0x1000>;
786 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
787 };
788 };
789
6c3debcb
AH		 790 i2c1: i2c@30a20000 {
791 compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c";
792 #address-cells = <1>;
793 #size-cells = <0>;
794 reg = <0x30a20000 0x10000>;
795 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
796 clocks = <&clk IMX8MN_CLK_I2C1_ROOT>;
797 status = "disabled";
798 };
799
800 i2c2: i2c@30a30000 {
801 compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c";
802 #address-cells = <1>;
803 #size-cells = <0>;
804 reg = <0x30a30000 0x10000>;
805 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
806 clocks = <&clk IMX8MN_CLK_I2C2_ROOT>;
807 status = "disabled";
808 };
809
810 i2c3: i2c@30a40000 {
811 #address-cells = <1>;
812 #size-cells = <0>;
813 compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c";
814 reg = <0x30a40000 0x10000>;
815 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
816 clocks = <&clk IMX8MN_CLK_I2C3_ROOT>;
817 status = "disabled";
818 };
819
820 i2c4: i2c@30a50000 {
821 compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c";
822 #address-cells = <1>;
823 #size-cells = <0>;
824 reg = <0x30a50000 0x10000>;
825 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
826 clocks = <&clk IMX8MN_CLK_I2C4_ROOT>;
827 status = "disabled";
828 };
829
830 uart4: serial@30a60000 {
831 compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
832 reg = <0x30a60000 0x10000>;
833 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
834 clocks = <&clk IMX8MN_CLK_UART4_ROOT>,
835 <&clk IMX8MN_CLK_UART4_ROOT>;
836 clock-names = "ipg", "per";
837 dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>;
838 dma-names = "rx", "tx";
839 status = "disabled";
840 };
841
bbfc59be
PF		 842 mu: mailbox@30aa0000 {
843 compatible = "fsl,imx8mn-mu", "fsl,imx6sx-mu";
844 reg = <0x30aa0000 0x10000>;
845 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
846 clocks = <&clk IMX8MN_CLK_MU_ROOT>;
847 #mbox-cells = <2>;
848 };
849
6c3debcb
AH		 850 usdhc1: mmc@30b40000 {
851 compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc";
852 reg = <0x30b40000 0x10000>;
853 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
ea65aba8 854 clocks = <&clk IMX8MN_CLK_IPG_ROOT>,
6c3debcb
AH		 855 <&clk IMX8MN_CLK_NAND_USDHC_BUS>,
856 <&clk IMX8MN_CLK_USDHC1_ROOT>;
857 clock-names = "ipg", "ahb", "per";
6c3debcb
AH		 858 fsl,tuning-start-tap = <20>;
859 fsl,tuning-step= <2>;
860 bus-width = <4>;
861 status = "disabled";
862 };
863
864 usdhc2: mmc@30b50000 {
865 compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc";
866 reg = <0x30b50000 0x10000>;
867 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
ea65aba8 868 clocks = <&clk IMX8MN_CLK_IPG_ROOT>,
6c3debcb
AH		 869 <&clk IMX8MN_CLK_NAND_USDHC_BUS>,
870 <&clk IMX8MN_CLK_USDHC2_ROOT>;
871 clock-names = "ipg", "ahb", "per";
872 fsl,tuning-start-tap = <20>;
873 fsl,tuning-step= <2>;
874 bus-width = <4>;
875 status = "disabled";
876 };
877
878 usdhc3: mmc@30b60000 {
879 compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc";
880 reg = <0x30b60000 0x10000>;
881 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
ea65aba8 882 clocks = <&clk IMX8MN_CLK_IPG_ROOT>,
6c3debcb
AH		 883 <&clk IMX8MN_CLK_NAND_USDHC_BUS>,
884 <&clk IMX8MN_CLK_USDHC3_ROOT>;
885 clock-names = "ipg", "ahb", "per";
6c3debcb
AH		 886 fsl,tuning-start-tap = <20>;
887 fsl,tuning-step= <2>;
888 bus-width = <4>;
889 status = "disabled";
890 };
891
892 sdma1: dma-controller@30bd0000 {
958c6014 893 compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma";
6c3debcb
AH		 894 reg = <0x30bd0000 0x10000>;
895 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
896 clocks = <&clk IMX8MN_CLK_SDMA1_ROOT>,
15ddc3e1 897 <&clk IMX8MN_CLK_AHB>;
6c3debcb
AH		 898 clock-names = "ipg", "ahb";
899 #dma-cells = <3>;
900 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
901 };
902
903 fec1: ethernet@30be0000 {
904 compatible = "fsl,imx8mn-fec", "fsl,imx6sx-fec";
905 reg = <0x30be0000 0x10000>;
906 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
907 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
d3762a47
FE		 908 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
909 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
6c3debcb
AH		 910 clocks = <&clk IMX8MN_CLK_ENET1_ROOT>,
911 <&clk IMX8MN_CLK_ENET1_ROOT>,
912 <&clk IMX8MN_CLK_ENET_TIMER>,
913 <&clk IMX8MN_CLK_ENET_REF>,
914 <&clk IMX8MN_CLK_ENET_PHY_REF>;
915 clock-names = "ipg", "ahb", "ptp",
916 "enet_clk_ref", "enet_out";
917 assigned-clocks = <&clk IMX8MN_CLK_ENET_AXI>,
918 <&clk IMX8MN_CLK_ENET_TIMER>,
919 <&clk IMX8MN_CLK_ENET_REF>,
70eacf42 920 <&clk IMX8MN_CLK_ENET_PHY_REF>;
6c3debcb
AH		 921 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_266M>,
922 <&clk IMX8MN_SYS_PLL2_100M>,
70eacf42
JZ		 923 <&clk IMX8MN_SYS_PLL2_125M>,
924 <&clk IMX8MN_SYS_PLL2_50M>;
925 assigned-clock-rates = <0>, <100000000>, <125000000>, <0>;
6c3debcb
AH		 926 fsl,num-tx-queues = <3>;
927 fsl,num-rx-queues = <3>;
066438ae
JZ		 928 nvmem-cells = <&fec_mac_address>;
929 nvmem-cell-names = "mac-address";
930 nvmem_macaddr_swap;
afe99354 931 fsl,stop-mode = <&gpr 0x10 3>;
6c3debcb
AH		 932 status = "disabled";
933 };
934
935 };
936
937 aips4: bus@32c00000 {
dc3efc6f 938 compatible = "fsl,aips-bus", "simple-bus";
921a6845 939 reg = <0x32c00000 0x400000>;
6c3debcb
AH		 940 #address-cells = <1>;
941 #size-cells = <1>;
942 ranges;
943
944 usbotg1: usb@32e40000 {
945 compatible = "fsl,imx8mn-usb", "fsl,imx7d-usb";
946 reg = <0x32e40000 0x200>;
947 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
948 clocks = <&clk IMX8MN_CLK_USB1_CTRL_ROOT>;
949 clock-names = "usb1_ctrl_root_clk";
d51cb99c
LJ		 950 assigned-clocks = <&clk IMX8MN_CLK_USB_BUS>;
951 assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_500M>;
6c3debcb
AH		 952 fsl,usbphy = <&usbphynop1>;
953 fsl,usbmisc = <&usbmisc1 0>;
954 status = "disabled";
955 };
956
957 usbmisc1: usbmisc@32e40200 {
958 compatible = "fsl,imx8mn-usbmisc", "fsl,imx7d-usbmisc";
959 #index-cells = <1>;
960 reg = <0x32e40200 0x200>;
961 };
6c3debcb
AH		 962 };
963
964 dma_apbh: dma-controller@33000000 {
965 compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh";
966 reg = <0x33000000 0x2000>;
967 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
968 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
969 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
970 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
971 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
972 #dma-cells = <1>;
973 dma-channels = <4>;
974 clocks = <&clk IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK>;
975 };
976
977 gpmi: nand-controller@33002000 {
978 compatible = "fsl,imx8mn-gpmi-nand", "fsl,imx7d-gpmi-nand";
979 #address-cells = <1>;
980 #size-cells = <1>;
981 reg = <0x33002000 0x2000>, <0x33004000 0x4000>;
982 reg-names = "gpmi-nand", "bch";
983 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
984 interrupt-names = "bch";
985 clocks = <&clk IMX8MN_CLK_NAND_ROOT>,
986 <&clk IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK>;
987 clock-names = "gpmi_io", "gpmi_bch_apb";
988 dmas = <&dma_apbh 0>;
989 dma-names = "rx-tx";
990 status = "disabled";
991 };
992
993 gic: interrupt-controller@38800000 {
994 compatible = "arm,gic-v3";
995 reg = <0x38800000 0x10000>,
996 <0x38880000 0xc0000>;
997 #interrupt-cells = <3>;
998 interrupt-controller;
999 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
1000 };
2d8e0747 1001
0376f6ec
LC		 1002 ddrc: memory-controller@3d400000 {
1003 compatible = "fsl,imx8mn-ddrc", "fsl,imx8m-ddrc";
1004 reg = <0x3d400000 0x400000>;
1005 clock-names = "core", "pll", "alt", "apb";
1006 clocks = <&clk IMX8MN_CLK_DRAM_CORE>,
1007 <&clk IMX8MN_DRAM_PLL>,
1008 <&clk IMX8MN_CLK_DRAM_ALT>,
1009 <&clk IMX8MN_CLK_DRAM_APB>;
1010 };
1011
2d8e0747
JZ		 1012 ddr-pmu@3d800000 {
1013 compatible = "fsl,imx8mn-ddr-pmu", "fsl,imx8m-ddr-pmu";
1014 reg = <0x3d800000 0x400000>;
1015 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1016 };
6c3debcb
AH		 1017 };
1018
1019 usbphynop1: usbphynop1 {
1020 compatible = "usb-nop-xceiv";
1021 clocks = <&clk IMX8MN_CLK_USB_PHY_REF>;
1022 assigned-clocks = <&clk IMX8MN_CLK_USB_PHY_REF>;
1023 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_100M>;
1024 clock-names = "main_clk";
1025 };
6c3debcb 1026};
Linux 6.x block layer and io_uring tree(s)