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arm64: dts: imx8mn: Add gpio-ranges property
[linux-2.6-block.git] / arch / arm64 / boot / dts / freescale / imx8mn.dtsi
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6c3debcb
AH		 1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2019 NXP
4 */
5
6#include <dt-bindings/clock/imx8mn-clock.h>
7#include <dt-bindings/gpio/gpio.h>
8#include <dt-bindings/input/input.h>
9#include <dt-bindings/interrupt-controller/arm-gic.h>
10
11#include "imx8mn-pinfunc.h"
12
13/ {
14 compatible = "fsl,imx8mn";
15 interrupt-parent = <&gic>;
16 #address-cells = <2>;
17 #size-cells = <2>;
18
19 aliases {
20 ethernet0 = &fec1;
21 gpio0 = &gpio1;
22 gpio1 = &gpio2;
23 gpio2 = &gpio3;
24 gpio3 = &gpio4;
25 gpio4 = &gpio5;
26 i2c0 = &i2c1;
27 i2c1 = &i2c2;
28 i2c2 = &i2c3;
29 i2c3 = &i2c4;
30 mmc0 = &usdhc1;
31 mmc1 = &usdhc2;
32 mmc2 = &usdhc3;
33 serial0 = &uart1;
34 serial1 = &uart2;
35 serial2 = &uart3;
36 serial3 = &uart4;
37 spi0 = &ecspi1;
38 spi1 = &ecspi2;
39 spi2 = &ecspi3;
40 };
41
42 cpus {
43 #address-cells = <1>;
44 #size-cells = <0>;
45
46 A53_0: cpu@0 {
47 device_type = "cpu";
48 compatible = "arm,cortex-a53";
49 reg = <0x0>;
50 clock-latency = <61036>;
51 clocks = <&clk IMX8MN_CLK_ARM>;
52 enable-method = "psci";
53 next-level-cache = <&A53_L2>;
54 };
55
56 A53_1: cpu@1 {
57 device_type = "cpu";
58 compatible = "arm,cortex-a53";
59 reg = <0x1>;
60 clock-latency = <61036>;
61 clocks = <&clk IMX8MN_CLK_ARM>;
62 enable-method = "psci";
63 next-level-cache = <&A53_L2>;
64 };
65
66 A53_2: cpu@2 {
67 device_type = "cpu";
68 compatible = "arm,cortex-a53";
69 reg = <0x2>;
70 clock-latency = <61036>;
71 clocks = <&clk IMX8MN_CLK_ARM>;
72 enable-method = "psci";
73 next-level-cache = <&A53_L2>;
74 };
75
76 A53_3: cpu@3 {
77 device_type = "cpu";
78 compatible = "arm,cortex-a53";
79 reg = <0x3>;
80 clock-latency = <61036>;
81 clocks = <&clk IMX8MN_CLK_ARM>;
82 enable-method = "psci";
83 next-level-cache = <&A53_L2>;
84 };
85
86 A53_L2: l2-cache0 {
87 compatible = "cache";
88 };
89 };
90
91 memory@40000000 {
92 device_type = "memory";
93 reg = <0x0 0x40000000 0 0x80000000>;
94 };
95
96 osc_32k: clock-osc-32k {
97 compatible = "fixed-clock";
98 #clock-cells = <0>;
99 clock-frequency = <32768>;
100 clock-output-names = "osc_32k";
101 };
102
103 osc_24m: clock-osc-24m {
104 compatible = "fixed-clock";
105 #clock-cells = <0>;
106 clock-frequency = <24000000>;
107 clock-output-names = "osc_24m";
108 };
109
110 clk_ext1: clock-ext1 {
111 compatible = "fixed-clock";
112 #clock-cells = <0>;
113 clock-frequency = <133000000>;
114 clock-output-names = "clk_ext1";
115 };
116
117 clk_ext2: clock-ext2 {
118 compatible = "fixed-clock";
119 #clock-cells = <0>;
120 clock-frequency = <133000000>;
121 clock-output-names = "clk_ext2";
122 };
123
124 clk_ext3: clock-ext3 {
125 compatible = "fixed-clock";
126 #clock-cells = <0>;
127 clock-frequency = <133000000>;
128 clock-output-names = "clk_ext3";
129 };
130
131 clk_ext4: clock-ext4 {
132 compatible = "fixed-clock";
133 #clock-cells = <0>;
134 clock-frequency= <133000000>;
135 clock-output-names = "clk_ext4";
136 };
137
138 psci {
139 compatible = "arm,psci-1.0";
140 method = "smc";
141 };
142
143 timer {
144 compatible = "arm,armv8-timer";
145 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
146 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
147 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
148 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
149 clock-frequency = <8000000>;
150 arm,no-tick-in-suspend;
151 };
152
153 soc@0 {
154 compatible = "simple-bus";
155 #address-cells = <1>;
156 #size-cells = <1>;
157 ranges = <0x0 0x0 0x0 0x3e000000>;
158
159 aips1: bus@30000000 {
160 compatible = "fsl,aips-bus", "simple-bus";
161 reg = <0x30000000 0x400000>;
162 #address-cells = <1>;
163 #size-cells = <1>;
164 ranges;
165
166 gpio1: gpio@30200000 {
167 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
168 reg = <0x30200000 0x10000>;
169 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
170 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
171 clocks = <&clk IMX8MN_CLK_GPIO1_ROOT>;
172 gpio-controller;
173 #gpio-cells = <2>;
174 interrupt-controller;
175 #interrupt-cells = <2>;
ee8696be 176 gpio-ranges = <&iomuxc 0 10 30>;
6c3debcb
AH		 177 };
178
179 gpio2: gpio@30210000 {
180 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
181 reg = <0x30210000 0x10000>;
182 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
183 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
184 clocks = <&clk IMX8MN_CLK_GPIO2_ROOT>;
185 gpio-controller;
186 #gpio-cells = <2>;
187 interrupt-controller;
188 #interrupt-cells = <2>;
ee8696be 189 gpio-ranges = <&iomuxc 0 40 21>;
6c3debcb
AH		 190 };
191
192 gpio3: gpio@30220000 {
193 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
194 reg = <0x30220000 0x10000>;
195 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
196 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
197 clocks = <&clk IMX8MN_CLK_GPIO3_ROOT>;
198 gpio-controller;
199 #gpio-cells = <2>;
200 interrupt-controller;
201 #interrupt-cells = <2>;
ee8696be 202 gpio-ranges = <&iomuxc 0 61 26>;
6c3debcb
AH		 203 };
204
205 gpio4: gpio@30230000 {
206 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
207 reg = <0x30230000 0x10000>;
208 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
209 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
210 clocks = <&clk IMX8MN_CLK_GPIO4_ROOT>;
211 gpio-controller;
212 #gpio-cells = <2>;
213 interrupt-controller;
214 #interrupt-cells = <2>;
ee8696be 215 gpio-ranges = <&iomuxc 21 108 11>;
6c3debcb
AH		 216 };
217
218 gpio5: gpio@30240000 {
219 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
220 reg = <0x30240000 0x10000>;
221 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
222 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
223 clocks = <&clk IMX8MN_CLK_GPIO5_ROOT>;
224 gpio-controller;
225 #gpio-cells = <2>;
226 interrupt-controller;
227 #interrupt-cells = <2>;
ee8696be 228 gpio-ranges = <&iomuxc 0 119 30>;
6c3debcb
AH		 229 };
230
231 wdog1: watchdog@30280000 {
232 compatible = "fsl,imx8mn-wdt", "fsl,imx21-wdt";
233 reg = <0x30280000 0x10000>;
234 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
235 clocks = <&clk IMX8MN_CLK_WDOG1_ROOT>;
236 status = "disabled";
237 };
238
239 wdog2: watchdog@30290000 {
240 compatible = "fsl,imx8mn-wdt", "fsl,imx21-wdt";
241 reg = <0x30290000 0x10000>;
242 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
243 clocks = <&clk IMX8MN_CLK_WDOG2_ROOT>;
244 status = "disabled";
245 };
246
247 wdog3: watchdog@302a0000 {
248 compatible = "fsl,imx8mn-wdt", "fsl,imx21-wdt";
249 reg = <0x302a0000 0x10000>;
250 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
251 clocks = <&clk IMX8MN_CLK_WDOG3_ROOT>;
252 status = "disabled";
253 };
254
255 sdma3: dma-controller@302b0000 {
256 compatible = "fsl,imx8mn-sdma", "fsl,imx7d-sdma";
257 reg = <0x302b0000 0x10000>;
258 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
259 clocks = <&clk IMX8MN_CLK_SDMA3_ROOT>,
260 <&clk IMX8MN_CLK_SDMA3_ROOT>;
261 clock-names = "ipg", "ahb";
262 #dma-cells = <3>;
263 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
264 };
265
266 sdma2: dma-controller@302c0000 {
267 compatible = "fsl,imx8mn-sdma", "fsl,imx7d-sdma";
268 reg = <0x302c0000 0x10000>;
269 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
270 clocks = <&clk IMX8MN_CLK_SDMA2_ROOT>,
271 <&clk IMX8MN_CLK_SDMA2_ROOT>;
272 clock-names = "ipg", "ahb";
273 #dma-cells = <3>;
274 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
275 };
276
277 iomuxc: pinctrl@30330000 {
278 compatible = "fsl,imx8mn-iomuxc";
279 reg = <0x30330000 0x10000>;
280 };
281
282 gpr: iomuxc-gpr@30340000 {
283 compatible = "fsl,imx8mn-iomuxc-gpr", "syscon";
284 reg = <0x30340000 0x10000>;
285 };
286
287 ocotp: ocotp-ctrl@30350000 {
288 compatible = "fsl,imx8mn-ocotp", "fsl,imx7d-ocotp", "syscon";
289 reg = <0x30350000 0x10000>;
290 clocks = <&clk IMX8MN_CLK_OCOTP_ROOT>;
291 };
292
293 anatop: anatop@30360000 {
294 compatible = "fsl,imx8mn-anatop", "fsl,imx8mm-anatop",
295 "syscon", "simple-bus";
296 reg = <0x30360000 0x10000>;
297 };
298
299 snvs: snvs@30370000 {
300 compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd";
301 reg = <0x30370000 0x10000>;
302
303 snvs_rtc: snvs-rtc-lp {
304 compatible = "fsl,sec-v4.0-mon-rtc-lp";
305 regmap = <&snvs>;
306 offset = <0x34>;
307 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
308 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
309 clock-names = "snvs-rtc";
310 };
311
312 snvs_pwrkey: snvs-powerkey {
313 compatible = "fsl,sec-v4.0-pwrkey";
314 regmap = <&snvs>;
315 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
316 linux,keycode = <KEY_POWER>;
317 wakeup-source;
318 status = "disabled";
319 };
320 };
321
322 clk: clock-controller@30380000 {
323 compatible = "fsl,imx8mn-ccm";
324 reg = <0x30380000 0x10000>;
325 #clock-cells = <1>;
326 clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>,
327 <&clk_ext3>, <&clk_ext4>;
328 clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
329 "clk_ext3", "clk_ext4";
330 };
331
332 src: reset-controller@30390000 {
333 compatible = "fsl,imx8mn-src", "syscon";
334 reg = <0x30390000 0x10000>;
335 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
336 #reset-cells = <1>;
337 };
338 };
339
340 aips2: bus@30400000 {
341 compatible = "fsl,aips-bus", "simple-bus";
342 reg = <0x30400000 0x400000>;
343 #address-cells = <1>;
344 #size-cells = <1>;
345 ranges;
346
347 pwm1: pwm@30660000 {
348 compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm";
349 reg = <0x30660000 0x10000>;
350 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
351 clocks = <&clk IMX8MN_CLK_PWM1_ROOT>,
352 <&clk IMX8MN_CLK_PWM1_ROOT>;
353 clock-names = "ipg", "per";
354 #pwm-cells = <2>;
355 status = "disabled";
356 };
357
358 pwm2: pwm@30670000 {
359 compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm";
360 reg = <0x30670000 0x10000>;
361 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
362 clocks = <&clk IMX8MN_CLK_PWM2_ROOT>,
363 <&clk IMX8MN_CLK_PWM2_ROOT>;
364 clock-names = "ipg", "per";
365 #pwm-cells = <2>;
366 status = "disabled";
367 };
368
369 pwm3: pwm@30680000 {
370 compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm";
371 reg = <0x30680000 0x10000>;
372 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
373 clocks = <&clk IMX8MN_CLK_PWM3_ROOT>,
374 <&clk IMX8MN_CLK_PWM3_ROOT>;
375 clock-names = "ipg", "per";
376 #pwm-cells = <2>;
377 status = "disabled";
378 };
379
380 pwm4: pwm@30690000 {
381 compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm";
382 reg = <0x30690000 0x10000>;
383 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
384 clocks = <&clk IMX8MN_CLK_PWM4_ROOT>,
385 <&clk IMX8MN_CLK_PWM4_ROOT>;
386 clock-names = "ipg", "per";
387 #pwm-cells = <2>;
388 status = "disabled";
389 };
390 };
391
392 aips3: bus@30800000 {
393 compatible = "fsl,aips-bus", "simple-bus";
394 reg = <0x30800000 0x400000>;
395 #address-cells = <1>;
396 #size-cells = <1>;
397 ranges;
398
399 ecspi1: spi@30820000 {
400 compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi";
401 #address-cells = <1>;
402 #size-cells = <0>;
403 reg = <0x30820000 0x10000>;
404 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
405 clocks = <&clk IMX8MN_CLK_ECSPI1_ROOT>,
406 <&clk IMX8MN_CLK_ECSPI1_ROOT>;
407 clock-names = "ipg", "per";
408 dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
409 dma-names = "rx", "tx";
410 status = "disabled";
411 };
412
413 ecspi2: spi@30830000 {
414 compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi";
415 #address-cells = <1>;
416 #size-cells = <0>;
417 reg = <0x30830000 0x10000>;
418 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
419 clocks = <&clk IMX8MN_CLK_ECSPI2_ROOT>,
420 <&clk IMX8MN_CLK_ECSPI2_ROOT>;
421 clock-names = "ipg", "per";
422 dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;
423 dma-names = "rx", "tx";
424 status = "disabled";
425 };
426
427 ecspi3: spi@30840000 {
428 compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi";
429 #address-cells = <1>;
430 #size-cells = <0>;
431 reg = <0x30840000 0x10000>;
432 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
433 clocks = <&clk IMX8MN_CLK_ECSPI3_ROOT>,
434 <&clk IMX8MN_CLK_ECSPI3_ROOT>;
435 clock-names = "ipg", "per";
436 dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;
437 dma-names = "rx", "tx";
438 status = "disabled";
439 };
440
441 uart1: serial@30860000 {
442 compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
443 reg = <0x30860000 0x10000>;
444 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
445 clocks = <&clk IMX8MN_CLK_UART1_ROOT>,
446 <&clk IMX8MN_CLK_UART1_ROOT>;
447 clock-names = "ipg", "per";
448 dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;
449 dma-names = "rx", "tx";
450 status = "disabled";
451 };
452
453 uart3: serial@30880000 {
454 compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
455 reg = <0x30880000 0x10000>;
456 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
457 clocks = <&clk IMX8MN_CLK_UART3_ROOT>,
458 <&clk IMX8MN_CLK_UART3_ROOT>;
459 clock-names = "ipg", "per";
460 dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;
461 dma-names = "rx", "tx";
462 status = "disabled";
463 };
464
465 uart2: serial@30890000 {
466 compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
467 reg = <0x30890000 0x10000>;
468 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
469 clocks = <&clk IMX8MN_CLK_UART2_ROOT>,
470 <&clk IMX8MN_CLK_UART2_ROOT>;
471 clock-names = "ipg", "per";
472 status = "disabled";
473 };
474
475 i2c1: i2c@30a20000 {
476 compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c";
477 #address-cells = <1>;
478 #size-cells = <0>;
479 reg = <0x30a20000 0x10000>;
480 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
481 clocks = <&clk IMX8MN_CLK_I2C1_ROOT>;
482 status = "disabled";
483 };
484
485 i2c2: i2c@30a30000 {
486 compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c";
487 #address-cells = <1>;
488 #size-cells = <0>;
489 reg = <0x30a30000 0x10000>;
490 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
491 clocks = <&clk IMX8MN_CLK_I2C2_ROOT>;
492 status = "disabled";
493 };
494
495 i2c3: i2c@30a40000 {
496 #address-cells = <1>;
497 #size-cells = <0>;
498 compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c";
499 reg = <0x30a40000 0x10000>;
500 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
501 clocks = <&clk IMX8MN_CLK_I2C3_ROOT>;
502 status = "disabled";
503 };
504
505 i2c4: i2c@30a50000 {
506 compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c";
507 #address-cells = <1>;
508 #size-cells = <0>;
509 reg = <0x30a50000 0x10000>;
510 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
511 clocks = <&clk IMX8MN_CLK_I2C4_ROOT>;
512 status = "disabled";
513 };
514
515 uart4: serial@30a60000 {
516 compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
517 reg = <0x30a60000 0x10000>;
518 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
519 clocks = <&clk IMX8MN_CLK_UART4_ROOT>,
520 <&clk IMX8MN_CLK_UART4_ROOT>;
521 clock-names = "ipg", "per";
522 dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>;
523 dma-names = "rx", "tx";
524 status = "disabled";
525 };
526
527 usdhc1: mmc@30b40000 {
528 compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc";
529 reg = <0x30b40000 0x10000>;
530 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
531 clocks = <&clk IMX8MN_CLK_DUMMY>,
532 <&clk IMX8MN_CLK_NAND_USDHC_BUS>,
533 <&clk IMX8MN_CLK_USDHC1_ROOT>;
534 clock-names = "ipg", "ahb", "per";
535 assigned-clocks = <&clk IMX8MN_CLK_USDHC1>;
536 assigned-clock-rates = <400000000>;
537 fsl,tuning-start-tap = <20>;
538 fsl,tuning-step= <2>;
539 bus-width = <4>;
540 status = "disabled";
541 };
542
543 usdhc2: mmc@30b50000 {
544 compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc";
545 reg = <0x30b50000 0x10000>;
546 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
547 clocks = <&clk IMX8MN_CLK_DUMMY>,
548 <&clk IMX8MN_CLK_NAND_USDHC_BUS>,
549 <&clk IMX8MN_CLK_USDHC2_ROOT>;
550 clock-names = "ipg", "ahb", "per";
551 fsl,tuning-start-tap = <20>;
552 fsl,tuning-step= <2>;
553 bus-width = <4>;
554 status = "disabled";
555 };
556
557 usdhc3: mmc@30b60000 {
558 compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc";
559 reg = <0x30b60000 0x10000>;
560 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
561 clocks = <&clk IMX8MN_CLK_DUMMY>,
562 <&clk IMX8MN_CLK_NAND_USDHC_BUS>,
563 <&clk IMX8MN_CLK_USDHC3_ROOT>;
564 clock-names = "ipg", "ahb", "per";
565 assigned-clocks = <&clk IMX8MN_CLK_USDHC3_ROOT>;
566 assigned-clock-rates = <400000000>;
567 fsl,tuning-start-tap = <20>;
568 fsl,tuning-step= <2>;
569 bus-width = <4>;
570 status = "disabled";
571 };
572
573 sdma1: dma-controller@30bd0000 {
574 compatible = "fsl,imx8mn-sdma", "fsl,imx7d-sdma";
575 reg = <0x30bd0000 0x10000>;
576 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
577 clocks = <&clk IMX8MN_CLK_SDMA1_ROOT>,
578 <&clk IMX8MN_CLK_SDMA1_ROOT>;
579 clock-names = "ipg", "ahb";
580 #dma-cells = <3>;
581 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
582 };
583
584 fec1: ethernet@30be0000 {
585 compatible = "fsl,imx8mn-fec", "fsl,imx6sx-fec";
586 reg = <0x30be0000 0x10000>;
587 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
588 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
589 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
590 clocks = <&clk IMX8MN_CLK_ENET1_ROOT>,
591 <&clk IMX8MN_CLK_ENET1_ROOT>,
592 <&clk IMX8MN_CLK_ENET_TIMER>,
593 <&clk IMX8MN_CLK_ENET_REF>,
594 <&clk IMX8MN_CLK_ENET_PHY_REF>;
595 clock-names = "ipg", "ahb", "ptp",
596 "enet_clk_ref", "enet_out";
597 assigned-clocks = <&clk IMX8MN_CLK_ENET_AXI>,
598 <&clk IMX8MN_CLK_ENET_TIMER>,
599 <&clk IMX8MN_CLK_ENET_REF>,
600 <&clk IMX8MN_CLK_ENET_TIMER>;
601 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_266M>,
602 <&clk IMX8MN_SYS_PLL2_100M>,
603 <&clk IMX8MN_SYS_PLL2_125M>;
604 assigned-clock-rates = <0>, <0>, <125000000>, <100000000>;
605 fsl,num-tx-queues = <3>;
606 fsl,num-rx-queues = <3>;
607 status = "disabled";
608 };
609
610 };
611
612 aips4: bus@32c00000 {
613 compatible = "fsl,aips-bus", "simple-bus";
614 reg = <0x32c00000 0x400000>;
615 #address-cells = <1>;
616 #size-cells = <1>;
617 ranges;
618
619 usbotg1: usb@32e40000 {
620 compatible = "fsl,imx8mn-usb", "fsl,imx7d-usb";
621 reg = <0x32e40000 0x200>;
622 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
623 clocks = <&clk IMX8MN_CLK_USB1_CTRL_ROOT>;
624 clock-names = "usb1_ctrl_root_clk";
625 assigned-clocks = <&clk IMX8MN_CLK_USB_BUS>,
626 <&clk IMX8MN_CLK_USB_CORE_REF>;
627 assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_500M>,
628 <&clk IMX8MN_SYS_PLL1_100M>;
629 fsl,usbphy = <&usbphynop1>;
630 fsl,usbmisc = <&usbmisc1 0>;
631 status = "disabled";
632 };
633
634 usbmisc1: usbmisc@32e40200 {
635 compatible = "fsl,imx8mn-usbmisc", "fsl,imx7d-usbmisc";
636 #index-cells = <1>;
637 reg = <0x32e40200 0x200>;
638 };
639
640 usbotg2: usb@32e50000 {
641 compatible = "fsl,imx8mn-usb", "fsl,imx7d-usb";
642 reg = <0x32e50000 0x200>;
643 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
644 clocks = <&clk IMX8MN_CLK_USB1_CTRL_ROOT>;
645 clock-names = "usb1_ctrl_root_clk";
646 assigned-clocks = <&clk IMX8MN_CLK_USB_BUS>,
647 <&clk IMX8MN_CLK_USB_CORE_REF>;
648 assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_500M>,
649 <&clk IMX8MN_SYS_PLL1_100M>;
650 fsl,usbphy = <&usbphynop2>;
651 fsl,usbmisc = <&usbmisc2 0>;
652 status = "disabled";
653 };
654
655 usbmisc2: usbmisc@32e50200 {
656 compatible = "fsl,imx8mn-usbmisc", "fsl,imx7d-usbmisc";
657 #index-cells = <1>;
658 reg = <0x32e50200 0x200>;
659 };
660
661 };
662
663 dma_apbh: dma-controller@33000000 {
664 compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh";
665 reg = <0x33000000 0x2000>;
666 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
667 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
668 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
669 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
670 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
671 #dma-cells = <1>;
672 dma-channels = <4>;
673 clocks = <&clk IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK>;
674 };
675
676 gpmi: nand-controller@33002000 {
677 compatible = "fsl,imx8mn-gpmi-nand", "fsl,imx7d-gpmi-nand";
678 #address-cells = <1>;
679 #size-cells = <1>;
680 reg = <0x33002000 0x2000>, <0x33004000 0x4000>;
681 reg-names = "gpmi-nand", "bch";
682 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
683 interrupt-names = "bch";
684 clocks = <&clk IMX8MN_CLK_NAND_ROOT>,
685 <&clk IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK>;
686 clock-names = "gpmi_io", "gpmi_bch_apb";
687 dmas = <&dma_apbh 0>;
688 dma-names = "rx-tx";
689 status = "disabled";
690 };
691
692 gic: interrupt-controller@38800000 {
693 compatible = "arm,gic-v3";
694 reg = <0x38800000 0x10000>,
695 <0x38880000 0xc0000>;
696 #interrupt-cells = <3>;
697 interrupt-controller;
698 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
699 };
700 };
701
702 usbphynop1: usbphynop1 {
703 compatible = "usb-nop-xceiv";
704 clocks = <&clk IMX8MN_CLK_USB_PHY_REF>;
705 assigned-clocks = <&clk IMX8MN_CLK_USB_PHY_REF>;
706 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_100M>;
707 clock-names = "main_clk";
708 };
709
710 usbphynop2: usbphynop2 {
711 compatible = "usb-nop-xceiv";
712 clocks = <&clk IMX8MN_CLK_USB_PHY_REF>;
713 assigned-clocks = <&clk IMX8MN_CLK_USB_PHY_REF>;
714 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_100M>;
715 clock-names = "main_clk";
716 };
717};
Linux 6.x block layer and io_uring tree(s)