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arm64: dts: imx8mn: Add support for micfil
[linux-2.6-block.git] / arch / arm64 / boot / dts / freescale / imx8mn.dtsi
CommitLineData
6c3debcb
AH		 1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2019 NXP
4 */
5
6#include <dt-bindings/clock/imx8mn-clock.h>
7#include <dt-bindings/gpio/gpio.h>
8#include <dt-bindings/input/input.h>
9#include <dt-bindings/interrupt-controller/arm-gic.h>
819779a9 10#include <dt-bindings/thermal/thermal.h>
6c3debcb
AH		 11
12#include "imx8mn-pinfunc.h"
13
14/ {
6c3debcb
AH		 15 interrupt-parent = <&gic>;
16 #address-cells = <2>;
17 #size-cells = <2>;
18
19 aliases {
20 ethernet0 = &fec1;
21 gpio0 = &gpio1;
22 gpio1 = &gpio2;
23 gpio2 = &gpio3;
24 gpio3 = &gpio4;
25 gpio4 = &gpio5;
26 i2c0 = &i2c1;
27 i2c1 = &i2c2;
28 i2c2 = &i2c3;
29 i2c3 = &i2c4;
30 mmc0 = &usdhc1;
31 mmc1 = &usdhc2;
32 mmc2 = &usdhc3;
33 serial0 = &uart1;
34 serial1 = &uart2;
35 serial2 = &uart3;
36 serial3 = &uart4;
37 spi0 = &ecspi1;
38 spi1 = &ecspi2;
39 spi2 = &ecspi3;
40 };
41
42 cpus {
43 #address-cells = <1>;
44 #size-cells = <0>;
45
df844a9a
AH		 46 idle-states {
47 entry-method = "psci";
48
49 cpu_pd_wait: cpu-pd-wait {
50 compatible = "arm,idle-state";
51 arm,psci-suspend-param = <0x0010033>;
52 local-timer-stop;
53 entry-latency-us = <1000>;
54 exit-latency-us = <700>;
55 min-residency-us = <2700>;
56 };
57 };
58
6c3debcb
AH		 59 A53_0: cpu@0 {
60 device_type = "cpu";
61 compatible = "arm,cortex-a53";
62 reg = <0x0>;
63 clock-latency = <61036>;
64 clocks = <&clk IMX8MN_CLK_ARM>;
65 enable-method = "psci";
66 next-level-cache = <&A53_L2>;
01c49314
AH		 67 operating-points-v2 = <&a53_opp_table>;
68 nvmem-cells = <&cpu_speed_grade>;
69 nvmem-cell-names = "speed_grade";
df844a9a 70 cpu-idle-states = <&cpu_pd_wait>;
819779a9 71 #cooling-cells = <2>;
6c3debcb
AH		 72 };
73
74 A53_1: cpu@1 {
75 device_type = "cpu";
76 compatible = "arm,cortex-a53";
77 reg = <0x1>;
78 clock-latency = <61036>;
79 clocks = <&clk IMX8MN_CLK_ARM>;
80 enable-method = "psci";
81 next-level-cache = <&A53_L2>;
01c49314 82 operating-points-v2 = <&a53_opp_table>;
df844a9a 83 cpu-idle-states = <&cpu_pd_wait>;
819779a9 84 #cooling-cells = <2>;
6c3debcb
AH		 85 };
86
87 A53_2: cpu@2 {
88 device_type = "cpu";
89 compatible = "arm,cortex-a53";
90 reg = <0x2>;
91 clock-latency = <61036>;
92 clocks = <&clk IMX8MN_CLK_ARM>;
93 enable-method = "psci";
94 next-level-cache = <&A53_L2>;
01c49314 95 operating-points-v2 = <&a53_opp_table>;
df844a9a 96 cpu-idle-states = <&cpu_pd_wait>;
819779a9 97 #cooling-cells = <2>;
6c3debcb
AH		 98 };
99
100 A53_3: cpu@3 {
101 device_type = "cpu";
102 compatible = "arm,cortex-a53";
103 reg = <0x3>;
104 clock-latency = <61036>;
105 clocks = <&clk IMX8MN_CLK_ARM>;
106 enable-method = "psci";
107 next-level-cache = <&A53_L2>;
01c49314 108 operating-points-v2 = <&a53_opp_table>;
df844a9a 109 cpu-idle-states = <&cpu_pd_wait>;
819779a9 110 #cooling-cells = <2>;
6c3debcb
AH		 111 };
112
113 A53_L2: l2-cache0 {
114 compatible = "cache";
115 };
116 };
117
01c49314
AH		 118 a53_opp_table: opp-table {
119 compatible = "operating-points-v2";
120 opp-shared;
121
122 opp-1200000000 {
123 opp-hz = /bits/ 64 <1200000000>;
8c30e7ca 124 opp-microvolt = <850000>;
01c49314
AH		 125 opp-supported-hw = <0xb00>, <0x7>;
126 clock-latency-ns = <150000>;
127 opp-suspend;
128 };
129
130 opp-1400000000 {
131 opp-hz = /bits/ 64 <1400000000>;
132 opp-microvolt = <950000>;
133 opp-supported-hw = <0x300>, <0x7>;
134 clock-latency-ns = <150000>;
135 opp-suspend;
136 };
137
138 opp-1500000000 {
139 opp-hz = /bits/ 64 <1500000000>;
140 opp-microvolt = <1000000>;
141 opp-supported-hw = <0x100>, <0x3>;
142 clock-latency-ns = <150000>;
143 opp-suspend;
144 };
145 };
146
6c3debcb
AH		 147 osc_32k: clock-osc-32k {
148 compatible = "fixed-clock";
149 #clock-cells = <0>;
150 clock-frequency = <32768>;
151 clock-output-names = "osc_32k";
152 };
153
154 osc_24m: clock-osc-24m {
155 compatible = "fixed-clock";
156 #clock-cells = <0>;
157 clock-frequency = <24000000>;
158 clock-output-names = "osc_24m";
159 };
160
161 clk_ext1: clock-ext1 {
162 compatible = "fixed-clock";
163 #clock-cells = <0>;
164 clock-frequency = <133000000>;
165 clock-output-names = "clk_ext1";
166 };
167
168 clk_ext2: clock-ext2 {
169 compatible = "fixed-clock";
170 #clock-cells = <0>;
171 clock-frequency = <133000000>;
172 clock-output-names = "clk_ext2";
173 };
174
175 clk_ext3: clock-ext3 {
176 compatible = "fixed-clock";
177 #clock-cells = <0>;
178 clock-frequency = <133000000>;
179 clock-output-names = "clk_ext3";
180 };
181
182 clk_ext4: clock-ext4 {
183 compatible = "fixed-clock";
184 #clock-cells = <0>;
185 clock-frequency= <133000000>;
186 clock-output-names = "clk_ext4";
187 };
188
c13a7d84
JB		 189 pmu {
190 compatible = "arm,cortex-a53-pmu";
191 interrupts = <GIC_PPI 7
192 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
193 interrupt-affinity = <&A53_0>, <&A53_1>, <&A53_2>, <&A53_3>;
194 };
195
6c3debcb
AH		 196 psci {
197 compatible = "arm,psci-1.0";
198 method = "smc";
199 };
200
819779a9
AH		 201 thermal-zones {
202 cpu-thermal {
203 polling-delay-passive = <250>;
204 polling-delay = <2000>;
205 thermal-sensors = <&tmu>;
206 trips {
207 cpu_alert0: trip0 {
208 temperature = <85000>;
209 hysteresis = <2000>;
210 type = "passive";
211 };
212
213 cpu_crit0: trip1 {
214 temperature = <95000>;
215 hysteresis = <2000>;
216 type = "critical";
217 };
218 };
219
220 cooling-maps {
221 map0 {
222 trip = <&cpu_alert0>;
223 cooling-device =
224 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
225 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
226 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
227 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
228 };
229 };
230 };
231 };
232
6c3debcb
AH		 233 timer {
234 compatible = "arm,armv8-timer";
0656e37a
KK		 235 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
236 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
237 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
238 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
6c3debcb
AH		 239 clock-frequency = <8000000>;
240 arm,no-tick-in-suspend;
241 };
242
243 soc@0 {
244 compatible = "simple-bus";
245 #address-cells = <1>;
246 #size-cells = <1>;
247 ranges = <0x0 0x0 0x0 0x3e000000>;
248
249 aips1: bus@30000000 {
dc3efc6f 250 compatible = "fsl,aips-bus", "simple-bus";
921a6845 251 reg = <0x30000000 0x400000>;
6c3debcb
AH		 252 #address-cells = <1>;
253 #size-cells = <1>;
254 ranges;
255
970406ea
AF		 256 spba: bus@30000000 {
257 compatible = "fsl,spba-bus", "simple-bus";
258 #address-cells = <1>;
259 #size-cells = <1>;
260 reg = <0x30000000 0x100000>;
261 ranges;
262
9e986006
AF		 263 sai2: sai@30020000 {
264 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
265 reg = <0x30020000 0x10000>;
266 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
267 clocks = <&clk IMX8MN_CLK_SAI2_IPG>,
268 <&clk IMX8MN_CLK_DUMMY>,
269 <&clk IMX8MN_CLK_SAI2_ROOT>,
270 <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>;
271 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
272 dmas = <&sdma2 2 2 0>, <&sdma2 3 2 0>;
273 dma-names = "rx", "tx";
274 status = "disabled";
275 };
276
277 sai3: sai@30030000 {
278 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
279 reg = <0x30030000 0x10000>;
280 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
281 clocks = <&clk IMX8MN_CLK_SAI3_IPG>,
282 <&clk IMX8MN_CLK_DUMMY>,
283 <&clk IMX8MN_CLK_SAI3_ROOT>,
284 <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>;
285 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
286 dmas = <&sdma2 4 2 0>, <&sdma2 5 2 0>;
287 dma-names = "rx", "tx";
288 status = "disabled";
289 };
290
291 sai5: sai@30050000 {
292 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
293 reg = <0x30050000 0x10000>;
294 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
295 clocks = <&clk IMX8MN_CLK_SAI5_IPG>,
296 <&clk IMX8MN_CLK_DUMMY>,
297 <&clk IMX8MN_CLK_SAI5_ROOT>,
298 <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>;
299 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
300 dmas = <&sdma2 8 2 0>, <&sdma2 9 2 0>;
301 dma-names = "rx", "tx";
302 fsl,shared-interrupt;
303 fsl,dataline = <0 0xf 0xf>;
304 status = "disabled";
305 };
306
307 sai6: sai@30060000 {
308 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
309 reg = <0x30060000 0x10000>;
310 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
311 clocks = <&clk IMX8MN_CLK_SAI6_IPG>,
312 <&clk IMX8MN_CLK_DUMMY>,
313 <&clk IMX8MN_CLK_SAI6_ROOT>,
314 <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>;
315 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
316 dmas = <&sdma2 10 2 0>, <&sdma2 11 2 0>;
317 dma-names = "rx", "tx";
318 status = "disabled";
319 };
320
cca69ef6
AF		 321 micfil: audio-controller@30080000 {
322 compatible = "fsl,imx8mm-micfil";
323 reg = <0x30080000 0x10000>;
324 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
325 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
326 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
327 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
328 clocks = <&clk IMX8MN_CLK_PDM_IPG>,
329 <&clk IMX8MN_CLK_PDM_ROOT>,
330 <&clk IMX8MN_AUDIO_PLL1_OUT>,
331 <&clk IMX8MN_AUDIO_PLL2_OUT>,
332 <&clk IMX8MN_CLK_EXT3>;
333 clock-names = "ipg_clk", "ipg_clk_app",
334 "pll8k", "pll11k", "clkext3";
335 dmas = <&sdma2 24 25 0x80000000>;
336 dma-names = "rx";
337 status = "disabled";
338 };
339
9e986006
AF		 340 sai7: sai@300b0000 {
341 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
342 reg = <0x300b0000 0x10000>;
343 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
344 clocks = <&clk IMX8MN_CLK_SAI7_IPG>,
345 <&clk IMX8MN_CLK_DUMMY>,
346 <&clk IMX8MN_CLK_SAI7_ROOT>,
347 <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>;
348 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
349 dmas = <&sdma2 12 2 0>, <&sdma2 13 2 0>;
350 dma-names = "rx", "tx";
351 status = "disabled";
352 };
353
970406ea
AF		 354 easrc: easrc@300c0000 {
355 compatible = "fsl,imx8mn-easrc";
356 reg = <0x300c0000 0x10000>;
357 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
358 clocks = <&clk IMX8MN_CLK_ASRC_ROOT>;
359 clock-names = "mem";
360 dmas = <&sdma2 16 23 0> , <&sdma2 17 23 0>,
361 <&sdma2 18 23 0> , <&sdma2 19 23 0>,
362 <&sdma2 20 23 0> , <&sdma2 21 23 0>,
363 <&sdma2 22 23 0> , <&sdma2 23 23 0>;
364 dma-names = "ctx0_rx", "ctx0_tx",
365 "ctx1_rx", "ctx1_tx",
366 "ctx2_rx", "ctx2_tx",
367 "ctx3_rx", "ctx3_tx";
368 firmware-name = "imx/easrc/easrc-imx8mn.bin";
369 fsl,asrc-rate = <8000>;
370 fsl,asrc-format = <2>;
371 status = "disabled";
372 };
373 };
374
6c3debcb
AH		 375 gpio1: gpio@30200000 {
376 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
377 reg = <0x30200000 0x10000>;
378 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
379 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
380 clocks = <&clk IMX8MN_CLK_GPIO1_ROOT>;
381 gpio-controller;
382 #gpio-cells = <2>;
383 interrupt-controller;
384 #interrupt-cells = <2>;
ee8696be 385 gpio-ranges = <&iomuxc 0 10 30>;
6c3debcb
AH		 386 };
387
388 gpio2: gpio@30210000 {
389 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
390 reg = <0x30210000 0x10000>;
391 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
392 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
393 clocks = <&clk IMX8MN_CLK_GPIO2_ROOT>;
394 gpio-controller;
395 #gpio-cells = <2>;
396 interrupt-controller;
397 #interrupt-cells = <2>;
ee8696be 398 gpio-ranges = <&iomuxc 0 40 21>;
6c3debcb
AH		 399 };
400
401 gpio3: gpio@30220000 {
402 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
403 reg = <0x30220000 0x10000>;
404 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
405 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
406 clocks = <&clk IMX8MN_CLK_GPIO3_ROOT>;
407 gpio-controller;
408 #gpio-cells = <2>;
409 interrupt-controller;
410 #interrupt-cells = <2>;
ee8696be 411 gpio-ranges = <&iomuxc 0 61 26>;
6c3debcb
AH		 412 };
413
414 gpio4: gpio@30230000 {
415 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
416 reg = <0x30230000 0x10000>;
417 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
418 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
419 clocks = <&clk IMX8MN_CLK_GPIO4_ROOT>;
420 gpio-controller;
421 #gpio-cells = <2>;
422 interrupt-controller;
423 #interrupt-cells = <2>;
ee8696be 424 gpio-ranges = <&iomuxc 21 108 11>;
6c3debcb
AH		 425 };
426
427 gpio5: gpio@30240000 {
428 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
429 reg = <0x30240000 0x10000>;
430 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
431 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
432 clocks = <&clk IMX8MN_CLK_GPIO5_ROOT>;
433 gpio-controller;
434 #gpio-cells = <2>;
435 interrupt-controller;
436 #interrupt-cells = <2>;
ee8696be 437 gpio-ranges = <&iomuxc 0 119 30>;
6c3debcb
AH		 438 };
439
819779a9
AH		 440 tmu: tmu@30260000 {
441 compatible = "fsl,imx8mn-tmu", "fsl,imx8mm-tmu";
442 reg = <0x30260000 0x10000>;
443 clocks = <&clk IMX8MN_CLK_TMU_ROOT>;
444 #thermal-sensor-cells = <0>;
445 };
446
6c3debcb
AH		 447 wdog1: watchdog@30280000 {
448 compatible = "fsl,imx8mn-wdt", "fsl,imx21-wdt";
449 reg = <0x30280000 0x10000>;
450 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
451 clocks = <&clk IMX8MN_CLK_WDOG1_ROOT>;
452 status = "disabled";
453 };
454
455 wdog2: watchdog@30290000 {
456 compatible = "fsl,imx8mn-wdt", "fsl,imx21-wdt";
457 reg = <0x30290000 0x10000>;
458 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
459 clocks = <&clk IMX8MN_CLK_WDOG2_ROOT>;
460 status = "disabled";
461 };
462
463 wdog3: watchdog@302a0000 {
464 compatible = "fsl,imx8mn-wdt", "fsl,imx21-wdt";
465 reg = <0x302a0000 0x10000>;
466 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
467 clocks = <&clk IMX8MN_CLK_WDOG3_ROOT>;
468 status = "disabled";
469 };
470
471 sdma3: dma-controller@302b0000 {
958c6014 472 compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma";
6c3debcb
AH		 473 reg = <0x302b0000 0x10000>;
474 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
475 clocks = <&clk IMX8MN_CLK_SDMA3_ROOT>,
476 <&clk IMX8MN_CLK_SDMA3_ROOT>;
477 clock-names = "ipg", "ahb";
478 #dma-cells = <3>;
479 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
480 };
481
482 sdma2: dma-controller@302c0000 {
958c6014 483 compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma";
6c3debcb
AH		 484 reg = <0x302c0000 0x10000>;
485 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
486 clocks = <&clk IMX8MN_CLK_SDMA2_ROOT>,
487 <&clk IMX8MN_CLK_SDMA2_ROOT>;
488 clock-names = "ipg", "ahb";
489 #dma-cells = <3>;
490 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
491 };
492
493 iomuxc: pinctrl@30330000 {
494 compatible = "fsl,imx8mn-iomuxc";
495 reg = <0x30330000 0x10000>;
496 };
497
498 gpr: iomuxc-gpr@30340000 {
499 compatible = "fsl,imx8mn-iomuxc-gpr", "syscon";
500 reg = <0x30340000 0x10000>;
501 };
502
12fa1078 503 ocotp: efuse@30350000 {
2bad8c48 504 compatible = "fsl,imx8mn-ocotp", "fsl,imx8mm-ocotp", "syscon";
6c3debcb
AH		 505 reg = <0x30350000 0x10000>;
506 clocks = <&clk IMX8MN_CLK_OCOTP_ROOT>;
01c49314
AH		 507 #address-cells = <1>;
508 #size-cells = <1>;
509
510 cpu_speed_grade: speed-grade@10 {
511 reg = <0x10 4>;
512 };
6c3debcb
AH		 513 };
514
515 anatop: anatop@30360000 {
516 compatible = "fsl,imx8mn-anatop", "fsl,imx8mm-anatop",
0f93eb28 517 "syscon";
6c3debcb
AH		 518 reg = <0x30360000 0x10000>;
519 };
520
521 snvs: snvs@30370000 {
522 compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd";
523 reg = <0x30370000 0x10000>;
524
525 snvs_rtc: snvs-rtc-lp {
526 compatible = "fsl,sec-v4.0-mon-rtc-lp";
527 regmap = <&snvs>;
528 offset = <0x34>;
529 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
530 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
42ef961b 531 clocks = <&clk IMX8MN_CLK_SNVS_ROOT>;
6c3debcb
AH		 532 clock-names = "snvs-rtc";
533 };
534
535 snvs_pwrkey: snvs-powerkey {
536 compatible = "fsl,sec-v4.0-pwrkey";
537 regmap = <&snvs>;
538 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
c2a2f446
AH		 539 clocks = <&clk IMX8MN_CLK_SNVS_ROOT>;
540 clock-names = "snvs-pwrkey";
6c3debcb
AH		 541 linux,keycode = <KEY_POWER>;
542 wakeup-source;
543 status = "disabled";
544 };
545 };
546
547 clk: clock-controller@30380000 {
548 compatible = "fsl,imx8mn-ccm";
549 reg = <0x30380000 0x10000>;
550 #clock-cells = <1>;
551 clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>,
552 <&clk_ext3>, <&clk_ext4>;
553 clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
554 "clk_ext3", "clk_ext4";
9e6337e6
PF		 555 assigned-clocks = <&clk IMX8MN_CLK_A53_SRC>,
556 <&clk IMX8MN_CLK_A53_CORE>,
557 <&clk IMX8MN_CLK_NOC>,
53458f86
PF		 558 <&clk IMX8MN_CLK_AUDIO_AHB>,
559 <&clk IMX8MN_CLK_IPG_AUDIO_ROOT>,
560 <&clk IMX8MN_SYS_PLL3>;
9e6337e6
PF		 561 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_800M>,
562 <&clk IMX8MN_ARM_PLL_OUT>,
563 <&clk IMX8MN_SYS_PLL3_OUT>,
53458f86 564 <&clk IMX8MN_SYS_PLL1_800M>;
9e6337e6 565 assigned-clock-rates = <0>, <0>, <0>,
53458f86
PF		 566 <400000000>,
567 <400000000>,
568 <600000000>;
6c3debcb
AH		 569 };
570
571 src: reset-controller@30390000 {
23b80c20 572 compatible = "fsl,imx8mn-src", "fsl,imx8mq-src", "syscon";
6c3debcb
AH		 573 reg = <0x30390000 0x10000>;
574 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
575 #reset-cells = <1>;
576 };
577 };
578
579 aips2: bus@30400000 {
dc3efc6f 580 compatible = "fsl,aips-bus", "simple-bus";
921a6845 581 reg = <0x30400000 0x400000>;
6c3debcb
AH		 582 #address-cells = <1>;
583 #size-cells = <1>;
584 ranges;
585
586 pwm1: pwm@30660000 {
587 compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm";
588 reg = <0x30660000 0x10000>;
589 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
590 clocks = <&clk IMX8MN_CLK_PWM1_ROOT>,
591 <&clk IMX8MN_CLK_PWM1_ROOT>;
592 clock-names = "ipg", "per";
593 #pwm-cells = <2>;
594 status = "disabled";
595 };
596
597 pwm2: pwm@30670000 {
598 compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm";
599 reg = <0x30670000 0x10000>;
600 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
601 clocks = <&clk IMX8MN_CLK_PWM2_ROOT>,
602 <&clk IMX8MN_CLK_PWM2_ROOT>;
603 clock-names = "ipg", "per";
604 #pwm-cells = <2>;
605 status = "disabled";
606 };
607
608 pwm3: pwm@30680000 {
609 compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm";
610 reg = <0x30680000 0x10000>;
611 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
612 clocks = <&clk IMX8MN_CLK_PWM3_ROOT>,
613 <&clk IMX8MN_CLK_PWM3_ROOT>;
614 clock-names = "ipg", "per";
615 #pwm-cells = <2>;
616 status = "disabled";
617 };
618
619 pwm4: pwm@30690000 {
620 compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm";
621 reg = <0x30690000 0x10000>;
622 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
623 clocks = <&clk IMX8MN_CLK_PWM4_ROOT>,
624 <&clk IMX8MN_CLK_PWM4_ROOT>;
625 clock-names = "ipg", "per";
626 #pwm-cells = <2>;
627 status = "disabled";
628 };
c4a21269
AH		 629
630 system_counter: timer@306a0000 {
631 compatible = "nxp,sysctr-timer";
632 reg = <0x306a0000 0x20000>;
633 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
634 clocks = <&osc_24m>;
635 clock-names = "per";
636 };
6c3debcb
AH		 637 };
638
639 aips3: bus@30800000 {
dc3efc6f 640 compatible = "fsl,aips-bus", "simple-bus";
921a6845 641 reg = <0x30800000 0x400000>;
6c3debcb
AH		 642 #address-cells = <1>;
643 #size-cells = <1>;
644 ranges;
645
646 ecspi1: spi@30820000 {
647 compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi";
648 #address-cells = <1>;
649 #size-cells = <0>;
650 reg = <0x30820000 0x10000>;
651 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
652 clocks = <&clk IMX8MN_CLK_ECSPI1_ROOT>,
653 <&clk IMX8MN_CLK_ECSPI1_ROOT>;
654 clock-names = "ipg", "per";
655 dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
656 dma-names = "rx", "tx";
657 status = "disabled";
658 };
659
660 ecspi2: spi@30830000 {
661 compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi";
662 #address-cells = <1>;
663 #size-cells = <0>;
664 reg = <0x30830000 0x10000>;
665 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
666 clocks = <&clk IMX8MN_CLK_ECSPI2_ROOT>,
667 <&clk IMX8MN_CLK_ECSPI2_ROOT>;
668 clock-names = "ipg", "per";
669 dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;
670 dma-names = "rx", "tx";
671 status = "disabled";
672 };
673
674 ecspi3: spi@30840000 {
675 compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi";
676 #address-cells = <1>;
677 #size-cells = <0>;
678 reg = <0x30840000 0x10000>;
679 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
680 clocks = <&clk IMX8MN_CLK_ECSPI3_ROOT>,
681 <&clk IMX8MN_CLK_ECSPI3_ROOT>;
682 clock-names = "ipg", "per";
683 dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;
684 dma-names = "rx", "tx";
685 status = "disabled";
686 };
687
688 uart1: serial@30860000 {
689 compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
690 reg = <0x30860000 0x10000>;
691 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
692 clocks = <&clk IMX8MN_CLK_UART1_ROOT>,
693 <&clk IMX8MN_CLK_UART1_ROOT>;
694 clock-names = "ipg", "per";
695 dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;
696 dma-names = "rx", "tx";
697 status = "disabled";
698 };
699
700 uart3: serial@30880000 {
701 compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
702 reg = <0x30880000 0x10000>;
703 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
704 clocks = <&clk IMX8MN_CLK_UART3_ROOT>,
705 <&clk IMX8MN_CLK_UART3_ROOT>;
706 clock-names = "ipg", "per";
707 dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;
708 dma-names = "rx", "tx";
709 status = "disabled";
710 };
711
712 uart2: serial@30890000 {
713 compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
714 reg = <0x30890000 0x10000>;
715 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
716 clocks = <&clk IMX8MN_CLK_UART2_ROOT>,
717 <&clk IMX8MN_CLK_UART2_ROOT>;
718 clock-names = "ipg", "per";
719 status = "disabled";
720 };
721
aad24175
HG		 722 crypto: crypto@30900000 {
723 compatible = "fsl,sec-v4.0";
724 #address-cells = <1>;
725 #size-cells = <1>;
726 reg = <0x30900000 0x40000>;
727 ranges = <0 0x30900000 0x40000>;
728 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
729 clocks = <&clk IMX8MN_CLK_AHB>,
730 <&clk IMX8MN_CLK_IPG_ROOT>;
731 clock-names = "aclk", "ipg";
732
f5ff5a21 733 sec_jr0: jr@1000 {
aad24175
HG		 734 compatible = "fsl,sec-v4.0-job-ring";
735 reg = <0x1000 0x1000>;
736 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
737 };
738
f5ff5a21 739 sec_jr1: jr@2000 {
aad24175
HG		 740 compatible = "fsl,sec-v4.0-job-ring";
741 reg = <0x2000 0x1000>;
742 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
743 };
744
f5ff5a21 745 sec_jr2: jr@3000 {
aad24175
HG		 746 compatible = "fsl,sec-v4.0-job-ring";
747 reg = <0x3000 0x1000>;
748 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
749 };
750 };
751
6c3debcb
AH		 752 i2c1: i2c@30a20000 {
753 compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c";
754 #address-cells = <1>;
755 #size-cells = <0>;
756 reg = <0x30a20000 0x10000>;
757 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
758 clocks = <&clk IMX8MN_CLK_I2C1_ROOT>;
759 status = "disabled";
760 };
761
762 i2c2: i2c@30a30000 {
763 compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c";
764 #address-cells = <1>;
765 #size-cells = <0>;
766 reg = <0x30a30000 0x10000>;
767 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
768 clocks = <&clk IMX8MN_CLK_I2C2_ROOT>;
769 status = "disabled";
770 };
771
772 i2c3: i2c@30a40000 {
773 #address-cells = <1>;
774 #size-cells = <0>;
775 compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c";
776 reg = <0x30a40000 0x10000>;
777 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
778 clocks = <&clk IMX8MN_CLK_I2C3_ROOT>;
779 status = "disabled";
780 };
781
782 i2c4: i2c@30a50000 {
783 compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c";
784 #address-cells = <1>;
785 #size-cells = <0>;
786 reg = <0x30a50000 0x10000>;
787 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
788 clocks = <&clk IMX8MN_CLK_I2C4_ROOT>;
789 status = "disabled";
790 };
791
792 uart4: serial@30a60000 {
793 compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
794 reg = <0x30a60000 0x10000>;
795 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
796 clocks = <&clk IMX8MN_CLK_UART4_ROOT>,
797 <&clk IMX8MN_CLK_UART4_ROOT>;
798 clock-names = "ipg", "per";
799 dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>;
800 dma-names = "rx", "tx";
801 status = "disabled";
802 };
803
bbfc59be
PF		 804 mu: mailbox@30aa0000 {
805 compatible = "fsl,imx8mn-mu", "fsl,imx6sx-mu";
806 reg = <0x30aa0000 0x10000>;
807 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
808 clocks = <&clk IMX8MN_CLK_MU_ROOT>;
809 #mbox-cells = <2>;
810 };
811
6c3debcb
AH		 812 usdhc1: mmc@30b40000 {
813 compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc";
814 reg = <0x30b40000 0x10000>;
815 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
ea65aba8 816 clocks = <&clk IMX8MN_CLK_IPG_ROOT>,
6c3debcb
AH		 817 <&clk IMX8MN_CLK_NAND_USDHC_BUS>,
818 <&clk IMX8MN_CLK_USDHC1_ROOT>;
819 clock-names = "ipg", "ahb", "per";
6c3debcb
AH		 820 fsl,tuning-start-tap = <20>;
821 fsl,tuning-step= <2>;
822 bus-width = <4>;
823 status = "disabled";
824 };
825
826 usdhc2: mmc@30b50000 {
827 compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc";
828 reg = <0x30b50000 0x10000>;
829 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
ea65aba8 830 clocks = <&clk IMX8MN_CLK_IPG_ROOT>,
6c3debcb
AH		 831 <&clk IMX8MN_CLK_NAND_USDHC_BUS>,
832 <&clk IMX8MN_CLK_USDHC2_ROOT>;
833 clock-names = "ipg", "ahb", "per";
834 fsl,tuning-start-tap = <20>;
835 fsl,tuning-step= <2>;
836 bus-width = <4>;
837 status = "disabled";
838 };
839
840 usdhc3: mmc@30b60000 {
841 compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc";
842 reg = <0x30b60000 0x10000>;
843 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
ea65aba8 844 clocks = <&clk IMX8MN_CLK_IPG_ROOT>,
6c3debcb
AH		 845 <&clk IMX8MN_CLK_NAND_USDHC_BUS>,
846 <&clk IMX8MN_CLK_USDHC3_ROOT>;
847 clock-names = "ipg", "ahb", "per";
6c3debcb
AH		 848 fsl,tuning-start-tap = <20>;
849 fsl,tuning-step= <2>;
850 bus-width = <4>;
851 status = "disabled";
852 };
853
854 sdma1: dma-controller@30bd0000 {
958c6014 855 compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma";
6c3debcb
AH		 856 reg = <0x30bd0000 0x10000>;
857 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
858 clocks = <&clk IMX8MN_CLK_SDMA1_ROOT>,
15ddc3e1 859 <&clk IMX8MN_CLK_AHB>;
6c3debcb
AH		 860 clock-names = "ipg", "ahb";
861 #dma-cells = <3>;
862 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
863 };
864
865 fec1: ethernet@30be0000 {
866 compatible = "fsl,imx8mn-fec", "fsl,imx6sx-fec";
867 reg = <0x30be0000 0x10000>;
868 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
869 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
d3762a47
FE		 870 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
871 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
6c3debcb
AH		 872 clocks = <&clk IMX8MN_CLK_ENET1_ROOT>,
873 <&clk IMX8MN_CLK_ENET1_ROOT>,
874 <&clk IMX8MN_CLK_ENET_TIMER>,
875 <&clk IMX8MN_CLK_ENET_REF>,
876 <&clk IMX8MN_CLK_ENET_PHY_REF>;
877 clock-names = "ipg", "ahb", "ptp",
878 "enet_clk_ref", "enet_out";
879 assigned-clocks = <&clk IMX8MN_CLK_ENET_AXI>,
880 <&clk IMX8MN_CLK_ENET_TIMER>,
881 <&clk IMX8MN_CLK_ENET_REF>,
882 <&clk IMX8MN_CLK_ENET_TIMER>;
883 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_266M>,
884 <&clk IMX8MN_SYS_PLL2_100M>,
885 <&clk IMX8MN_SYS_PLL2_125M>;
886 assigned-clock-rates = <0>, <0>, <125000000>, <100000000>;
887 fsl,num-tx-queues = <3>;
888 fsl,num-rx-queues = <3>;
889 status = "disabled";
890 };
891
892 };
893
894 aips4: bus@32c00000 {
dc3efc6f 895 compatible = "fsl,aips-bus", "simple-bus";
921a6845 896 reg = <0x32c00000 0x400000>;
6c3debcb
AH		 897 #address-cells = <1>;
898 #size-cells = <1>;
899 ranges;
900
901 usbotg1: usb@32e40000 {
902 compatible = "fsl,imx8mn-usb", "fsl,imx7d-usb";
903 reg = <0x32e40000 0x200>;
904 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
905 clocks = <&clk IMX8MN_CLK_USB1_CTRL_ROOT>;
906 clock-names = "usb1_ctrl_root_clk";
d51cb99c
LJ		 907 assigned-clocks = <&clk IMX8MN_CLK_USB_BUS>;
908 assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_500M>;
6c3debcb
AH		 909 fsl,usbphy = <&usbphynop1>;
910 fsl,usbmisc = <&usbmisc1 0>;
911 status = "disabled";
912 };
913
914 usbmisc1: usbmisc@32e40200 {
915 compatible = "fsl,imx8mn-usbmisc", "fsl,imx7d-usbmisc";
916 #index-cells = <1>;
917 reg = <0x32e40200 0x200>;
918 };
919
920 usbotg2: usb@32e50000 {
921 compatible = "fsl,imx8mn-usb", "fsl,imx7d-usb";
922 reg = <0x32e50000 0x200>;
923 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
924 clocks = <&clk IMX8MN_CLK_USB1_CTRL_ROOT>;
925 clock-names = "usb1_ctrl_root_clk";
926 assigned-clocks = <&clk IMX8MN_CLK_USB_BUS>,
927 <&clk IMX8MN_CLK_USB_CORE_REF>;
928 assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_500M>,
929 <&clk IMX8MN_SYS_PLL1_100M>;
930 fsl,usbphy = <&usbphynop2>;
931 fsl,usbmisc = <&usbmisc2 0>;
932 status = "disabled";
933 };
934
935 usbmisc2: usbmisc@32e50200 {
936 compatible = "fsl,imx8mn-usbmisc", "fsl,imx7d-usbmisc";
937 #index-cells = <1>;
938 reg = <0x32e50200 0x200>;
939 };
940
941 };
942
943 dma_apbh: dma-controller@33000000 {
944 compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh";
945 reg = <0x33000000 0x2000>;
946 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
947 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
948 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
949 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
950 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
951 #dma-cells = <1>;
952 dma-channels = <4>;
953 clocks = <&clk IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK>;
954 };
955
956 gpmi: nand-controller@33002000 {
957 compatible = "fsl,imx8mn-gpmi-nand", "fsl,imx7d-gpmi-nand";
958 #address-cells = <1>;
959 #size-cells = <1>;
960 reg = <0x33002000 0x2000>, <0x33004000 0x4000>;
961 reg-names = "gpmi-nand", "bch";
962 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
963 interrupt-names = "bch";
964 clocks = <&clk IMX8MN_CLK_NAND_ROOT>,
965 <&clk IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK>;
966 clock-names = "gpmi_io", "gpmi_bch_apb";
967 dmas = <&dma_apbh 0>;
968 dma-names = "rx-tx";
969 status = "disabled";
970 };
971
972 gic: interrupt-controller@38800000 {
973 compatible = "arm,gic-v3";
974 reg = <0x38800000 0x10000>,
975 <0x38880000 0xc0000>;
976 #interrupt-cells = <3>;
977 interrupt-controller;
978 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
979 };
2d8e0747 980
0376f6ec
LC		 981 ddrc: memory-controller@3d400000 {
982 compatible = "fsl,imx8mn-ddrc", "fsl,imx8m-ddrc";
983 reg = <0x3d400000 0x400000>;
984 clock-names = "core", "pll", "alt", "apb";
985 clocks = <&clk IMX8MN_CLK_DRAM_CORE>,
986 <&clk IMX8MN_DRAM_PLL>,
987 <&clk IMX8MN_CLK_DRAM_ALT>,
988 <&clk IMX8MN_CLK_DRAM_APB>;
989 };
990
2d8e0747
JZ		 991 ddr-pmu@3d800000 {
992 compatible = "fsl,imx8mn-ddr-pmu", "fsl,imx8m-ddr-pmu";
993 reg = <0x3d800000 0x400000>;
994 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
995 };
6c3debcb
AH		 996 };
997
998 usbphynop1: usbphynop1 {
999 compatible = "usb-nop-xceiv";
1000 clocks = <&clk IMX8MN_CLK_USB_PHY_REF>;
1001 assigned-clocks = <&clk IMX8MN_CLK_USB_PHY_REF>;
1002 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_100M>;
1003 clock-names = "main_clk";
1004 };
1005
1006 usbphynop2: usbphynop2 {
1007 compatible = "usb-nop-xceiv";
1008 clocks = <&clk IMX8MN_CLK_USB_PHY_REF>;
1009 assigned-clocks = <&clk IMX8MN_CLK_USB_PHY_REF>;
1010 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_100M>;
1011 clock-names = "main_clk";
1012 };
1013};
Linux 6.x block layer and io_uring tree(s)