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arm64: dts: lx2160a: use constants in the clockgen phandle
[linux-2.6-block.git] / arch / arm64 / boot / dts / freescale / imx8mn.dtsi
CommitLineData
6c3debcb
AH		 1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2019 NXP
4 */
5
6#include <dt-bindings/clock/imx8mn-clock.h>
7#include <dt-bindings/gpio/gpio.h>
8#include <dt-bindings/input/input.h>
9#include <dt-bindings/interrupt-controller/arm-gic.h>
819779a9 10#include <dt-bindings/thermal/thermal.h>
6c3debcb
AH		 11
12#include "imx8mn-pinfunc.h"
13
14/ {
6c3debcb
AH		 15 interrupt-parent = <&gic>;
16 #address-cells = <2>;
17 #size-cells = <2>;
18
19 aliases {
20 ethernet0 = &fec1;
21 gpio0 = &gpio1;
22 gpio1 = &gpio2;
23 gpio2 = &gpio3;
24 gpio3 = &gpio4;
25 gpio4 = &gpio5;
26 i2c0 = &i2c1;
27 i2c1 = &i2c2;
28 i2c2 = &i2c3;
29 i2c3 = &i2c4;
30 mmc0 = &usdhc1;
31 mmc1 = &usdhc2;
32 mmc2 = &usdhc3;
33 serial0 = &uart1;
34 serial1 = &uart2;
35 serial2 = &uart3;
36 serial3 = &uart4;
37 spi0 = &ecspi1;
38 spi1 = &ecspi2;
39 spi2 = &ecspi3;
40 };
41
42 cpus {
43 #address-cells = <1>;
44 #size-cells = <0>;
45
df844a9a
AH		 46 idle-states {
47 entry-method = "psci";
48
49 cpu_pd_wait: cpu-pd-wait {
50 compatible = "arm,idle-state";
51 arm,psci-suspend-param = <0x0010033>;
52 local-timer-stop;
53 entry-latency-us = <1000>;
54 exit-latency-us = <700>;
55 min-residency-us = <2700>;
56 };
57 };
58
6c3debcb
AH		 59 A53_0: cpu@0 {
60 device_type = "cpu";
61 compatible = "arm,cortex-a53";
62 reg = <0x0>;
63 clock-latency = <61036>;
64 clocks = <&clk IMX8MN_CLK_ARM>;
65 enable-method = "psci";
66 next-level-cache = <&A53_L2>;
01c49314
AH		 67 operating-points-v2 = <&a53_opp_table>;
68 nvmem-cells = <&cpu_speed_grade>;
69 nvmem-cell-names = "speed_grade";
df844a9a 70 cpu-idle-states = <&cpu_pd_wait>;
819779a9 71 #cooling-cells = <2>;
6c3debcb
AH		 72 };
73
74 A53_1: cpu@1 {
75 device_type = "cpu";
76 compatible = "arm,cortex-a53";
77 reg = <0x1>;
78 clock-latency = <61036>;
79 clocks = <&clk IMX8MN_CLK_ARM>;
80 enable-method = "psci";
81 next-level-cache = <&A53_L2>;
01c49314 82 operating-points-v2 = <&a53_opp_table>;
df844a9a 83 cpu-idle-states = <&cpu_pd_wait>;
819779a9 84 #cooling-cells = <2>;
6c3debcb
AH		 85 };
86
87 A53_2: cpu@2 {
88 device_type = "cpu";
89 compatible = "arm,cortex-a53";
90 reg = <0x2>;
91 clock-latency = <61036>;
92 clocks = <&clk IMX8MN_CLK_ARM>;
93 enable-method = "psci";
94 next-level-cache = <&A53_L2>;
01c49314 95 operating-points-v2 = <&a53_opp_table>;
df844a9a 96 cpu-idle-states = <&cpu_pd_wait>;
819779a9 97 #cooling-cells = <2>;
6c3debcb
AH		 98 };
99
100 A53_3: cpu@3 {
101 device_type = "cpu";
102 compatible = "arm,cortex-a53";
103 reg = <0x3>;
104 clock-latency = <61036>;
105 clocks = <&clk IMX8MN_CLK_ARM>;
106 enable-method = "psci";
107 next-level-cache = <&A53_L2>;
01c49314 108 operating-points-v2 = <&a53_opp_table>;
df844a9a 109 cpu-idle-states = <&cpu_pd_wait>;
819779a9 110 #cooling-cells = <2>;
6c3debcb
AH		 111 };
112
113 A53_L2: l2-cache0 {
114 compatible = "cache";
115 };
116 };
117
01c49314
AH		 118 a53_opp_table: opp-table {
119 compatible = "operating-points-v2";
120 opp-shared;
121
122 opp-1200000000 {
123 opp-hz = /bits/ 64 <1200000000>;
8c30e7ca 124 opp-microvolt = <850000>;
01c49314
AH		 125 opp-supported-hw = <0xb00>, <0x7>;
126 clock-latency-ns = <150000>;
127 opp-suspend;
128 };
129
130 opp-1400000000 {
131 opp-hz = /bits/ 64 <1400000000>;
132 opp-microvolt = <950000>;
133 opp-supported-hw = <0x300>, <0x7>;
134 clock-latency-ns = <150000>;
135 opp-suspend;
136 };
137
138 opp-1500000000 {
139 opp-hz = /bits/ 64 <1500000000>;
140 opp-microvolt = <1000000>;
141 opp-supported-hw = <0x100>, <0x3>;
142 clock-latency-ns = <150000>;
143 opp-suspend;
144 };
145 };
146
6c3debcb
AH		 147 osc_32k: clock-osc-32k {
148 compatible = "fixed-clock";
149 #clock-cells = <0>;
150 clock-frequency = <32768>;
151 clock-output-names = "osc_32k";
152 };
153
154 osc_24m: clock-osc-24m {
155 compatible = "fixed-clock";
156 #clock-cells = <0>;
157 clock-frequency = <24000000>;
158 clock-output-names = "osc_24m";
159 };
160
161 clk_ext1: clock-ext1 {
162 compatible = "fixed-clock";
163 #clock-cells = <0>;
164 clock-frequency = <133000000>;
165 clock-output-names = "clk_ext1";
166 };
167
168 clk_ext2: clock-ext2 {
169 compatible = "fixed-clock";
170 #clock-cells = <0>;
171 clock-frequency = <133000000>;
172 clock-output-names = "clk_ext2";
173 };
174
175 clk_ext3: clock-ext3 {
176 compatible = "fixed-clock";
177 #clock-cells = <0>;
178 clock-frequency = <133000000>;
179 clock-output-names = "clk_ext3";
180 };
181
182 clk_ext4: clock-ext4 {
183 compatible = "fixed-clock";
184 #clock-cells = <0>;
185 clock-frequency= <133000000>;
186 clock-output-names = "clk_ext4";
187 };
188
c13a7d84
JB		 189 pmu {
190 compatible = "arm,cortex-a53-pmu";
191 interrupts = <GIC_PPI 7
192 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
193 interrupt-affinity = <&A53_0>, <&A53_1>, <&A53_2>, <&A53_3>;
194 };
195
6c3debcb
AH		 196 psci {
197 compatible = "arm,psci-1.0";
198 method = "smc";
199 };
200
819779a9
AH		 201 thermal-zones {
202 cpu-thermal {
203 polling-delay-passive = <250>;
204 polling-delay = <2000>;
205 thermal-sensors = <&tmu>;
206 trips {
207 cpu_alert0: trip0 {
208 temperature = <85000>;
209 hysteresis = <2000>;
210 type = "passive";
211 };
212
213 cpu_crit0: trip1 {
214 temperature = <95000>;
215 hysteresis = <2000>;
216 type = "critical";
217 };
218 };
219
220 cooling-maps {
221 map0 {
222 trip = <&cpu_alert0>;
223 cooling-device =
224 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
225 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
226 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
227 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
228 };
229 };
230 };
231 };
232
6c3debcb
AH		 233 timer {
234 compatible = "arm,armv8-timer";
0656e37a
KK		 235 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
236 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
237 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
238 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
6c3debcb
AH		 239 clock-frequency = <8000000>;
240 arm,no-tick-in-suspend;
241 };
242
243 soc@0 {
244 compatible = "simple-bus";
245 #address-cells = <1>;
246 #size-cells = <1>;
247 ranges = <0x0 0x0 0x0 0x3e000000>;
248
249 aips1: bus@30000000 {
dc3efc6f 250 compatible = "fsl,aips-bus", "simple-bus";
921a6845 251 reg = <0x30000000 0x400000>;
6c3debcb
AH		 252 #address-cells = <1>;
253 #size-cells = <1>;
254 ranges;
255
970406ea
AF		 256 spba: bus@30000000 {
257 compatible = "fsl,spba-bus", "simple-bus";
258 #address-cells = <1>;
259 #size-cells = <1>;
260 reg = <0x30000000 0x100000>;
261 ranges;
262
9e986006
AF		 263 sai2: sai@30020000 {
264 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
265 reg = <0x30020000 0x10000>;
266 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
267 clocks = <&clk IMX8MN_CLK_SAI2_IPG>,
268 <&clk IMX8MN_CLK_DUMMY>,
269 <&clk IMX8MN_CLK_SAI2_ROOT>,
270 <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>;
271 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
272 dmas = <&sdma2 2 2 0>, <&sdma2 3 2 0>;
273 dma-names = "rx", "tx";
274 status = "disabled";
275 };
276
277 sai3: sai@30030000 {
278 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
279 reg = <0x30030000 0x10000>;
280 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
281 clocks = <&clk IMX8MN_CLK_SAI3_IPG>,
282 <&clk IMX8MN_CLK_DUMMY>,
283 <&clk IMX8MN_CLK_SAI3_ROOT>,
284 <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>;
285 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
286 dmas = <&sdma2 4 2 0>, <&sdma2 5 2 0>;
287 dma-names = "rx", "tx";
288 status = "disabled";
289 };
290
291 sai5: sai@30050000 {
292 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
293 reg = <0x30050000 0x10000>;
294 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
295 clocks = <&clk IMX8MN_CLK_SAI5_IPG>,
296 <&clk IMX8MN_CLK_DUMMY>,
297 <&clk IMX8MN_CLK_SAI5_ROOT>,
298 <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>;
299 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
300 dmas = <&sdma2 8 2 0>, <&sdma2 9 2 0>;
301 dma-names = "rx", "tx";
302 fsl,shared-interrupt;
303 fsl,dataline = <0 0xf 0xf>;
304 status = "disabled";
305 };
306
307 sai6: sai@30060000 {
308 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
309 reg = <0x30060000 0x10000>;
310 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
311 clocks = <&clk IMX8MN_CLK_SAI6_IPG>,
312 <&clk IMX8MN_CLK_DUMMY>,
313 <&clk IMX8MN_CLK_SAI6_ROOT>,
314 <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>;
315 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
316 dmas = <&sdma2 10 2 0>, <&sdma2 11 2 0>;
317 dma-names = "rx", "tx";
318 status = "disabled";
319 };
320
cca69ef6
AF		 321 micfil: audio-controller@30080000 {
322 compatible = "fsl,imx8mm-micfil";
323 reg = <0x30080000 0x10000>;
324 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
325 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
326 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
327 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
328 clocks = <&clk IMX8MN_CLK_PDM_IPG>,
329 <&clk IMX8MN_CLK_PDM_ROOT>,
330 <&clk IMX8MN_AUDIO_PLL1_OUT>,
331 <&clk IMX8MN_AUDIO_PLL2_OUT>,
332 <&clk IMX8MN_CLK_EXT3>;
333 clock-names = "ipg_clk", "ipg_clk_app",
334 "pll8k", "pll11k", "clkext3";
335 dmas = <&sdma2 24 25 0x80000000>;
336 dma-names = "rx";
337 status = "disabled";
338 };
339
b9cf7d3b
AF		 340 spdif1: spdif@30090000 {
341 compatible = "fsl,imx35-spdif";
342 reg = <0x30090000 0x10000>;
343 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
344 clocks = <&clk IMX8MN_CLK_AUDIO_AHB>, /* core */
345 <&clk IMX8MN_CLK_24M>, /* rxtx0 */
346 <&clk IMX8MN_CLK_SPDIF1>, /* rxtx1 */
347 <&clk IMX8MN_CLK_DUMMY>, /* rxtx2 */
348 <&clk IMX8MN_CLK_DUMMY>, /* rxtx3 */
349 <&clk IMX8MN_CLK_DUMMY>, /* rxtx4 */
350 <&clk IMX8MN_CLK_AUDIO_AHB>, /* rxtx5 */
351 <&clk IMX8MN_CLK_DUMMY>, /* rxtx6 */
352 <&clk IMX8MN_CLK_DUMMY>, /* rxtx7 */
353 <&clk IMX8MN_CLK_DUMMY>; /* spba */
354 clock-names = "core", "rxtx0",
355 "rxtx1", "rxtx2",
356 "rxtx3", "rxtx4",
357 "rxtx5", "rxtx6",
358 "rxtx7", "spba";
359 dmas = <&sdma2 28 18 0>, <&sdma2 29 18 0>;
360 dma-names = "rx", "tx";
361 status = "disabled";
362 };
363
9e986006
AF		 364 sai7: sai@300b0000 {
365 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
366 reg = <0x300b0000 0x10000>;
367 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
368 clocks = <&clk IMX8MN_CLK_SAI7_IPG>,
369 <&clk IMX8MN_CLK_DUMMY>,
370 <&clk IMX8MN_CLK_SAI7_ROOT>,
371 <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>;
372 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
373 dmas = <&sdma2 12 2 0>, <&sdma2 13 2 0>;
374 dma-names = "rx", "tx";
375 status = "disabled";
376 };
377
970406ea
AF		 378 easrc: easrc@300c0000 {
379 compatible = "fsl,imx8mn-easrc";
380 reg = <0x300c0000 0x10000>;
381 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
382 clocks = <&clk IMX8MN_CLK_ASRC_ROOT>;
383 clock-names = "mem";
384 dmas = <&sdma2 16 23 0> , <&sdma2 17 23 0>,
385 <&sdma2 18 23 0> , <&sdma2 19 23 0>,
386 <&sdma2 20 23 0> , <&sdma2 21 23 0>,
387 <&sdma2 22 23 0> , <&sdma2 23 23 0>;
388 dma-names = "ctx0_rx", "ctx0_tx",
389 "ctx1_rx", "ctx1_tx",
390 "ctx2_rx", "ctx2_tx",
391 "ctx3_rx", "ctx3_tx";
392 firmware-name = "imx/easrc/easrc-imx8mn.bin";
393 fsl,asrc-rate = <8000>;
394 fsl,asrc-format = <2>;
395 status = "disabled";
396 };
397 };
398
6c3debcb
AH		 399 gpio1: gpio@30200000 {
400 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
401 reg = <0x30200000 0x10000>;
402 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
403 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
404 clocks = <&clk IMX8MN_CLK_GPIO1_ROOT>;
405 gpio-controller;
406 #gpio-cells = <2>;
407 interrupt-controller;
408 #interrupt-cells = <2>;
ee8696be 409 gpio-ranges = <&iomuxc 0 10 30>;
6c3debcb
AH		 410 };
411
412 gpio2: gpio@30210000 {
413 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
414 reg = <0x30210000 0x10000>;
415 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
416 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
417 clocks = <&clk IMX8MN_CLK_GPIO2_ROOT>;
418 gpio-controller;
419 #gpio-cells = <2>;
420 interrupt-controller;
421 #interrupt-cells = <2>;
ee8696be 422 gpio-ranges = <&iomuxc 0 40 21>;
6c3debcb
AH		 423 };
424
425 gpio3: gpio@30220000 {
426 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
427 reg = <0x30220000 0x10000>;
428 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
429 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
430 clocks = <&clk IMX8MN_CLK_GPIO3_ROOT>;
431 gpio-controller;
432 #gpio-cells = <2>;
433 interrupt-controller;
434 #interrupt-cells = <2>;
ee8696be 435 gpio-ranges = <&iomuxc 0 61 26>;
6c3debcb
AH		 436 };
437
438 gpio4: gpio@30230000 {
439 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
440 reg = <0x30230000 0x10000>;
441 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
442 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
443 clocks = <&clk IMX8MN_CLK_GPIO4_ROOT>;
444 gpio-controller;
445 #gpio-cells = <2>;
446 interrupt-controller;
447 #interrupt-cells = <2>;
ee8696be 448 gpio-ranges = <&iomuxc 21 108 11>;
6c3debcb
AH		 449 };
450
451 gpio5: gpio@30240000 {
452 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
453 reg = <0x30240000 0x10000>;
454 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
455 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
456 clocks = <&clk IMX8MN_CLK_GPIO5_ROOT>;
457 gpio-controller;
458 #gpio-cells = <2>;
459 interrupt-controller;
460 #interrupt-cells = <2>;
ee8696be 461 gpio-ranges = <&iomuxc 0 119 30>;
6c3debcb
AH		 462 };
463
819779a9
AH		 464 tmu: tmu@30260000 {
465 compatible = "fsl,imx8mn-tmu", "fsl,imx8mm-tmu";
466 reg = <0x30260000 0x10000>;
467 clocks = <&clk IMX8MN_CLK_TMU_ROOT>;
468 #thermal-sensor-cells = <0>;
469 };
470
6c3debcb
AH		 471 wdog1: watchdog@30280000 {
472 compatible = "fsl,imx8mn-wdt", "fsl,imx21-wdt";
473 reg = <0x30280000 0x10000>;
474 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
475 clocks = <&clk IMX8MN_CLK_WDOG1_ROOT>;
476 status = "disabled";
477 };
478
479 wdog2: watchdog@30290000 {
480 compatible = "fsl,imx8mn-wdt", "fsl,imx21-wdt";
481 reg = <0x30290000 0x10000>;
482 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
483 clocks = <&clk IMX8MN_CLK_WDOG2_ROOT>;
484 status = "disabled";
485 };
486
487 wdog3: watchdog@302a0000 {
488 compatible = "fsl,imx8mn-wdt", "fsl,imx21-wdt";
489 reg = <0x302a0000 0x10000>;
490 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
491 clocks = <&clk IMX8MN_CLK_WDOG3_ROOT>;
492 status = "disabled";
493 };
494
495 sdma3: dma-controller@302b0000 {
958c6014 496 compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma";
6c3debcb
AH		 497 reg = <0x302b0000 0x10000>;
498 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
499 clocks = <&clk IMX8MN_CLK_SDMA3_ROOT>,
500 <&clk IMX8MN_CLK_SDMA3_ROOT>;
501 clock-names = "ipg", "ahb";
502 #dma-cells = <3>;
503 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
504 };
505
506 sdma2: dma-controller@302c0000 {
958c6014 507 compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma";
6c3debcb
AH		 508 reg = <0x302c0000 0x10000>;
509 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
510 clocks = <&clk IMX8MN_CLK_SDMA2_ROOT>,
511 <&clk IMX8MN_CLK_SDMA2_ROOT>;
512 clock-names = "ipg", "ahb";
513 #dma-cells = <3>;
514 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
515 };
516
517 iomuxc: pinctrl@30330000 {
518 compatible = "fsl,imx8mn-iomuxc";
519 reg = <0x30330000 0x10000>;
520 };
521
522 gpr: iomuxc-gpr@30340000 {
523 compatible = "fsl,imx8mn-iomuxc-gpr", "syscon";
524 reg = <0x30340000 0x10000>;
525 };
526
12fa1078 527 ocotp: efuse@30350000 {
2bad8c48 528 compatible = "fsl,imx8mn-ocotp", "fsl,imx8mm-ocotp", "syscon";
6c3debcb
AH		 529 reg = <0x30350000 0x10000>;
530 clocks = <&clk IMX8MN_CLK_OCOTP_ROOT>;
01c49314
AH		 531 #address-cells = <1>;
532 #size-cells = <1>;
533
534 cpu_speed_grade: speed-grade@10 {
535 reg = <0x10 4>;
536 };
6c3debcb
AH		 537 };
538
539 anatop: anatop@30360000 {
540 compatible = "fsl,imx8mn-anatop", "fsl,imx8mm-anatop",
0f93eb28 541 "syscon";
6c3debcb
AH		 542 reg = <0x30360000 0x10000>;
543 };
544
545 snvs: snvs@30370000 {
546 compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd";
547 reg = <0x30370000 0x10000>;
548
549 snvs_rtc: snvs-rtc-lp {
550 compatible = "fsl,sec-v4.0-mon-rtc-lp";
551 regmap = <&snvs>;
552 offset = <0x34>;
553 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
554 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
42ef961b 555 clocks = <&clk IMX8MN_CLK_SNVS_ROOT>;
6c3debcb
AH		 556 clock-names = "snvs-rtc";
557 };
558
559 snvs_pwrkey: snvs-powerkey {
560 compatible = "fsl,sec-v4.0-pwrkey";
561 regmap = <&snvs>;
562 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
c2a2f446
AH		 563 clocks = <&clk IMX8MN_CLK_SNVS_ROOT>;
564 clock-names = "snvs-pwrkey";
6c3debcb
AH		 565 linux,keycode = <KEY_POWER>;
566 wakeup-source;
567 status = "disabled";
568 };
569 };
570
571 clk: clock-controller@30380000 {
572 compatible = "fsl,imx8mn-ccm";
573 reg = <0x30380000 0x10000>;
574 #clock-cells = <1>;
575 clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>,
576 <&clk_ext3>, <&clk_ext4>;
577 clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
578 "clk_ext3", "clk_ext4";
9e6337e6
PF		 579 assigned-clocks = <&clk IMX8MN_CLK_A53_SRC>,
580 <&clk IMX8MN_CLK_A53_CORE>,
581 <&clk IMX8MN_CLK_NOC>,
53458f86
PF		 582 <&clk IMX8MN_CLK_AUDIO_AHB>,
583 <&clk IMX8MN_CLK_IPG_AUDIO_ROOT>,
26442c79
SW		 584 <&clk IMX8MN_SYS_PLL3>,
585 <&clk IMX8MN_AUDIO_PLL1>,
586 <&clk IMX8MN_AUDIO_PLL2>;
9e6337e6
PF		 587 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_800M>,
588 <&clk IMX8MN_ARM_PLL_OUT>,
589 <&clk IMX8MN_SYS_PLL3_OUT>,
53458f86 590 <&clk IMX8MN_SYS_PLL1_800M>;
9e6337e6 591 assigned-clock-rates = <0>, <0>, <0>,
53458f86
PF		 592 <400000000>,
593 <400000000>,
26442c79
SW		 594 <600000000>,
595 <393216000>,
596 <361267200>;
6c3debcb
AH		 597 };
598
599 src: reset-controller@30390000 {
23b80c20 600 compatible = "fsl,imx8mn-src", "fsl,imx8mq-src", "syscon";
6c3debcb
AH		 601 reg = <0x30390000 0x10000>;
602 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
603 #reset-cells = <1>;
604 };
605 };
606
607 aips2: bus@30400000 {
dc3efc6f 608 compatible = "fsl,aips-bus", "simple-bus";
921a6845 609 reg = <0x30400000 0x400000>;
6c3debcb
AH		 610 #address-cells = <1>;
611 #size-cells = <1>;
612 ranges;
613
614 pwm1: pwm@30660000 {
615 compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm";
616 reg = <0x30660000 0x10000>;
617 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
618 clocks = <&clk IMX8MN_CLK_PWM1_ROOT>,
619 <&clk IMX8MN_CLK_PWM1_ROOT>;
620 clock-names = "ipg", "per";
621 #pwm-cells = <2>;
622 status = "disabled";
623 };
624
625 pwm2: pwm@30670000 {
626 compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm";
627 reg = <0x30670000 0x10000>;
628 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
629 clocks = <&clk IMX8MN_CLK_PWM2_ROOT>,
630 <&clk IMX8MN_CLK_PWM2_ROOT>;
631 clock-names = "ipg", "per";
632 #pwm-cells = <2>;
633 status = "disabled";
634 };
635
636 pwm3: pwm@30680000 {
637 compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm";
638 reg = <0x30680000 0x10000>;
639 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
640 clocks = <&clk IMX8MN_CLK_PWM3_ROOT>,
641 <&clk IMX8MN_CLK_PWM3_ROOT>;
642 clock-names = "ipg", "per";
643 #pwm-cells = <2>;
644 status = "disabled";
645 };
646
647 pwm4: pwm@30690000 {
648 compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm";
649 reg = <0x30690000 0x10000>;
650 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
651 clocks = <&clk IMX8MN_CLK_PWM4_ROOT>,
652 <&clk IMX8MN_CLK_PWM4_ROOT>;
653 clock-names = "ipg", "per";
654 #pwm-cells = <2>;
655 status = "disabled";
656 };
c4a21269
AH		 657
658 system_counter: timer@306a0000 {
659 compatible = "nxp,sysctr-timer";
660 reg = <0x306a0000 0x20000>;
661 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
662 clocks = <&osc_24m>;
663 clock-names = "per";
664 };
6c3debcb
AH		 665 };
666
667 aips3: bus@30800000 {
dc3efc6f 668 compatible = "fsl,aips-bus", "simple-bus";
921a6845 669 reg = <0x30800000 0x400000>;
6c3debcb
AH		 670 #address-cells = <1>;
671 #size-cells = <1>;
672 ranges;
673
674 ecspi1: spi@30820000 {
675 compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi";
676 #address-cells = <1>;
677 #size-cells = <0>;
678 reg = <0x30820000 0x10000>;
679 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
680 clocks = <&clk IMX8MN_CLK_ECSPI1_ROOT>,
681 <&clk IMX8MN_CLK_ECSPI1_ROOT>;
682 clock-names = "ipg", "per";
683 dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
684 dma-names = "rx", "tx";
685 status = "disabled";
686 };
687
688 ecspi2: spi@30830000 {
689 compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi";
690 #address-cells = <1>;
691 #size-cells = <0>;
692 reg = <0x30830000 0x10000>;
693 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
694 clocks = <&clk IMX8MN_CLK_ECSPI2_ROOT>,
695 <&clk IMX8MN_CLK_ECSPI2_ROOT>;
696 clock-names = "ipg", "per";
697 dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;
698 dma-names = "rx", "tx";
699 status = "disabled";
700 };
701
702 ecspi3: spi@30840000 {
703 compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi";
704 #address-cells = <1>;
705 #size-cells = <0>;
706 reg = <0x30840000 0x10000>;
707 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
708 clocks = <&clk IMX8MN_CLK_ECSPI3_ROOT>,
709 <&clk IMX8MN_CLK_ECSPI3_ROOT>;
710 clock-names = "ipg", "per";
711 dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;
712 dma-names = "rx", "tx";
713 status = "disabled";
714 };
715
716 uart1: serial@30860000 {
717 compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
718 reg = <0x30860000 0x10000>;
719 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
720 clocks = <&clk IMX8MN_CLK_UART1_ROOT>,
721 <&clk IMX8MN_CLK_UART1_ROOT>;
722 clock-names = "ipg", "per";
723 dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;
724 dma-names = "rx", "tx";
725 status = "disabled";
726 };
727
728 uart3: serial@30880000 {
729 compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
730 reg = <0x30880000 0x10000>;
731 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
732 clocks = <&clk IMX8MN_CLK_UART3_ROOT>,
733 <&clk IMX8MN_CLK_UART3_ROOT>;
734 clock-names = "ipg", "per";
735 dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;
736 dma-names = "rx", "tx";
737 status = "disabled";
738 };
739
740 uart2: serial@30890000 {
741 compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
742 reg = <0x30890000 0x10000>;
743 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
744 clocks = <&clk IMX8MN_CLK_UART2_ROOT>,
745 <&clk IMX8MN_CLK_UART2_ROOT>;
746 clock-names = "ipg", "per";
747 status = "disabled";
748 };
749
aad24175
HG		 750 crypto: crypto@30900000 {
751 compatible = "fsl,sec-v4.0";
752 #address-cells = <1>;
753 #size-cells = <1>;
754 reg = <0x30900000 0x40000>;
755 ranges = <0 0x30900000 0x40000>;
756 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
757 clocks = <&clk IMX8MN_CLK_AHB>,
758 <&clk IMX8MN_CLK_IPG_ROOT>;
759 clock-names = "aclk", "ipg";
760
f5ff5a21 761 sec_jr0: jr@1000 {
aad24175
HG		 762 compatible = "fsl,sec-v4.0-job-ring";
763 reg = <0x1000 0x1000>;
764 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
765 };
766
f5ff5a21 767 sec_jr1: jr@2000 {
aad24175
HG		 768 compatible = "fsl,sec-v4.0-job-ring";
769 reg = <0x2000 0x1000>;
770 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
771 };
772
f5ff5a21 773 sec_jr2: jr@3000 {
aad24175
HG		 774 compatible = "fsl,sec-v4.0-job-ring";
775 reg = <0x3000 0x1000>;
776 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
777 };
778 };
779
6c3debcb
AH		 780 i2c1: i2c@30a20000 {
781 compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c";
782 #address-cells = <1>;
783 #size-cells = <0>;
784 reg = <0x30a20000 0x10000>;
785 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
786 clocks = <&clk IMX8MN_CLK_I2C1_ROOT>;
787 status = "disabled";
788 };
789
790 i2c2: i2c@30a30000 {
791 compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c";
792 #address-cells = <1>;
793 #size-cells = <0>;
794 reg = <0x30a30000 0x10000>;
795 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
796 clocks = <&clk IMX8MN_CLK_I2C2_ROOT>;
797 status = "disabled";
798 };
799
800 i2c3: i2c@30a40000 {
801 #address-cells = <1>;
802 #size-cells = <0>;
803 compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c";
804 reg = <0x30a40000 0x10000>;
805 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
806 clocks = <&clk IMX8MN_CLK_I2C3_ROOT>;
807 status = "disabled";
808 };
809
810 i2c4: i2c@30a50000 {
811 compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c";
812 #address-cells = <1>;
813 #size-cells = <0>;
814 reg = <0x30a50000 0x10000>;
815 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
816 clocks = <&clk IMX8MN_CLK_I2C4_ROOT>;
817 status = "disabled";
818 };
819
820 uart4: serial@30a60000 {
821 compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
822 reg = <0x30a60000 0x10000>;
823 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
824 clocks = <&clk IMX8MN_CLK_UART4_ROOT>,
825 <&clk IMX8MN_CLK_UART4_ROOT>;
826 clock-names = "ipg", "per";
827 dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>;
828 dma-names = "rx", "tx";
829 status = "disabled";
830 };
831
bbfc59be
PF		 832 mu: mailbox@30aa0000 {
833 compatible = "fsl,imx8mn-mu", "fsl,imx6sx-mu";
834 reg = <0x30aa0000 0x10000>;
835 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
836 clocks = <&clk IMX8MN_CLK_MU_ROOT>;
837 #mbox-cells = <2>;
838 };
839
6c3debcb
AH		 840 usdhc1: mmc@30b40000 {
841 compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc";
842 reg = <0x30b40000 0x10000>;
843 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
ea65aba8 844 clocks = <&clk IMX8MN_CLK_IPG_ROOT>,
6c3debcb
AH		 845 <&clk IMX8MN_CLK_NAND_USDHC_BUS>,
846 <&clk IMX8MN_CLK_USDHC1_ROOT>;
847 clock-names = "ipg", "ahb", "per";
6c3debcb
AH		 848 fsl,tuning-start-tap = <20>;
849 fsl,tuning-step= <2>;
850 bus-width = <4>;
851 status = "disabled";
852 };
853
854 usdhc2: mmc@30b50000 {
855 compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc";
856 reg = <0x30b50000 0x10000>;
857 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
ea65aba8 858 clocks = <&clk IMX8MN_CLK_IPG_ROOT>,
6c3debcb
AH		 859 <&clk IMX8MN_CLK_NAND_USDHC_BUS>,
860 <&clk IMX8MN_CLK_USDHC2_ROOT>;
861 clock-names = "ipg", "ahb", "per";
862 fsl,tuning-start-tap = <20>;
863 fsl,tuning-step= <2>;
864 bus-width = <4>;
865 status = "disabled";
866 };
867
868 usdhc3: mmc@30b60000 {
869 compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc";
870 reg = <0x30b60000 0x10000>;
871 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
ea65aba8 872 clocks = <&clk IMX8MN_CLK_IPG_ROOT>,
6c3debcb
AH		 873 <&clk IMX8MN_CLK_NAND_USDHC_BUS>,
874 <&clk IMX8MN_CLK_USDHC3_ROOT>;
875 clock-names = "ipg", "ahb", "per";
6c3debcb
AH		 876 fsl,tuning-start-tap = <20>;
877 fsl,tuning-step= <2>;
878 bus-width = <4>;
879 status = "disabled";
880 };
881
882 sdma1: dma-controller@30bd0000 {
958c6014 883 compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma";
6c3debcb
AH		 884 reg = <0x30bd0000 0x10000>;
885 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
886 clocks = <&clk IMX8MN_CLK_SDMA1_ROOT>,
15ddc3e1 887 <&clk IMX8MN_CLK_AHB>;
6c3debcb
AH		 888 clock-names = "ipg", "ahb";
889 #dma-cells = <3>;
890 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
891 };
892
893 fec1: ethernet@30be0000 {
894 compatible = "fsl,imx8mn-fec", "fsl,imx6sx-fec";
895 reg = <0x30be0000 0x10000>;
896 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
897 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
d3762a47
FE		 898 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
899 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
6c3debcb
AH		 900 clocks = <&clk IMX8MN_CLK_ENET1_ROOT>,
901 <&clk IMX8MN_CLK_ENET1_ROOT>,
902 <&clk IMX8MN_CLK_ENET_TIMER>,
903 <&clk IMX8MN_CLK_ENET_REF>,
904 <&clk IMX8MN_CLK_ENET_PHY_REF>;
905 clock-names = "ipg", "ahb", "ptp",
906 "enet_clk_ref", "enet_out";
907 assigned-clocks = <&clk IMX8MN_CLK_ENET_AXI>,
908 <&clk IMX8MN_CLK_ENET_TIMER>,
909 <&clk IMX8MN_CLK_ENET_REF>,
910 <&clk IMX8MN_CLK_ENET_TIMER>;
911 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_266M>,
912 <&clk IMX8MN_SYS_PLL2_100M>,
913 <&clk IMX8MN_SYS_PLL2_125M>;
914 assigned-clock-rates = <0>, <0>, <125000000>, <100000000>;
915 fsl,num-tx-queues = <3>;
916 fsl,num-rx-queues = <3>;
917 status = "disabled";
918 };
919
920 };
921
922 aips4: bus@32c00000 {
dc3efc6f 923 compatible = "fsl,aips-bus", "simple-bus";
921a6845 924 reg = <0x32c00000 0x400000>;
6c3debcb
AH		 925 #address-cells = <1>;
926 #size-cells = <1>;
927 ranges;
928
929 usbotg1: usb@32e40000 {
930 compatible = "fsl,imx8mn-usb", "fsl,imx7d-usb";
931 reg = <0x32e40000 0x200>;
932 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
933 clocks = <&clk IMX8MN_CLK_USB1_CTRL_ROOT>;
934 clock-names = "usb1_ctrl_root_clk";
d51cb99c
LJ		 935 assigned-clocks = <&clk IMX8MN_CLK_USB_BUS>;
936 assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_500M>;
6c3debcb
AH		 937 fsl,usbphy = <&usbphynop1>;
938 fsl,usbmisc = <&usbmisc1 0>;
939 status = "disabled";
940 };
941
942 usbmisc1: usbmisc@32e40200 {
943 compatible = "fsl,imx8mn-usbmisc", "fsl,imx7d-usbmisc";
944 #index-cells = <1>;
945 reg = <0x32e40200 0x200>;
946 };
6c3debcb
AH		 947 };
948
949 dma_apbh: dma-controller@33000000 {
950 compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh";
951 reg = <0x33000000 0x2000>;
952 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
953 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
954 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
955 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
956 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
957 #dma-cells = <1>;
958 dma-channels = <4>;
959 clocks = <&clk IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK>;
960 };
961
962 gpmi: nand-controller@33002000 {
963 compatible = "fsl,imx8mn-gpmi-nand", "fsl,imx7d-gpmi-nand";
964 #address-cells = <1>;
965 #size-cells = <1>;
966 reg = <0x33002000 0x2000>, <0x33004000 0x4000>;
967 reg-names = "gpmi-nand", "bch";
968 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
969 interrupt-names = "bch";
970 clocks = <&clk IMX8MN_CLK_NAND_ROOT>,
971 <&clk IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK>;
972 clock-names = "gpmi_io", "gpmi_bch_apb";
973 dmas = <&dma_apbh 0>;
974 dma-names = "rx-tx";
975 status = "disabled";
976 };
977
978 gic: interrupt-controller@38800000 {
979 compatible = "arm,gic-v3";
980 reg = <0x38800000 0x10000>,
981 <0x38880000 0xc0000>;
982 #interrupt-cells = <3>;
983 interrupt-controller;
984 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
985 };
2d8e0747 986
0376f6ec
LC		 987 ddrc: memory-controller@3d400000 {
988 compatible = "fsl,imx8mn-ddrc", "fsl,imx8m-ddrc";
989 reg = <0x3d400000 0x400000>;
990 clock-names = "core", "pll", "alt", "apb";
991 clocks = <&clk IMX8MN_CLK_DRAM_CORE>,
992 <&clk IMX8MN_DRAM_PLL>,
993 <&clk IMX8MN_CLK_DRAM_ALT>,
994 <&clk IMX8MN_CLK_DRAM_APB>;
995 };
996
2d8e0747
JZ		 997 ddr-pmu@3d800000 {
998 compatible = "fsl,imx8mn-ddr-pmu", "fsl,imx8m-ddr-pmu";
999 reg = <0x3d800000 0x400000>;
1000 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1001 };
6c3debcb
AH		 1002 };
1003
1004 usbphynop1: usbphynop1 {
1005 compatible = "usb-nop-xceiv";
1006 clocks = <&clk IMX8MN_CLK_USB_PHY_REF>;
1007 assigned-clocks = <&clk IMX8MN_CLK_USB_PHY_REF>;
1008 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_100M>;
1009 clock-names = "main_clk";
1010 };
6c3debcb 1011};
Linux 6.x block layer and io_uring tree(s)