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arm64: dts: freescale: add Kontron sl28 support
[linux-2.6-block.git] / arch / arm64 / boot / dts / freescale / imx8mn.dtsi
CommitLineData
6c3debcb
AH		 1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2019 NXP
4 */
5
6#include <dt-bindings/clock/imx8mn-clock.h>
7#include <dt-bindings/gpio/gpio.h>
8#include <dt-bindings/input/input.h>
9#include <dt-bindings/interrupt-controller/arm-gic.h>
10
11#include "imx8mn-pinfunc.h"
12
13/ {
6c3debcb
AH		 14 interrupt-parent = <&gic>;
15 #address-cells = <2>;
16 #size-cells = <2>;
17
18 aliases {
19 ethernet0 = &fec1;
20 gpio0 = &gpio1;
21 gpio1 = &gpio2;
22 gpio2 = &gpio3;
23 gpio3 = &gpio4;
24 gpio4 = &gpio5;
25 i2c0 = &i2c1;
26 i2c1 = &i2c2;
27 i2c2 = &i2c3;
28 i2c3 = &i2c4;
29 mmc0 = &usdhc1;
30 mmc1 = &usdhc2;
31 mmc2 = &usdhc3;
32 serial0 = &uart1;
33 serial1 = &uart2;
34 serial2 = &uart3;
35 serial3 = &uart4;
36 spi0 = &ecspi1;
37 spi1 = &ecspi2;
38 spi2 = &ecspi3;
39 };
40
41 cpus {
42 #address-cells = <1>;
43 #size-cells = <0>;
44
df844a9a
AH		 45 idle-states {
46 entry-method = "psci";
47
48 cpu_pd_wait: cpu-pd-wait {
49 compatible = "arm,idle-state";
50 arm,psci-suspend-param = <0x0010033>;
51 local-timer-stop;
52 entry-latency-us = <1000>;
53 exit-latency-us = <700>;
54 min-residency-us = <2700>;
55 };
56 };
57
6c3debcb
AH		 58 A53_0: cpu@0 {
59 device_type = "cpu";
60 compatible = "arm,cortex-a53";
61 reg = <0x0>;
62 clock-latency = <61036>;
63 clocks = <&clk IMX8MN_CLK_ARM>;
64 enable-method = "psci";
65 next-level-cache = <&A53_L2>;
01c49314
AH		 66 operating-points-v2 = <&a53_opp_table>;
67 nvmem-cells = <&cpu_speed_grade>;
68 nvmem-cell-names = "speed_grade";
df844a9a 69 cpu-idle-states = <&cpu_pd_wait>;
6c3debcb
AH		 70 };
71
72 A53_1: cpu@1 {
73 device_type = "cpu";
74 compatible = "arm,cortex-a53";
75 reg = <0x1>;
76 clock-latency = <61036>;
77 clocks = <&clk IMX8MN_CLK_ARM>;
78 enable-method = "psci";
79 next-level-cache = <&A53_L2>;
01c49314 80 operating-points-v2 = <&a53_opp_table>;
df844a9a 81 cpu-idle-states = <&cpu_pd_wait>;
6c3debcb
AH		 82 };
83
84 A53_2: cpu@2 {
85 device_type = "cpu";
86 compatible = "arm,cortex-a53";
87 reg = <0x2>;
88 clock-latency = <61036>;
89 clocks = <&clk IMX8MN_CLK_ARM>;
90 enable-method = "psci";
91 next-level-cache = <&A53_L2>;
01c49314 92 operating-points-v2 = <&a53_opp_table>;
df844a9a 93 cpu-idle-states = <&cpu_pd_wait>;
6c3debcb
AH		 94 };
95
96 A53_3: cpu@3 {
97 device_type = "cpu";
98 compatible = "arm,cortex-a53";
99 reg = <0x3>;
100 clock-latency = <61036>;
101 clocks = <&clk IMX8MN_CLK_ARM>;
102 enable-method = "psci";
103 next-level-cache = <&A53_L2>;
01c49314 104 operating-points-v2 = <&a53_opp_table>;
df844a9a 105 cpu-idle-states = <&cpu_pd_wait>;
6c3debcb
AH		 106 };
107
108 A53_L2: l2-cache0 {
109 compatible = "cache";
110 };
111 };
112
01c49314
AH		 113 a53_opp_table: opp-table {
114 compatible = "operating-points-v2";
115 opp-shared;
116
117 opp-1200000000 {
118 opp-hz = /bits/ 64 <1200000000>;
119 opp-microvolt = <850000>;
120 opp-supported-hw = <0xb00>, <0x7>;
121 clock-latency-ns = <150000>;
122 opp-suspend;
123 };
124
125 opp-1400000000 {
126 opp-hz = /bits/ 64 <1400000000>;
127 opp-microvolt = <950000>;
128 opp-supported-hw = <0x300>, <0x7>;
129 clock-latency-ns = <150000>;
130 opp-suspend;
131 };
132
133 opp-1500000000 {
134 opp-hz = /bits/ 64 <1500000000>;
135 opp-microvolt = <1000000>;
136 opp-supported-hw = <0x100>, <0x3>;
137 clock-latency-ns = <150000>;
138 opp-suspend;
139 };
140 };
141
6c3debcb
AH		 142 osc_32k: clock-osc-32k {
143 compatible = "fixed-clock";
144 #clock-cells = <0>;
145 clock-frequency = <32768>;
146 clock-output-names = "osc_32k";
147 };
148
149 osc_24m: clock-osc-24m {
150 compatible = "fixed-clock";
151 #clock-cells = <0>;
152 clock-frequency = <24000000>;
153 clock-output-names = "osc_24m";
154 };
155
156 clk_ext1: clock-ext1 {
157 compatible = "fixed-clock";
158 #clock-cells = <0>;
159 clock-frequency = <133000000>;
160 clock-output-names = "clk_ext1";
161 };
162
163 clk_ext2: clock-ext2 {
164 compatible = "fixed-clock";
165 #clock-cells = <0>;
166 clock-frequency = <133000000>;
167 clock-output-names = "clk_ext2";
168 };
169
170 clk_ext3: clock-ext3 {
171 compatible = "fixed-clock";
172 #clock-cells = <0>;
173 clock-frequency = <133000000>;
174 clock-output-names = "clk_ext3";
175 };
176
177 clk_ext4: clock-ext4 {
178 compatible = "fixed-clock";
179 #clock-cells = <0>;
180 clock-frequency= <133000000>;
181 clock-output-names = "clk_ext4";
182 };
183
184 psci {
185 compatible = "arm,psci-1.0";
186 method = "smc";
187 };
188
189 timer {
190 compatible = "arm,armv8-timer";
191 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
192 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
193 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
194 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
195 clock-frequency = <8000000>;
196 arm,no-tick-in-suspend;
197 };
198
199 soc@0 {
200 compatible = "simple-bus";
201 #address-cells = <1>;
202 #size-cells = <1>;
203 ranges = <0x0 0x0 0x0 0x3e000000>;
204
205 aips1: bus@30000000 {
aebf07e6 206 compatible = "simple-bus";
6c3debcb
AH		 207 reg = <0x30000000 0x400000>;
208 #address-cells = <1>;
209 #size-cells = <1>;
210 ranges;
211
212 gpio1: gpio@30200000 {
213 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
214 reg = <0x30200000 0x10000>;
215 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
216 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
217 clocks = <&clk IMX8MN_CLK_GPIO1_ROOT>;
218 gpio-controller;
219 #gpio-cells = <2>;
220 interrupt-controller;
221 #interrupt-cells = <2>;
ee8696be 222 gpio-ranges = <&iomuxc 0 10 30>;
6c3debcb
AH		 223 };
224
225 gpio2: gpio@30210000 {
226 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
227 reg = <0x30210000 0x10000>;
228 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
229 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
230 clocks = <&clk IMX8MN_CLK_GPIO2_ROOT>;
231 gpio-controller;
232 #gpio-cells = <2>;
233 interrupt-controller;
234 #interrupt-cells = <2>;
ee8696be 235 gpio-ranges = <&iomuxc 0 40 21>;
6c3debcb
AH		 236 };
237
238 gpio3: gpio@30220000 {
239 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
240 reg = <0x30220000 0x10000>;
241 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
242 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
243 clocks = <&clk IMX8MN_CLK_GPIO3_ROOT>;
244 gpio-controller;
245 #gpio-cells = <2>;
246 interrupt-controller;
247 #interrupt-cells = <2>;
ee8696be 248 gpio-ranges = <&iomuxc 0 61 26>;
6c3debcb
AH		 249 };
250
251 gpio4: gpio@30230000 {
252 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
253 reg = <0x30230000 0x10000>;
254 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
255 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
256 clocks = <&clk IMX8MN_CLK_GPIO4_ROOT>;
257 gpio-controller;
258 #gpio-cells = <2>;
259 interrupt-controller;
260 #interrupt-cells = <2>;
ee8696be 261 gpio-ranges = <&iomuxc 21 108 11>;
6c3debcb
AH		 262 };
263
264 gpio5: gpio@30240000 {
265 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
266 reg = <0x30240000 0x10000>;
267 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
268 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
269 clocks = <&clk IMX8MN_CLK_GPIO5_ROOT>;
270 gpio-controller;
271 #gpio-cells = <2>;
272 interrupt-controller;
273 #interrupt-cells = <2>;
ee8696be 274 gpio-ranges = <&iomuxc 0 119 30>;
6c3debcb
AH		 275 };
276
277 wdog1: watchdog@30280000 {
278 compatible = "fsl,imx8mn-wdt", "fsl,imx21-wdt";
279 reg = <0x30280000 0x10000>;
280 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
281 clocks = <&clk IMX8MN_CLK_WDOG1_ROOT>;
282 status = "disabled";
283 };
284
285 wdog2: watchdog@30290000 {
286 compatible = "fsl,imx8mn-wdt", "fsl,imx21-wdt";
287 reg = <0x30290000 0x10000>;
288 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
289 clocks = <&clk IMX8MN_CLK_WDOG2_ROOT>;
290 status = "disabled";
291 };
292
293 wdog3: watchdog@302a0000 {
294 compatible = "fsl,imx8mn-wdt", "fsl,imx21-wdt";
295 reg = <0x302a0000 0x10000>;
296 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
297 clocks = <&clk IMX8MN_CLK_WDOG3_ROOT>;
298 status = "disabled";
299 };
300
301 sdma3: dma-controller@302b0000 {
958c6014 302 compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma";
6c3debcb
AH		 303 reg = <0x302b0000 0x10000>;
304 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
305 clocks = <&clk IMX8MN_CLK_SDMA3_ROOT>,
306 <&clk IMX8MN_CLK_SDMA3_ROOT>;
307 clock-names = "ipg", "ahb";
308 #dma-cells = <3>;
309 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
310 };
311
312 sdma2: dma-controller@302c0000 {
958c6014 313 compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma";
6c3debcb
AH		 314 reg = <0x302c0000 0x10000>;
315 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
316 clocks = <&clk IMX8MN_CLK_SDMA2_ROOT>,
317 <&clk IMX8MN_CLK_SDMA2_ROOT>;
318 clock-names = "ipg", "ahb";
319 #dma-cells = <3>;
320 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
321 };
322
323 iomuxc: pinctrl@30330000 {
324 compatible = "fsl,imx8mn-iomuxc";
325 reg = <0x30330000 0x10000>;
326 };
327
328 gpr: iomuxc-gpr@30340000 {
329 compatible = "fsl,imx8mn-iomuxc-gpr", "syscon";
330 reg = <0x30340000 0x10000>;
331 };
332
333 ocotp: ocotp-ctrl@30350000 {
2bad8c48 334 compatible = "fsl,imx8mn-ocotp", "fsl,imx8mm-ocotp", "syscon";
6c3debcb
AH		 335 reg = <0x30350000 0x10000>;
336 clocks = <&clk IMX8MN_CLK_OCOTP_ROOT>;
01c49314
AH		 337 #address-cells = <1>;
338 #size-cells = <1>;
339
340 cpu_speed_grade: speed-grade@10 {
341 reg = <0x10 4>;
342 };
6c3debcb
AH		 343 };
344
345 anatop: anatop@30360000 {
346 compatible = "fsl,imx8mn-anatop", "fsl,imx8mm-anatop",
0f93eb28 347 "syscon";
6c3debcb
AH		 348 reg = <0x30360000 0x10000>;
349 };
350
351 snvs: snvs@30370000 {
352 compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd";
353 reg = <0x30370000 0x10000>;
354
355 snvs_rtc: snvs-rtc-lp {
356 compatible = "fsl,sec-v4.0-mon-rtc-lp";
357 regmap = <&snvs>;
358 offset = <0x34>;
359 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
360 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
42ef961b 361 clocks = <&clk IMX8MN_CLK_SNVS_ROOT>;
6c3debcb
AH		 362 clock-names = "snvs-rtc";
363 };
364
365 snvs_pwrkey: snvs-powerkey {
366 compatible = "fsl,sec-v4.0-pwrkey";
367 regmap = <&snvs>;
368 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
369 linux,keycode = <KEY_POWER>;
370 wakeup-source;
371 status = "disabled";
372 };
373 };
374
375 clk: clock-controller@30380000 {
376 compatible = "fsl,imx8mn-ccm";
377 reg = <0x30380000 0x10000>;
378 #clock-cells = <1>;
379 clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>,
380 <&clk_ext3>, <&clk_ext4>;
381 clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
382 "clk_ext3", "clk_ext4";
383 };
384
385 src: reset-controller@30390000 {
23b80c20 386 compatible = "fsl,imx8mn-src", "fsl,imx8mq-src", "syscon";
6c3debcb
AH		 387 reg = <0x30390000 0x10000>;
388 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
389 #reset-cells = <1>;
390 };
391 };
392
393 aips2: bus@30400000 {
aebf07e6 394 compatible = "simple-bus";
6c3debcb
AH		 395 reg = <0x30400000 0x400000>;
396 #address-cells = <1>;
397 #size-cells = <1>;
398 ranges;
399
400 pwm1: pwm@30660000 {
401 compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm";
402 reg = <0x30660000 0x10000>;
403 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
404 clocks = <&clk IMX8MN_CLK_PWM1_ROOT>,
405 <&clk IMX8MN_CLK_PWM1_ROOT>;
406 clock-names = "ipg", "per";
407 #pwm-cells = <2>;
408 status = "disabled";
409 };
410
411 pwm2: pwm@30670000 {
412 compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm";
413 reg = <0x30670000 0x10000>;
414 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
415 clocks = <&clk IMX8MN_CLK_PWM2_ROOT>,
416 <&clk IMX8MN_CLK_PWM2_ROOT>;
417 clock-names = "ipg", "per";
418 #pwm-cells = <2>;
419 status = "disabled";
420 };
421
422 pwm3: pwm@30680000 {
423 compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm";
424 reg = <0x30680000 0x10000>;
425 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
426 clocks = <&clk IMX8MN_CLK_PWM3_ROOT>,
427 <&clk IMX8MN_CLK_PWM3_ROOT>;
428 clock-names = "ipg", "per";
429 #pwm-cells = <2>;
430 status = "disabled";
431 };
432
433 pwm4: pwm@30690000 {
434 compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm";
435 reg = <0x30690000 0x10000>;
436 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
437 clocks = <&clk IMX8MN_CLK_PWM4_ROOT>,
438 <&clk IMX8MN_CLK_PWM4_ROOT>;
439 clock-names = "ipg", "per";
440 #pwm-cells = <2>;
441 status = "disabled";
442 };
c4a21269
AH		 443
444 system_counter: timer@306a0000 {
445 compatible = "nxp,sysctr-timer";
446 reg = <0x306a0000 0x20000>;
447 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
448 clocks = <&osc_24m>;
449 clock-names = "per";
450 };
6c3debcb
AH		 451 };
452
453 aips3: bus@30800000 {
aebf07e6 454 compatible = "simple-bus";
6c3debcb
AH		 455 reg = <0x30800000 0x400000>;
456 #address-cells = <1>;
457 #size-cells = <1>;
458 ranges;
459
460 ecspi1: spi@30820000 {
461 compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi";
462 #address-cells = <1>;
463 #size-cells = <0>;
464 reg = <0x30820000 0x10000>;
465 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
466 clocks = <&clk IMX8MN_CLK_ECSPI1_ROOT>,
467 <&clk IMX8MN_CLK_ECSPI1_ROOT>;
468 clock-names = "ipg", "per";
469 dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
470 dma-names = "rx", "tx";
471 status = "disabled";
472 };
473
474 ecspi2: spi@30830000 {
475 compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi";
476 #address-cells = <1>;
477 #size-cells = <0>;
478 reg = <0x30830000 0x10000>;
479 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
480 clocks = <&clk IMX8MN_CLK_ECSPI2_ROOT>,
481 <&clk IMX8MN_CLK_ECSPI2_ROOT>;
482 clock-names = "ipg", "per";
483 dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;
484 dma-names = "rx", "tx";
485 status = "disabled";
486 };
487
488 ecspi3: spi@30840000 {
489 compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi";
490 #address-cells = <1>;
491 #size-cells = <0>;
492 reg = <0x30840000 0x10000>;
493 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
494 clocks = <&clk IMX8MN_CLK_ECSPI3_ROOT>,
495 <&clk IMX8MN_CLK_ECSPI3_ROOT>;
496 clock-names = "ipg", "per";
497 dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;
498 dma-names = "rx", "tx";
499 status = "disabled";
500 };
501
502 uart1: serial@30860000 {
503 compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
504 reg = <0x30860000 0x10000>;
505 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
506 clocks = <&clk IMX8MN_CLK_UART1_ROOT>,
507 <&clk IMX8MN_CLK_UART1_ROOT>;
508 clock-names = "ipg", "per";
509 dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;
510 dma-names = "rx", "tx";
511 status = "disabled";
512 };
513
514 uart3: serial@30880000 {
515 compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
516 reg = <0x30880000 0x10000>;
517 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
518 clocks = <&clk IMX8MN_CLK_UART3_ROOT>,
519 <&clk IMX8MN_CLK_UART3_ROOT>;
520 clock-names = "ipg", "per";
521 dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;
522 dma-names = "rx", "tx";
523 status = "disabled";
524 };
525
526 uart2: serial@30890000 {
527 compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
528 reg = <0x30890000 0x10000>;
529 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
530 clocks = <&clk IMX8MN_CLK_UART2_ROOT>,
531 <&clk IMX8MN_CLK_UART2_ROOT>;
532 clock-names = "ipg", "per";
533 status = "disabled";
534 };
535
aad24175
HG		 536 crypto: crypto@30900000 {
537 compatible = "fsl,sec-v4.0";
538 #address-cells = <1>;
539 #size-cells = <1>;
540 reg = <0x30900000 0x40000>;
541 ranges = <0 0x30900000 0x40000>;
542 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
543 clocks = <&clk IMX8MN_CLK_AHB>,
544 <&clk IMX8MN_CLK_IPG_ROOT>;
545 clock-names = "aclk", "ipg";
546
547 sec_jr0: jr0@1000 {
548 compatible = "fsl,sec-v4.0-job-ring";
549 reg = <0x1000 0x1000>;
550 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
551 };
552
553 sec_jr1: jr1@2000 {
554 compatible = "fsl,sec-v4.0-job-ring";
555 reg = <0x2000 0x1000>;
556 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
557 };
558
559 sec_jr2: jr2@3000 {
560 compatible = "fsl,sec-v4.0-job-ring";
561 reg = <0x3000 0x1000>;
562 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
563 };
564 };
565
6c3debcb
AH		 566 i2c1: i2c@30a20000 {
567 compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c";
568 #address-cells = <1>;
569 #size-cells = <0>;
570 reg = <0x30a20000 0x10000>;
571 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
572 clocks = <&clk IMX8MN_CLK_I2C1_ROOT>;
573 status = "disabled";
574 };
575
576 i2c2: i2c@30a30000 {
577 compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c";
578 #address-cells = <1>;
579 #size-cells = <0>;
580 reg = <0x30a30000 0x10000>;
581 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
582 clocks = <&clk IMX8MN_CLK_I2C2_ROOT>;
583 status = "disabled";
584 };
585
586 i2c3: i2c@30a40000 {
587 #address-cells = <1>;
588 #size-cells = <0>;
589 compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c";
590 reg = <0x30a40000 0x10000>;
591 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
592 clocks = <&clk IMX8MN_CLK_I2C3_ROOT>;
593 status = "disabled";
594 };
595
596 i2c4: i2c@30a50000 {
597 compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c";
598 #address-cells = <1>;
599 #size-cells = <0>;
600 reg = <0x30a50000 0x10000>;
601 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
602 clocks = <&clk IMX8MN_CLK_I2C4_ROOT>;
603 status = "disabled";
604 };
605
606 uart4: serial@30a60000 {
607 compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
608 reg = <0x30a60000 0x10000>;
609 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
610 clocks = <&clk IMX8MN_CLK_UART4_ROOT>,
611 <&clk IMX8MN_CLK_UART4_ROOT>;
612 clock-names = "ipg", "per";
613 dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>;
614 dma-names = "rx", "tx";
615 status = "disabled";
616 };
617
618 usdhc1: mmc@30b40000 {
619 compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc";
620 reg = <0x30b40000 0x10000>;
621 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
ea65aba8 622 clocks = <&clk IMX8MN_CLK_IPG_ROOT>,
6c3debcb
AH		 623 <&clk IMX8MN_CLK_NAND_USDHC_BUS>,
624 <&clk IMX8MN_CLK_USDHC1_ROOT>;
625 clock-names = "ipg", "ahb", "per";
6c3debcb
AH		 626 fsl,tuning-start-tap = <20>;
627 fsl,tuning-step= <2>;
628 bus-width = <4>;
629 status = "disabled";
630 };
631
632 usdhc2: mmc@30b50000 {
633 compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc";
634 reg = <0x30b50000 0x10000>;
635 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
ea65aba8 636 clocks = <&clk IMX8MN_CLK_IPG_ROOT>,
6c3debcb
AH		 637 <&clk IMX8MN_CLK_NAND_USDHC_BUS>,
638 <&clk IMX8MN_CLK_USDHC2_ROOT>;
639 clock-names = "ipg", "ahb", "per";
640 fsl,tuning-start-tap = <20>;
641 fsl,tuning-step= <2>;
642 bus-width = <4>;
643 status = "disabled";
644 };
645
646 usdhc3: mmc@30b60000 {
647 compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc";
648 reg = <0x30b60000 0x10000>;
649 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
ea65aba8 650 clocks = <&clk IMX8MN_CLK_IPG_ROOT>,
6c3debcb
AH		 651 <&clk IMX8MN_CLK_NAND_USDHC_BUS>,
652 <&clk IMX8MN_CLK_USDHC3_ROOT>;
653 clock-names = "ipg", "ahb", "per";
6c3debcb
AH		 654 fsl,tuning-start-tap = <20>;
655 fsl,tuning-step= <2>;
656 bus-width = <4>;
657 status = "disabled";
658 };
659
660 sdma1: dma-controller@30bd0000 {
958c6014 661 compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma";
6c3debcb
AH		 662 reg = <0x30bd0000 0x10000>;
663 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
664 clocks = <&clk IMX8MN_CLK_SDMA1_ROOT>,
665 <&clk IMX8MN_CLK_SDMA1_ROOT>;
666 clock-names = "ipg", "ahb";
667 #dma-cells = <3>;
668 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
669 };
670
671 fec1: ethernet@30be0000 {
672 compatible = "fsl,imx8mn-fec", "fsl,imx6sx-fec";
673 reg = <0x30be0000 0x10000>;
674 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
675 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
676 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
677 clocks = <&clk IMX8MN_CLK_ENET1_ROOT>,
678 <&clk IMX8MN_CLK_ENET1_ROOT>,
679 <&clk IMX8MN_CLK_ENET_TIMER>,
680 <&clk IMX8MN_CLK_ENET_REF>,
681 <&clk IMX8MN_CLK_ENET_PHY_REF>;
682 clock-names = "ipg", "ahb", "ptp",
683 "enet_clk_ref", "enet_out";
684 assigned-clocks = <&clk IMX8MN_CLK_ENET_AXI>,
685 <&clk IMX8MN_CLK_ENET_TIMER>,
686 <&clk IMX8MN_CLK_ENET_REF>,
687 <&clk IMX8MN_CLK_ENET_TIMER>;
688 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_266M>,
689 <&clk IMX8MN_SYS_PLL2_100M>,
690 <&clk IMX8MN_SYS_PLL2_125M>;
691 assigned-clock-rates = <0>, <0>, <125000000>, <100000000>;
692 fsl,num-tx-queues = <3>;
693 fsl,num-rx-queues = <3>;
694 status = "disabled";
695 };
696
697 };
698
699 aips4: bus@32c00000 {
aebf07e6 700 compatible = "simple-bus";
6c3debcb
AH		 701 reg = <0x32c00000 0x400000>;
702 #address-cells = <1>;
703 #size-cells = <1>;
704 ranges;
705
706 usbotg1: usb@32e40000 {
707 compatible = "fsl,imx8mn-usb", "fsl,imx7d-usb";
708 reg = <0x32e40000 0x200>;
709 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
710 clocks = <&clk IMX8MN_CLK_USB1_CTRL_ROOT>;
711 clock-names = "usb1_ctrl_root_clk";
d51cb99c
LJ		 712 assigned-clocks = <&clk IMX8MN_CLK_USB_BUS>;
713 assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_500M>;
6c3debcb
AH		 714 fsl,usbphy = <&usbphynop1>;
715 fsl,usbmisc = <&usbmisc1 0>;
716 status = "disabled";
717 };
718
719 usbmisc1: usbmisc@32e40200 {
720 compatible = "fsl,imx8mn-usbmisc", "fsl,imx7d-usbmisc";
721 #index-cells = <1>;
722 reg = <0x32e40200 0x200>;
723 };
724
725 usbotg2: usb@32e50000 {
726 compatible = "fsl,imx8mn-usb", "fsl,imx7d-usb";
727 reg = <0x32e50000 0x200>;
728 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
729 clocks = <&clk IMX8MN_CLK_USB1_CTRL_ROOT>;
730 clock-names = "usb1_ctrl_root_clk";
731 assigned-clocks = <&clk IMX8MN_CLK_USB_BUS>,
732 <&clk IMX8MN_CLK_USB_CORE_REF>;
733 assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_500M>,
734 <&clk IMX8MN_SYS_PLL1_100M>;
735 fsl,usbphy = <&usbphynop2>;
736 fsl,usbmisc = <&usbmisc2 0>;
737 status = "disabled";
738 };
739
740 usbmisc2: usbmisc@32e50200 {
741 compatible = "fsl,imx8mn-usbmisc", "fsl,imx7d-usbmisc";
742 #index-cells = <1>;
743 reg = <0x32e50200 0x200>;
744 };
745
746 };
747
748 dma_apbh: dma-controller@33000000 {
749 compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh";
750 reg = <0x33000000 0x2000>;
751 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
752 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
753 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
754 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
755 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
756 #dma-cells = <1>;
757 dma-channels = <4>;
758 clocks = <&clk IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK>;
759 };
760
761 gpmi: nand-controller@33002000 {
762 compatible = "fsl,imx8mn-gpmi-nand", "fsl,imx7d-gpmi-nand";
763 #address-cells = <1>;
764 #size-cells = <1>;
765 reg = <0x33002000 0x2000>, <0x33004000 0x4000>;
766 reg-names = "gpmi-nand", "bch";
767 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
768 interrupt-names = "bch";
769 clocks = <&clk IMX8MN_CLK_NAND_ROOT>,
770 <&clk IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK>;
771 clock-names = "gpmi_io", "gpmi_bch_apb";
772 dmas = <&dma_apbh 0>;
773 dma-names = "rx-tx";
774 status = "disabled";
775 };
776
777 gic: interrupt-controller@38800000 {
778 compatible = "arm,gic-v3";
779 reg = <0x38800000 0x10000>,
780 <0x38880000 0xc0000>;
781 #interrupt-cells = <3>;
782 interrupt-controller;
783 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
784 };
2d8e0747 785
0376f6ec
LC		 786 ddrc: memory-controller@3d400000 {
787 compatible = "fsl,imx8mn-ddrc", "fsl,imx8m-ddrc";
788 reg = <0x3d400000 0x400000>;
789 clock-names = "core", "pll", "alt", "apb";
790 clocks = <&clk IMX8MN_CLK_DRAM_CORE>,
791 <&clk IMX8MN_DRAM_PLL>,
792 <&clk IMX8MN_CLK_DRAM_ALT>,
793 <&clk IMX8MN_CLK_DRAM_APB>;
794 };
795
2d8e0747
JZ		 796 ddr-pmu@3d800000 {
797 compatible = "fsl,imx8mn-ddr-pmu", "fsl,imx8m-ddr-pmu";
798 reg = <0x3d800000 0x400000>;
799 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
800 };
6c3debcb
AH		 801 };
802
803 usbphynop1: usbphynop1 {
804 compatible = "usb-nop-xceiv";
805 clocks = <&clk IMX8MN_CLK_USB_PHY_REF>;
806 assigned-clocks = <&clk IMX8MN_CLK_USB_PHY_REF>;
807 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_100M>;
808 clock-names = "main_clk";
809 };
810
811 usbphynop2: usbphynop2 {
812 compatible = "usb-nop-xceiv";
813 clocks = <&clk IMX8MN_CLK_USB_PHY_REF>;
814 assigned-clocks = <&clk IMX8MN_CLK_USB_PHY_REF>;
815 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_100M>;
816 clock-names = "main_clk";
817 };
818};
Linux 6.x block layer and io_uring tree(s)