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arm64: dts: imx8mm-phg: Add initial board support
[linux-2.6-block.git] / arch / arm64 / boot / dts / freescale / imx8mn.dtsi
CommitLineData
6c3debcb
AH		 1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2019 NXP
4 */
5
6#include <dt-bindings/clock/imx8mn-clock.h>
8b8ebec6
AF		 7#include <dt-bindings/power/imx8mn-power.h>
8#include <dt-bindings/reset/imx8mq-reset.h>
6c3debcb
AH		 9#include <dt-bindings/gpio/gpio.h>
10#include <dt-bindings/input/input.h>
11#include <dt-bindings/interrupt-controller/arm-gic.h>
819779a9 12#include <dt-bindings/thermal/thermal.h>
6c3debcb
AH		 13
14#include "imx8mn-pinfunc.h"
15
16/ {
6c3debcb
AH		 17 interrupt-parent = <&gic>;
18 #address-cells = <2>;
19 #size-cells = <2>;
20
21 aliases {
22 ethernet0 = &fec1;
23 gpio0 = &gpio1;
24 gpio1 = &gpio2;
25 gpio2 = &gpio3;
26 gpio3 = &gpio4;
27 gpio4 = &gpio5;
28 i2c0 = &i2c1;
29 i2c1 = &i2c2;
30 i2c2 = &i2c3;
31 i2c3 = &i2c4;
32 mmc0 = &usdhc1;
33 mmc1 = &usdhc2;
34 mmc2 = &usdhc3;
35 serial0 = &uart1;
36 serial1 = &uart2;
37 serial2 = &uart3;
38 serial3 = &uart4;
39 spi0 = &ecspi1;
40 spi1 = &ecspi2;
41 spi2 = &ecspi3;
42 };
43
44 cpus {
45 #address-cells = <1>;
46 #size-cells = <0>;
47
df844a9a
AH		 48 idle-states {
49 entry-method = "psci";
50
51 cpu_pd_wait: cpu-pd-wait {
52 compatible = "arm,idle-state";
53 arm,psci-suspend-param = <0x0010033>;
54 local-timer-stop;
55 entry-latency-us = <1000>;
56 exit-latency-us = <700>;
57 min-residency-us = <2700>;
58 };
59 };
60
6c3debcb
AH		 61 A53_0: cpu@0 {
62 device_type = "cpu";
63 compatible = "arm,cortex-a53";
64 reg = <0x0>;
65 clock-latency = <61036>;
66 clocks = <&clk IMX8MN_CLK_ARM>;
67 enable-method = "psci";
cb551b5e
PF		 68 i-cache-size = <0x8000>;
69 i-cache-line-size = <64>;
70 i-cache-sets = <256>;
71 d-cache-size = <0x8000>;
72 d-cache-line-size = <64>;
73 d-cache-sets = <128>;
6c3debcb 74 next-level-cache = <&A53_L2>;
01c49314
AH		 75 operating-points-v2 = <&a53_opp_table>;
76 nvmem-cells = <&cpu_speed_grade>;
77 nvmem-cell-names = "speed_grade";
df844a9a 78 cpu-idle-states = <&cpu_pd_wait>;
819779a9 79 #cooling-cells = <2>;
6c3debcb
AH		 80 };
81
82 A53_1: cpu@1 {
83 device_type = "cpu";
84 compatible = "arm,cortex-a53";
85 reg = <0x1>;
86 clock-latency = <61036>;
87 clocks = <&clk IMX8MN_CLK_ARM>;
88 enable-method = "psci";
cb551b5e
PF		 89 i-cache-size = <0x8000>;
90 i-cache-line-size = <64>;
91 i-cache-sets = <256>;
92 d-cache-size = <0x8000>;
93 d-cache-line-size = <64>;
94 d-cache-sets = <128>;
6c3debcb 95 next-level-cache = <&A53_L2>;
01c49314 96 operating-points-v2 = <&a53_opp_table>;
df844a9a 97 cpu-idle-states = <&cpu_pd_wait>;
819779a9 98 #cooling-cells = <2>;
6c3debcb
AH		 99 };
100
101 A53_2: cpu@2 {
102 device_type = "cpu";
103 compatible = "arm,cortex-a53";
104 reg = <0x2>;
105 clock-latency = <61036>;
106 clocks = <&clk IMX8MN_CLK_ARM>;
107 enable-method = "psci";
cb551b5e
PF		 108 i-cache-size = <0x8000>;
109 i-cache-line-size = <64>;
110 i-cache-sets = <256>;
111 d-cache-size = <0x8000>;
112 d-cache-line-size = <64>;
113 d-cache-sets = <128>;
6c3debcb 114 next-level-cache = <&A53_L2>;
01c49314 115 operating-points-v2 = <&a53_opp_table>;
df844a9a 116 cpu-idle-states = <&cpu_pd_wait>;
819779a9 117 #cooling-cells = <2>;
6c3debcb
AH		 118 };
119
120 A53_3: cpu@3 {
121 device_type = "cpu";
122 compatible = "arm,cortex-a53";
123 reg = <0x3>;
124 clock-latency = <61036>;
125 clocks = <&clk IMX8MN_CLK_ARM>;
126 enable-method = "psci";
cb551b5e
PF		 127 i-cache-size = <0x8000>;
128 i-cache-line-size = <64>;
129 i-cache-sets = <256>;
130 d-cache-size = <0x8000>;
131 d-cache-line-size = <64>;
132 d-cache-sets = <128>;
6c3debcb 133 next-level-cache = <&A53_L2>;
01c49314 134 operating-points-v2 = <&a53_opp_table>;
df844a9a 135 cpu-idle-states = <&cpu_pd_wait>;
819779a9 136 #cooling-cells = <2>;
6c3debcb
AH		 137 };
138
139 A53_L2: l2-cache0 {
140 compatible = "cache";
cb551b5e
PF		 141 cache-level = <2>;
142 cache-size = <0x80000>;
143 cache-line-size = <64>;
144 cache-sets = <512>;
6c3debcb
AH		 145 };
146 };
147
01c49314
AH		 148 a53_opp_table: opp-table {
149 compatible = "operating-points-v2";
150 opp-shared;
151
152 opp-1200000000 {
153 opp-hz = /bits/ 64 <1200000000>;
8c30e7ca 154 opp-microvolt = <850000>;
01c49314
AH		 155 opp-supported-hw = <0xb00>, <0x7>;
156 clock-latency-ns = <150000>;
157 opp-suspend;
158 };
159
160 opp-1400000000 {
161 opp-hz = /bits/ 64 <1400000000>;
162 opp-microvolt = <950000>;
163 opp-supported-hw = <0x300>, <0x7>;
164 clock-latency-ns = <150000>;
165 opp-suspend;
166 };
167
168 opp-1500000000 {
169 opp-hz = /bits/ 64 <1500000000>;
170 opp-microvolt = <1000000>;
171 opp-supported-hw = <0x100>, <0x3>;
172 clock-latency-ns = <150000>;
173 opp-suspend;
174 };
175 };
176
6c3debcb
AH		 177 osc_32k: clock-osc-32k {
178 compatible = "fixed-clock";
179 #clock-cells = <0>;
180 clock-frequency = <32768>;
181 clock-output-names = "osc_32k";
182 };
183
184 osc_24m: clock-osc-24m {
185 compatible = "fixed-clock";
186 #clock-cells = <0>;
187 clock-frequency = <24000000>;
188 clock-output-names = "osc_24m";
189 };
190
191 clk_ext1: clock-ext1 {
192 compatible = "fixed-clock";
193 #clock-cells = <0>;
194 clock-frequency = <133000000>;
195 clock-output-names = "clk_ext1";
196 };
197
198 clk_ext2: clock-ext2 {
199 compatible = "fixed-clock";
200 #clock-cells = <0>;
201 clock-frequency = <133000000>;
202 clock-output-names = "clk_ext2";
203 };
204
205 clk_ext3: clock-ext3 {
206 compatible = "fixed-clock";
207 #clock-cells = <0>;
208 clock-frequency = <133000000>;
209 clock-output-names = "clk_ext3";
210 };
211
212 clk_ext4: clock-ext4 {
213 compatible = "fixed-clock";
214 #clock-cells = <0>;
33597c62 215 clock-frequency = <133000000>;
6c3debcb
AH		 216 clock-output-names = "clk_ext4";
217 };
218
c13a7d84
JB		 219 pmu {
220 compatible = "arm,cortex-a53-pmu";
221 interrupts = <GIC_PPI 7
222 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
c13a7d84
JB		 223 };
224
6c3debcb
AH		 225 psci {
226 compatible = "arm,psci-1.0";
227 method = "smc";
228 };
229
819779a9
AH		 230 thermal-zones {
231 cpu-thermal {
232 polling-delay-passive = <250>;
233 polling-delay = <2000>;
234 thermal-sensors = <&tmu>;
235 trips {
236 cpu_alert0: trip0 {
237 temperature = <85000>;
238 hysteresis = <2000>;
239 type = "passive";
240 };
241
242 cpu_crit0: trip1 {
243 temperature = <95000>;
244 hysteresis = <2000>;
245 type = "critical";
246 };
247 };
248
249 cooling-maps {
250 map0 {
251 trip = <&cpu_alert0>;
252 cooling-device =
253 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
254 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
255 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
256 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
257 };
258 };
259 };
260 };
261
6c3debcb
AH		 262 timer {
263 compatible = "arm,armv8-timer";
0656e37a
KK		 264 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
265 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
266 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
267 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
6c3debcb
AH		 268 clock-frequency = <8000000>;
269 arm,no-tick-in-suspend;
270 };
271
fcdef92b 272 soc: soc@0 {
ce58459d 273 compatible = "fsl,imx8mn-soc", "simple-bus";
6c3debcb
AH		 274 #address-cells = <1>;
275 #size-cells = <1>;
276 ranges = <0x0 0x0 0x0 0x3e000000>;
8d923cdf 277 dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>;
cbff2379
AG		 278 nvmem-cells = <&imx8mn_uid>;
279 nvmem-cell-names = "soc_unique_id";
6c3debcb
AH		 280
281 aips1: bus@30000000 {
dc3efc6f 282 compatible = "fsl,aips-bus", "simple-bus";
921a6845 283 reg = <0x30000000 0x400000>;
6c3debcb
AH		 284 #address-cells = <1>;
285 #size-cells = <1>;
286 ranges;
287
292e0f48 288 spba2: spba-bus@30000000 {
970406ea
AF		 289 compatible = "fsl,spba-bus", "simple-bus";
290 #address-cells = <1>;
291 #size-cells = <1>;
292 reg = <0x30000000 0x100000>;
293 ranges;
294
9e986006 295 sai2: sai@30020000 {
574518b7 296 compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai";
9e986006
AF		 297 reg = <0x30020000 0x10000>;
298 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
299 clocks = <&clk IMX8MN_CLK_SAI2_IPG>,
300 <&clk IMX8MN_CLK_DUMMY>,
301 <&clk IMX8MN_CLK_SAI2_ROOT>,
302 <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>;
303 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
304 dmas = <&sdma2 2 2 0>, <&sdma2 3 2 0>;
305 dma-names = "rx", "tx";
306 status = "disabled";
307 };
308
309 sai3: sai@30030000 {
574518b7 310 compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai";
9e986006
AF		 311 reg = <0x30030000 0x10000>;
312 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
313 clocks = <&clk IMX8MN_CLK_SAI3_IPG>,
314 <&clk IMX8MN_CLK_DUMMY>,
315 <&clk IMX8MN_CLK_SAI3_ROOT>,
316 <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>;
317 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
318 dmas = <&sdma2 4 2 0>, <&sdma2 5 2 0>;
319 dma-names = "rx", "tx";
320 status = "disabled";
321 };
322
323 sai5: sai@30050000 {
574518b7 324 compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai";
9e986006
AF		 325 reg = <0x30050000 0x10000>;
326 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
327 clocks = <&clk IMX8MN_CLK_SAI5_IPG>,
328 <&clk IMX8MN_CLK_DUMMY>,
329 <&clk IMX8MN_CLK_SAI5_ROOT>,
330 <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>;
331 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
332 dmas = <&sdma2 8 2 0>, <&sdma2 9 2 0>;
333 dma-names = "rx", "tx";
334 fsl,shared-interrupt;
335 fsl,dataline = <0 0xf 0xf>;
336 status = "disabled";
337 };
338
339 sai6: sai@30060000 {
574518b7 340 compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai";
9e986006
AF		 341 reg = <0x30060000 0x10000>;
342 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
343 clocks = <&clk IMX8MN_CLK_SAI6_IPG>,
344 <&clk IMX8MN_CLK_DUMMY>,
345 <&clk IMX8MN_CLK_SAI6_ROOT>,
346 <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>;
347 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
348 dmas = <&sdma2 10 2 0>, <&sdma2 11 2 0>;
349 dma-names = "rx", "tx";
350 status = "disabled";
351 };
352
cca69ef6
AF		 353 micfil: audio-controller@30080000 {
354 compatible = "fsl,imx8mm-micfil";
355 reg = <0x30080000 0x10000>;
356 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
357 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
358 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
359 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
360 clocks = <&clk IMX8MN_CLK_PDM_IPG>,
361 <&clk IMX8MN_CLK_PDM_ROOT>,
362 <&clk IMX8MN_AUDIO_PLL1_OUT>,
363 <&clk IMX8MN_AUDIO_PLL2_OUT>,
364 <&clk IMX8MN_CLK_EXT3>;
365 clock-names = "ipg_clk", "ipg_clk_app",
366 "pll8k", "pll11k", "clkext3";
367 dmas = <&sdma2 24 25 0x80000000>;
368 dma-names = "rx";
369 status = "disabled";
370 };
371
b9cf7d3b
AF		 372 spdif1: spdif@30090000 {
373 compatible = "fsl,imx35-spdif";
374 reg = <0x30090000 0x10000>;
375 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
376 clocks = <&clk IMX8MN_CLK_AUDIO_AHB>, /* core */
377 <&clk IMX8MN_CLK_24M>, /* rxtx0 */
378 <&clk IMX8MN_CLK_SPDIF1>, /* rxtx1 */
379 <&clk IMX8MN_CLK_DUMMY>, /* rxtx2 */
380 <&clk IMX8MN_CLK_DUMMY>, /* rxtx3 */
381 <&clk IMX8MN_CLK_DUMMY>, /* rxtx4 */
382 <&clk IMX8MN_CLK_AUDIO_AHB>, /* rxtx5 */
383 <&clk IMX8MN_CLK_DUMMY>, /* rxtx6 */
384 <&clk IMX8MN_CLK_DUMMY>, /* rxtx7 */
385 <&clk IMX8MN_CLK_DUMMY>; /* spba */
386 clock-names = "core", "rxtx0",
387 "rxtx1", "rxtx2",
388 "rxtx3", "rxtx4",
389 "rxtx5", "rxtx6",
390 "rxtx7", "spba";
391 dmas = <&sdma2 28 18 0>, <&sdma2 29 18 0>;
392 dma-names = "rx", "tx";
393 status = "disabled";
394 };
395
9e986006 396 sai7: sai@300b0000 {
574518b7 397 compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai";
9e986006
AF		 398 reg = <0x300b0000 0x10000>;
399 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
400 clocks = <&clk IMX8MN_CLK_SAI7_IPG>,
401 <&clk IMX8MN_CLK_DUMMY>,
402 <&clk IMX8MN_CLK_SAI7_ROOT>,
403 <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>;
404 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
405 dmas = <&sdma2 12 2 0>, <&sdma2 13 2 0>;
406 dma-names = "rx", "tx";
407 status = "disabled";
408 };
409
970406ea
AF		 410 easrc: easrc@300c0000 {
411 compatible = "fsl,imx8mn-easrc";
412 reg = <0x300c0000 0x10000>;
413 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
414 clocks = <&clk IMX8MN_CLK_ASRC_ROOT>;
415 clock-names = "mem";
416 dmas = <&sdma2 16 23 0> , <&sdma2 17 23 0>,
417 <&sdma2 18 23 0> , <&sdma2 19 23 0>,
418 <&sdma2 20 23 0> , <&sdma2 21 23 0>,
419 <&sdma2 22 23 0> , <&sdma2 23 23 0>;
420 dma-names = "ctx0_rx", "ctx0_tx",
421 "ctx1_rx", "ctx1_tx",
422 "ctx2_rx", "ctx2_tx",
423 "ctx3_rx", "ctx3_tx";
424 firmware-name = "imx/easrc/easrc-imx8mn.bin";
33597c62 425 fsl,asrc-rate = <8000>;
970406ea
AF		 426 fsl,asrc-format = <2>;
427 status = "disabled";
428 };
429 };
430
6c3debcb
AH		 431 gpio1: gpio@30200000 {
432 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
433 reg = <0x30200000 0x10000>;
434 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
435 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
436 clocks = <&clk IMX8MN_CLK_GPIO1_ROOT>;
437 gpio-controller;
438 #gpio-cells = <2>;
439 interrupt-controller;
440 #interrupt-cells = <2>;
ee8696be 441 gpio-ranges = <&iomuxc 0 10 30>;
6c3debcb
AH		 442 };
443
444 gpio2: gpio@30210000 {
445 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
446 reg = <0x30210000 0x10000>;
447 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
448 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
449 clocks = <&clk IMX8MN_CLK_GPIO2_ROOT>;
450 gpio-controller;
451 #gpio-cells = <2>;
452 interrupt-controller;
453 #interrupt-cells = <2>;
ee8696be 454 gpio-ranges = <&iomuxc 0 40 21>;
6c3debcb
AH		 455 };
456
457 gpio3: gpio@30220000 {
458 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
459 reg = <0x30220000 0x10000>;
460 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
461 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
462 clocks = <&clk IMX8MN_CLK_GPIO3_ROOT>;
463 gpio-controller;
464 #gpio-cells = <2>;
465 interrupt-controller;
466 #interrupt-cells = <2>;
ee8696be 467 gpio-ranges = <&iomuxc 0 61 26>;
6c3debcb
AH		 468 };
469
470 gpio4: gpio@30230000 {
471 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
472 reg = <0x30230000 0x10000>;
473 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
474 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
475 clocks = <&clk IMX8MN_CLK_GPIO4_ROOT>;
476 gpio-controller;
477 #gpio-cells = <2>;
478 interrupt-controller;
479 #interrupt-cells = <2>;
ee8696be 480 gpio-ranges = <&iomuxc 21 108 11>;
6c3debcb
AH		 481 };
482
483 gpio5: gpio@30240000 {
484 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
485 reg = <0x30240000 0x10000>;
486 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
487 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
488 clocks = <&clk IMX8MN_CLK_GPIO5_ROOT>;
489 gpio-controller;
490 #gpio-cells = <2>;
491 interrupt-controller;
492 #interrupt-cells = <2>;
ee8696be 493 gpio-ranges = <&iomuxc 0 119 30>;
6c3debcb
AH		 494 };
495
819779a9
AH		 496 tmu: tmu@30260000 {
497 compatible = "fsl,imx8mn-tmu", "fsl,imx8mm-tmu";
498 reg = <0x30260000 0x10000>;
499 clocks = <&clk IMX8MN_CLK_TMU_ROOT>;
500 #thermal-sensor-cells = <0>;
501 };
502
6c3debcb
AH		 503 wdog1: watchdog@30280000 {
504 compatible = "fsl,imx8mn-wdt", "fsl,imx21-wdt";
505 reg = <0x30280000 0x10000>;
506 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
507 clocks = <&clk IMX8MN_CLK_WDOG1_ROOT>;
508 status = "disabled";
509 };
510
511 wdog2: watchdog@30290000 {
512 compatible = "fsl,imx8mn-wdt", "fsl,imx21-wdt";
513 reg = <0x30290000 0x10000>;
514 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
515 clocks = <&clk IMX8MN_CLK_WDOG2_ROOT>;
516 status = "disabled";
517 };
518
519 wdog3: watchdog@302a0000 {
520 compatible = "fsl,imx8mn-wdt", "fsl,imx21-wdt";
521 reg = <0x302a0000 0x10000>;
522 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
523 clocks = <&clk IMX8MN_CLK_WDOG3_ROOT>;
524 status = "disabled";
525 };
526
527 sdma3: dma-controller@302b0000 {
958c6014 528 compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma";
6c3debcb
AH		 529 reg = <0x302b0000 0x10000>;
530 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
531 clocks = <&clk IMX8MN_CLK_SDMA3_ROOT>,
532 <&clk IMX8MN_CLK_SDMA3_ROOT>;
533 clock-names = "ipg", "ahb";
534 #dma-cells = <3>;
535 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
536 };
537
538 sdma2: dma-controller@302c0000 {
958c6014 539 compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma";
6c3debcb
AH		 540 reg = <0x302c0000 0x10000>;
541 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
542 clocks = <&clk IMX8MN_CLK_SDMA2_ROOT>,
543 <&clk IMX8MN_CLK_SDMA2_ROOT>;
544 clock-names = "ipg", "ahb";
545 #dma-cells = <3>;
546 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
547 };
548
549 iomuxc: pinctrl@30330000 {
550 compatible = "fsl,imx8mn-iomuxc";
551 reg = <0x30330000 0x10000>;
552 };
553
554 gpr: iomuxc-gpr@30340000 {
555 compatible = "fsl,imx8mn-iomuxc-gpr", "syscon";
556 reg = <0x30340000 0x10000>;
557 };
558
12fa1078 559 ocotp: efuse@30350000 {
2bad8c48 560 compatible = "fsl,imx8mn-ocotp", "fsl,imx8mm-ocotp", "syscon";
6c3debcb
AH		 561 reg = <0x30350000 0x10000>;
562 clocks = <&clk IMX8MN_CLK_OCOTP_ROOT>;
01c49314
AH		 563 #address-cells = <1>;
564 #size-cells = <1>;
565
cbff2379
AG		 566 imx8mn_uid: unique-id@410 {
567 reg = <0x4 0x8>;
568 };
569
01c49314
AH		 570 cpu_speed_grade: speed-grade@10 {
571 reg = <0x10 4>;
572 };
066438ae
JZ		 573
574 fec_mac_address: mac-address@90 {
575 reg = <0x90 6>;
576 };
6c3debcb
AH		 577 };
578
f98c2dfe
PF		 579 anatop: clock-controller@30360000 {
580 compatible = "fsl,imx8mn-anatop", "fsl,imx8mm-anatop";
6c3debcb 581 reg = <0x30360000 0x10000>;
f98c2dfe 582 #clock-cells = <1>;
6c3debcb
AH		 583 };
584
585 snvs: snvs@30370000 {
586 compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd";
587 reg = <0x30370000 0x10000>;
588
589 snvs_rtc: snvs-rtc-lp {
590 compatible = "fsl,sec-v4.0-mon-rtc-lp";
591 regmap = <&snvs>;
592 offset = <0x34>;
593 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
594 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
42ef961b 595 clocks = <&clk IMX8MN_CLK_SNVS_ROOT>;
6c3debcb
AH		 596 clock-names = "snvs-rtc";
597 };
598
599 snvs_pwrkey: snvs-powerkey {
600 compatible = "fsl,sec-v4.0-pwrkey";
601 regmap = <&snvs>;
602 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
c2a2f446
AH		 603 clocks = <&clk IMX8MN_CLK_SNVS_ROOT>;
604 clock-names = "snvs-pwrkey";
6c3debcb
AH		 605 linux,keycode = <KEY_POWER>;
606 wakeup-source;
607 status = "disabled";
608 };
609 };
610
611 clk: clock-controller@30380000 {
612 compatible = "fsl,imx8mn-ccm";
613 reg = <0x30380000 0x10000>;
614 #clock-cells = <1>;
615 clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>,
616 <&clk_ext3>, <&clk_ext4>;
617 clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
618 "clk_ext3", "clk_ext4";
9e6337e6
PF		 619 assigned-clocks = <&clk IMX8MN_CLK_A53_SRC>,
620 <&clk IMX8MN_CLK_A53_CORE>,
621 <&clk IMX8MN_CLK_NOC>,
53458f86
PF		 622 <&clk IMX8MN_CLK_AUDIO_AHB>,
623 <&clk IMX8MN_CLK_IPG_AUDIO_ROOT>,
26442c79
SW		 624 <&clk IMX8MN_SYS_PLL3>,
625 <&clk IMX8MN_AUDIO_PLL1>,
626 <&clk IMX8MN_AUDIO_PLL2>;
9e6337e6
PF		 627 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_800M>,
628 <&clk IMX8MN_ARM_PLL_OUT>,
629 <&clk IMX8MN_SYS_PLL3_OUT>,
53458f86 630 <&clk IMX8MN_SYS_PLL1_800M>;
9e6337e6 631 assigned-clock-rates = <0>, <0>, <0>,
53458f86
PF		 632 <400000000>,
633 <400000000>,
26442c79
SW		 634 <600000000>,
635 <393216000>,
636 <361267200>;
6c3debcb
AH		 637 };
638
639 src: reset-controller@30390000 {
23b80c20 640 compatible = "fsl,imx8mn-src", "fsl,imx8mq-src", "syscon";
6c3debcb
AH		 641 reg = <0x30390000 0x10000>;
642 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
643 #reset-cells = <1>;
644 };
8b8ebec6
AF		 645
646 gpc: gpc@303a0000 {
647 compatible = "fsl,imx8mn-gpc";
648 reg = <0x303a0000 0x10000>;
649 interrupt-parent = <&gic>;
650 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
651
652 pgc {
653 #address-cells = <1>;
654 #size-cells = <0>;
655
656 pgc_hsiomix: power-domain@0 {
657 #power-domain-cells = <0>;
658 reg = <IMX8MN_POWER_DOMAIN_HSIOMIX>;
659 clocks = <&clk IMX8MN_CLK_USB_BUS>;
660 };
661
662 pgc_otg1: power-domain@1 {
663 #power-domain-cells = <0>;
664 reg = <IMX8MN_POWER_DOMAIN_OTG1>;
665 power-domains = <&pgc_hsiomix>;
666 };
667
668 pgc_gpumix: power-domain@2 {
669 #power-domain-cells = <0>;
670 reg = <IMX8MN_POWER_DOMAIN_GPUMIX>;
671 clocks = <&clk IMX8MN_CLK_GPU_CORE_ROOT>,
672 <&clk IMX8MN_CLK_GPU_SHADER>,
673 <&clk IMX8MN_CLK_GPU_BUS_ROOT>,
674 <&clk IMX8MN_CLK_GPU_AHB>;
8b8ebec6
AF		 675 };
676
677 pgc_dispmix: power-domain@3 {
678 #power-domain-cells = <0>;
679 reg = <IMX8MN_POWER_DOMAIN_DISPMIX>;
680 clocks = <&clk IMX8MN_CLK_DISP_AXI_ROOT>,
681 <&clk IMX8MN_CLK_DISP_APB_ROOT>;
682 };
683
684 pgc_mipi: power-domain@4 {
685 #power-domain-cells = <0>;
686 reg = <IMX8MN_POWER_DOMAIN_MIPI>;
687 power-domains = <&pgc_dispmix>;
688 };
689 };
690 };
6c3debcb
AH		 691 };
692
693 aips2: bus@30400000 {
dc3efc6f 694 compatible = "fsl,aips-bus", "simple-bus";
921a6845 695 reg = <0x30400000 0x400000>;
6c3debcb
AH		 696 #address-cells = <1>;
697 #size-cells = <1>;
698 ranges;
699
700 pwm1: pwm@30660000 {
701 compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm";
702 reg = <0x30660000 0x10000>;
703 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
704 clocks = <&clk IMX8MN_CLK_PWM1_ROOT>,
705 <&clk IMX8MN_CLK_PWM1_ROOT>;
706 clock-names = "ipg", "per";
6bc1e580 707 #pwm-cells = <3>;
6c3debcb
AH		 708 status = "disabled";
709 };
710
711 pwm2: pwm@30670000 {
712 compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm";
713 reg = <0x30670000 0x10000>;
714 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
715 clocks = <&clk IMX8MN_CLK_PWM2_ROOT>,
716 <&clk IMX8MN_CLK_PWM2_ROOT>;
717 clock-names = "ipg", "per";
6bc1e580 718 #pwm-cells = <3>;
6c3debcb
AH		 719 status = "disabled";
720 };
721
722 pwm3: pwm@30680000 {
723 compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm";
724 reg = <0x30680000 0x10000>;
725 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
726 clocks = <&clk IMX8MN_CLK_PWM3_ROOT>,
727 <&clk IMX8MN_CLK_PWM3_ROOT>;
728 clock-names = "ipg", "per";
6bc1e580 729 #pwm-cells = <3>;
6c3debcb
AH		 730 status = "disabled";
731 };
732
733 pwm4: pwm@30690000 {
734 compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm";
735 reg = <0x30690000 0x10000>;
736 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
737 clocks = <&clk IMX8MN_CLK_PWM4_ROOT>,
738 <&clk IMX8MN_CLK_PWM4_ROOT>;
739 clock-names = "ipg", "per";
6bc1e580 740 #pwm-cells = <3>;
6c3debcb
AH		 741 status = "disabled";
742 };
c4a21269
AH		 743
744 system_counter: timer@306a0000 {
745 compatible = "nxp,sysctr-timer";
746 reg = <0x306a0000 0x20000>;
747 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
748 clocks = <&osc_24m>;
749 clock-names = "per";
750 };
6c3debcb
AH		 751 };
752
753 aips3: bus@30800000 {
dc3efc6f 754 compatible = "fsl,aips-bus", "simple-bus";
921a6845 755 reg = <0x30800000 0x400000>;
6c3debcb
AH		 756 #address-cells = <1>;
757 #size-cells = <1>;
758 ranges;
759
292e0f48
AF		 760 spba1: spba-bus@30800000 {
761 compatible = "fsl,spba-bus", "simple-bus";
6c3debcb 762 #address-cells = <1>;
292e0f48
AF		 763 #size-cells = <1>;
764 reg = <0x30800000 0x100000>;
765 ranges;
6c3debcb 766
292e0f48
AF		 767 ecspi1: spi@30820000 {
768 compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi";
769 #address-cells = <1>;
770 #size-cells = <0>;
771 reg = <0x30820000 0x10000>;
772 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
773 clocks = <&clk IMX8MN_CLK_ECSPI1_ROOT>,
774 <&clk IMX8MN_CLK_ECSPI1_ROOT>;
775 clock-names = "ipg", "per";
776 dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
777 dma-names = "rx", "tx";
778 status = "disabled";
779 };
6c3debcb 780
292e0f48
AF		 781 ecspi2: spi@30830000 {
782 compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi";
783 #address-cells = <1>;
784 #size-cells = <0>;
785 reg = <0x30830000 0x10000>;
786 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
787 clocks = <&clk IMX8MN_CLK_ECSPI2_ROOT>,
788 <&clk IMX8MN_CLK_ECSPI2_ROOT>;
789 clock-names = "ipg", "per";
790 dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;
791 dma-names = "rx", "tx";
792 status = "disabled";
793 };
6c3debcb 794
292e0f48
AF		 795 ecspi3: spi@30840000 {
796 compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi";
797 #address-cells = <1>;
798 #size-cells = <0>;
799 reg = <0x30840000 0x10000>;
800 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
801 clocks = <&clk IMX8MN_CLK_ECSPI3_ROOT>,
802 <&clk IMX8MN_CLK_ECSPI3_ROOT>;
803 clock-names = "ipg", "per";
804 dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;
805 dma-names = "rx", "tx";
806 status = "disabled";
807 };
6c3debcb 808
292e0f48
AF		 809 uart1: serial@30860000 {
810 compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
811 reg = <0x30860000 0x10000>;
812 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
813 clocks = <&clk IMX8MN_CLK_UART1_ROOT>,
814 <&clk IMX8MN_CLK_UART1_ROOT>;
815 clock-names = "ipg", "per";
816 dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;
817 dma-names = "rx", "tx";
818 status = "disabled";
819 };
6c3debcb 820
292e0f48
AF		 821 uart3: serial@30880000 {
822 compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
823 reg = <0x30880000 0x10000>;
824 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
825 clocks = <&clk IMX8MN_CLK_UART3_ROOT>,
826 <&clk IMX8MN_CLK_UART3_ROOT>;
827 clock-names = "ipg", "per";
828 dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;
829 dma-names = "rx", "tx";
830 status = "disabled";
831 };
832
833 uart2: serial@30890000 {
834 compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
835 reg = <0x30890000 0x10000>;
836 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
837 clocks = <&clk IMX8MN_CLK_UART2_ROOT>,
838 <&clk IMX8MN_CLK_UART2_ROOT>;
839 clock-names = "ipg", "per";
840 status = "disabled";
841 };
6c3debcb
AH		 842 };
843
aad24175
HG		 844 crypto: crypto@30900000 {
845 compatible = "fsl,sec-v4.0";
846 #address-cells = <1>;
847 #size-cells = <1>;
848 reg = <0x30900000 0x40000>;
849 ranges = <0 0x30900000 0x40000>;
850 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
851 clocks = <&clk IMX8MN_CLK_AHB>,
852 <&clk IMX8MN_CLK_IPG_ROOT>;
853 clock-names = "aclk", "ipg";
854
f5ff5a21 855 sec_jr0: jr@1000 {
aad24175
HG		 856 compatible = "fsl,sec-v4.0-job-ring";
857 reg = <0x1000 0x1000>;
858 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
dc9c1ceb 859 status = "disabled";
aad24175
HG		 860 };
861
f5ff5a21 862 sec_jr1: jr@2000 {
aad24175
HG		 863 compatible = "fsl,sec-v4.0-job-ring";
864 reg = <0x2000 0x1000>;
865 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
866 };
867
f5ff5a21 868 sec_jr2: jr@3000 {
aad24175
HG		 869 compatible = "fsl,sec-v4.0-job-ring";
870 reg = <0x3000 0x1000>;
871 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
872 };
873 };
874
6c3debcb
AH		 875 i2c1: i2c@30a20000 {
876 compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c";
877 #address-cells = <1>;
878 #size-cells = <0>;
879 reg = <0x30a20000 0x10000>;
880 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
881 clocks = <&clk IMX8MN_CLK_I2C1_ROOT>;
882 status = "disabled";
883 };
884
885 i2c2: i2c@30a30000 {
886 compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c";
887 #address-cells = <1>;
888 #size-cells = <0>;
889 reg = <0x30a30000 0x10000>;
890 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
891 clocks = <&clk IMX8MN_CLK_I2C2_ROOT>;
892 status = "disabled";
893 };
894
895 i2c3: i2c@30a40000 {
896 #address-cells = <1>;
897 #size-cells = <0>;
898 compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c";
899 reg = <0x30a40000 0x10000>;
900 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
901 clocks = <&clk IMX8MN_CLK_I2C3_ROOT>;
902 status = "disabled";
903 };
904
905 i2c4: i2c@30a50000 {
906 compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c";
907 #address-cells = <1>;
908 #size-cells = <0>;
909 reg = <0x30a50000 0x10000>;
910 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
911 clocks = <&clk IMX8MN_CLK_I2C4_ROOT>;
912 status = "disabled";
913 };
914
915 uart4: serial@30a60000 {
916 compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
917 reg = <0x30a60000 0x10000>;
918 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
919 clocks = <&clk IMX8MN_CLK_UART4_ROOT>,
920 <&clk IMX8MN_CLK_UART4_ROOT>;
921 clock-names = "ipg", "per";
922 dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>;
923 dma-names = "rx", "tx";
924 status = "disabled";
925 };
926
bbfc59be
PF		 927 mu: mailbox@30aa0000 {
928 compatible = "fsl,imx8mn-mu", "fsl,imx6sx-mu";
929 reg = <0x30aa0000 0x10000>;
930 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
931 clocks = <&clk IMX8MN_CLK_MU_ROOT>;
932 #mbox-cells = <2>;
933 };
934
6c3debcb 935 usdhc1: mmc@30b40000 {
472f20b4 936 compatible = "fsl,imx8mn-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
6c3debcb
AH		 937 reg = <0x30b40000 0x10000>;
938 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
ea65aba8 939 clocks = <&clk IMX8MN_CLK_IPG_ROOT>,
6c3debcb
AH		 940 <&clk IMX8MN_CLK_NAND_USDHC_BUS>,
941 <&clk IMX8MN_CLK_USDHC1_ROOT>;
942 clock-names = "ipg", "ahb", "per";
6c3debcb 943 fsl,tuning-start-tap = <20>;
33597c62 944 fsl,tuning-step = <2>;
6c3debcb
AH		 945 bus-width = <4>;
946 status = "disabled";
947 };
948
949 usdhc2: mmc@30b50000 {
472f20b4 950 compatible = "fsl,imx8mn-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
6c3debcb
AH		 951 reg = <0x30b50000 0x10000>;
952 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
ea65aba8 953 clocks = <&clk IMX8MN_CLK_IPG_ROOT>,
6c3debcb
AH		 954 <&clk IMX8MN_CLK_NAND_USDHC_BUS>,
955 <&clk IMX8MN_CLK_USDHC2_ROOT>;
956 clock-names = "ipg", "ahb", "per";
957 fsl,tuning-start-tap = <20>;
33597c62 958 fsl,tuning-step = <2>;
6c3debcb
AH		 959 bus-width = <4>;
960 status = "disabled";
961 };
962
963 usdhc3: mmc@30b60000 {
472f20b4 964 compatible = "fsl,imx8mn-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
6c3debcb
AH		 965 reg = <0x30b60000 0x10000>;
966 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
ea65aba8 967 clocks = <&clk IMX8MN_CLK_IPG_ROOT>,
6c3debcb
AH		 968 <&clk IMX8MN_CLK_NAND_USDHC_BUS>,
969 <&clk IMX8MN_CLK_USDHC3_ROOT>;
970 clock-names = "ipg", "ahb", "per";
6c3debcb 971 fsl,tuning-start-tap = <20>;
33597c62 972 fsl,tuning-step = <2>;
6c3debcb
AH		 973 bus-width = <4>;
974 status = "disabled";
975 };
976
189f6586
AF		 977 flexspi: spi@30bb0000 {
978 #address-cells = <1>;
979 #size-cells = <0>;
980 compatible = "nxp,imx8mm-fspi";
981 reg = <0x30bb0000 0x10000>, <0x8000000 0x10000000>;
982 reg-names = "fspi_base", "fspi_mmap";
983 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
984 clocks = <&clk IMX8MN_CLK_QSPI_ROOT>,
985 <&clk IMX8MN_CLK_QSPI_ROOT>;
f29fa744 986 clock-names = "fspi_en", "fspi";
189f6586
AF		 987 status = "disabled";
988 };
989
6c3debcb 990 sdma1: dma-controller@30bd0000 {
958c6014 991 compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma";
6c3debcb
AH		 992 reg = <0x30bd0000 0x10000>;
993 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
994 clocks = <&clk IMX8MN_CLK_SDMA1_ROOT>,
15ddc3e1 995 <&clk IMX8MN_CLK_AHB>;
6c3debcb
AH		 996 clock-names = "ipg", "ahb";
997 #dma-cells = <3>;
998 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
999 };
1000
1001 fec1: ethernet@30be0000 {
a758dee8 1002 compatible = "fsl,imx8mn-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec";
6c3debcb
AH		 1003 reg = <0x30be0000 0x10000>;
1004 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
1005 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
d3762a47
FE		 1006 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
1007 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
6c3debcb
AH		 1008 clocks = <&clk IMX8MN_CLK_ENET1_ROOT>,
1009 <&clk IMX8MN_CLK_ENET1_ROOT>,
1010 <&clk IMX8MN_CLK_ENET_TIMER>,
1011 <&clk IMX8MN_CLK_ENET_REF>,
1012 <&clk IMX8MN_CLK_ENET_PHY_REF>;
1013 clock-names = "ipg", "ahb", "ptp",
1014 "enet_clk_ref", "enet_out";
1015 assigned-clocks = <&clk IMX8MN_CLK_ENET_AXI>,
1016 <&clk IMX8MN_CLK_ENET_TIMER>,
1017 <&clk IMX8MN_CLK_ENET_REF>,
70eacf42 1018 <&clk IMX8MN_CLK_ENET_PHY_REF>;
6c3debcb
AH		 1019 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_266M>,
1020 <&clk IMX8MN_SYS_PLL2_100M>,
70eacf42
JZ		 1021 <&clk IMX8MN_SYS_PLL2_125M>,
1022 <&clk IMX8MN_SYS_PLL2_50M>;
1023 assigned-clock-rates = <0>, <100000000>, <125000000>, <0>;
6c3debcb
AH		 1024 fsl,num-tx-queues = <3>;
1025 fsl,num-rx-queues = <3>;
066438ae
JZ		 1026 nvmem-cells = <&fec_mac_address>;
1027 nvmem-cell-names = "mac-address";
afe99354 1028 fsl,stop-mode = <&gpr 0x10 3>;
6c3debcb
AH		 1029 status = "disabled";
1030 };
1031
1032 };
1033
1034 aips4: bus@32c00000 {
dc3efc6f 1035 compatible = "fsl,aips-bus", "simple-bus";
921a6845 1036 reg = <0x32c00000 0x400000>;
6c3debcb
AH		 1037 #address-cells = <1>;
1038 #size-cells = <1>;
1039 ranges;
1040
18d4a6c9
AF		 1041 disp_blk_ctrl: blk-ctrl@32e28000 {
1042 compatible = "fsl,imx8mn-disp-blk-ctrl", "syscon";
1043 reg = <0x32e28000 0x100>;
1044 power-domains = <&pgc_dispmix>, <&pgc_dispmix>,
1045 <&pgc_dispmix>, <&pgc_mipi>,
1046 <&pgc_mipi>;
1047 power-domain-names = "bus", "isi",
1048 "lcdif", "mipi-dsi",
1049 "mipi-csi";
1050 clocks = <&clk IMX8MN_CLK_DISP_AXI>,
1051 <&clk IMX8MN_CLK_DISP_APB>,
1052 <&clk IMX8MN_CLK_DISP_AXI_ROOT>,
1053 <&clk IMX8MN_CLK_DISP_APB_ROOT>,
1054 <&clk IMX8MN_CLK_DISP_AXI_ROOT>,
1055 <&clk IMX8MN_CLK_DISP_APB_ROOT>,
1056 <&clk IMX8MN_CLK_DISP_PIXEL_ROOT>,
1057 <&clk IMX8MN_CLK_DSI_CORE>,
1058 <&clk IMX8MN_CLK_DSI_PHY_REF>,
1059 <&clk IMX8MN_CLK_CSI1_PHY_REF>,
1060 <&clk IMX8MN_CLK_CAMERA_PIXEL_ROOT>;
1061 clock-names = "disp_axi", "disp_apb",
1062 "disp_axi_root", "disp_apb_root",
1063 "lcdif-axi", "lcdif-apb", "lcdif-pix",
1064 "dsi-pclk", "dsi-ref",
1065 "csi-aclk", "csi-pclk";
1066 #power-domain-cells = <1>;
1067 };
1068
6c3debcb
AH		 1069 usbotg1: usb@32e40000 {
1070 compatible = "fsl,imx8mn-usb", "fsl,imx7d-usb";
1071 reg = <0x32e40000 0x200>;
1072 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
1073 clocks = <&clk IMX8MN_CLK_USB1_CTRL_ROOT>;
1074 clock-names = "usb1_ctrl_root_clk";
d51cb99c
LJ		 1075 assigned-clocks = <&clk IMX8MN_CLK_USB_BUS>;
1076 assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_500M>;
78e80c4b 1077 phys = <&usbphynop1>;
6c3debcb 1078 fsl,usbmisc = <&usbmisc1 0>;
ea2b5af5 1079 power-domains = <&pgc_otg1>;
6c3debcb
AH		 1080 status = "disabled";
1081 };
1082
1083 usbmisc1: usbmisc@32e40200 {
1084 compatible = "fsl,imx8mn-usbmisc", "fsl,imx7d-usbmisc";
1085 #index-cells = <1>;
1086 reg = <0x32e40200 0x200>;
1087 };
6c3debcb
AH		 1088 };
1089
1090 dma_apbh: dma-controller@33000000 {
1091 compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh";
1092 reg = <0x33000000 0x2000>;
1093 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
1094 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
1095 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
1096 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1097 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
1098 #dma-cells = <1>;
1099 dma-channels = <4>;
1100 clocks = <&clk IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK>;
1101 };
1102
1103 gpmi: nand-controller@33002000 {
1104 compatible = "fsl,imx8mn-gpmi-nand", "fsl,imx7d-gpmi-nand";
1105 #address-cells = <1>;
1106 #size-cells = <1>;
1107 reg = <0x33002000 0x2000>, <0x33004000 0x4000>;
1108 reg-names = "gpmi-nand", "bch";
1109 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1110 interrupt-names = "bch";
1111 clocks = <&clk IMX8MN_CLK_NAND_ROOT>,
1112 <&clk IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK>;
1113 clock-names = "gpmi_io", "gpmi_bch_apb";
1114 dmas = <&dma_apbh 0>;
1115 dma-names = "rx-tx";
1116 status = "disabled";
1117 };
1118
9a0f3b15
AF		 1119 gpu: gpu@38000000 {
1120 compatible = "vivante,gc";
1121 reg = <0x38000000 0x8000>;
1122 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
1123 clocks = <&clk IMX8MN_CLK_GPU_AHB>,
1124 <&clk IMX8MN_CLK_GPU_BUS_ROOT>,
1125 <&clk IMX8MN_CLK_GPU_CORE_ROOT>,
1126 <&clk IMX8MN_CLK_GPU_SHADER>;
1127 clock-names = "reg", "bus", "core", "shader";
1128 assigned-clocks = <&clk IMX8MN_CLK_GPU_CORE>,
1129 <&clk IMX8MN_CLK_GPU_SHADER>,
1130 <&clk IMX8MN_CLK_GPU_AXI>,
1131 <&clk IMX8MN_CLK_GPU_AHB>,
1132 <&clk IMX8MN_GPU_PLL>;
1133 assigned-clock-parents = <&clk IMX8MN_GPU_PLL_OUT>,
1134 <&clk IMX8MN_GPU_PLL_OUT>,
1135 <&clk IMX8MN_SYS_PLL1_800M>,
1136 <&clk IMX8MN_SYS_PLL1_800M>;
1137 assigned-clock-rates = <400000000>,
1138 <400000000>,
1139 <800000000>,
1140 <400000000>,
1141 <1200000000>;
1142 power-domains = <&pgc_gpumix>;
1143 };
1144
6c3debcb
AH		 1145 gic: interrupt-controller@38800000 {
1146 compatible = "arm,gic-v3";
1147 reg = <0x38800000 0x10000>,
1148 <0x38880000 0xc0000>;
1149 #interrupt-cells = <3>;
1150 interrupt-controller;
1151 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
1152 };
2d8e0747 1153
0376f6ec
LC		 1154 ddrc: memory-controller@3d400000 {
1155 compatible = "fsl,imx8mn-ddrc", "fsl,imx8m-ddrc";
1156 reg = <0x3d400000 0x400000>;
1157 clock-names = "core", "pll", "alt", "apb";
1158 clocks = <&clk IMX8MN_CLK_DRAM_CORE>,
1159 <&clk IMX8MN_DRAM_PLL>,
1160 <&clk IMX8MN_CLK_DRAM_ALT>,
1161 <&clk IMX8MN_CLK_DRAM_APB>;
1162 };
1163
2d8e0747
JZ		 1164 ddr-pmu@3d800000 {
1165 compatible = "fsl,imx8mn-ddr-pmu", "fsl,imx8m-ddr-pmu";
1166 reg = <0x3d800000 0x400000>;
1167 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1168 };
6c3debcb
AH		 1169 };
1170
1171 usbphynop1: usbphynop1 {
78e80c4b 1172 #phy-cells = <0>;
6c3debcb
AH		 1173 compatible = "usb-nop-xceiv";
1174 clocks = <&clk IMX8MN_CLK_USB_PHY_REF>;
1175 assigned-clocks = <&clk IMX8MN_CLK_USB_PHY_REF>;
1176 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_100M>;
1177 clock-names = "main_clk";
1178 };
6c3debcb 1179};
Linux 6.x block layer and io_uring tree(s)