projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
arm64: dts: imx8mq: assign clock parents for FEC
[linux-2.6-block.git] / arch / arm64 / boot / dts / freescale / imx8mn.dtsi
CommitLineData
6c3debcb
AH		 1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2019 NXP
4 */
5
6#include <dt-bindings/clock/imx8mn-clock.h>
7#include <dt-bindings/gpio/gpio.h>
8#include <dt-bindings/input/input.h>
9#include <dt-bindings/interrupt-controller/arm-gic.h>
819779a9 10#include <dt-bindings/thermal/thermal.h>
6c3debcb
AH		 11
12#include "imx8mn-pinfunc.h"
13
14/ {
6c3debcb
AH		 15 interrupt-parent = <&gic>;
16 #address-cells = <2>;
17 #size-cells = <2>;
18
19 aliases {
20 ethernet0 = &fec1;
21 gpio0 = &gpio1;
22 gpio1 = &gpio2;
23 gpio2 = &gpio3;
24 gpio3 = &gpio4;
25 gpio4 = &gpio5;
26 i2c0 = &i2c1;
27 i2c1 = &i2c2;
28 i2c2 = &i2c3;
29 i2c3 = &i2c4;
30 mmc0 = &usdhc1;
31 mmc1 = &usdhc2;
32 mmc2 = &usdhc3;
33 serial0 = &uart1;
34 serial1 = &uart2;
35 serial2 = &uart3;
36 serial3 = &uart4;
37 spi0 = &ecspi1;
38 spi1 = &ecspi2;
39 spi2 = &ecspi3;
40 };
41
42 cpus {
43 #address-cells = <1>;
44 #size-cells = <0>;
45
df844a9a
AH		 46 idle-states {
47 entry-method = "psci";
48
49 cpu_pd_wait: cpu-pd-wait {
50 compatible = "arm,idle-state";
51 arm,psci-suspend-param = <0x0010033>;
52 local-timer-stop;
53 entry-latency-us = <1000>;
54 exit-latency-us = <700>;
55 min-residency-us = <2700>;
56 };
57 };
58
6c3debcb
AH		 59 A53_0: cpu@0 {
60 device_type = "cpu";
61 compatible = "arm,cortex-a53";
62 reg = <0x0>;
63 clock-latency = <61036>;
64 clocks = <&clk IMX8MN_CLK_ARM>;
65 enable-method = "psci";
66 next-level-cache = <&A53_L2>;
01c49314
AH		 67 operating-points-v2 = <&a53_opp_table>;
68 nvmem-cells = <&cpu_speed_grade>;
69 nvmem-cell-names = "speed_grade";
df844a9a 70 cpu-idle-states = <&cpu_pd_wait>;
819779a9 71 #cooling-cells = <2>;
6c3debcb
AH		 72 };
73
74 A53_1: cpu@1 {
75 device_type = "cpu";
76 compatible = "arm,cortex-a53";
77 reg = <0x1>;
78 clock-latency = <61036>;
79 clocks = <&clk IMX8MN_CLK_ARM>;
80 enable-method = "psci";
81 next-level-cache = <&A53_L2>;
01c49314 82 operating-points-v2 = <&a53_opp_table>;
df844a9a 83 cpu-idle-states = <&cpu_pd_wait>;
819779a9 84 #cooling-cells = <2>;
6c3debcb
AH		 85 };
86
87 A53_2: cpu@2 {
88 device_type = "cpu";
89 compatible = "arm,cortex-a53";
90 reg = <0x2>;
91 clock-latency = <61036>;
92 clocks = <&clk IMX8MN_CLK_ARM>;
93 enable-method = "psci";
94 next-level-cache = <&A53_L2>;
01c49314 95 operating-points-v2 = <&a53_opp_table>;
df844a9a 96 cpu-idle-states = <&cpu_pd_wait>;
819779a9 97 #cooling-cells = <2>;
6c3debcb
AH		 98 };
99
100 A53_3: cpu@3 {
101 device_type = "cpu";
102 compatible = "arm,cortex-a53";
103 reg = <0x3>;
104 clock-latency = <61036>;
105 clocks = <&clk IMX8MN_CLK_ARM>;
106 enable-method = "psci";
107 next-level-cache = <&A53_L2>;
01c49314 108 operating-points-v2 = <&a53_opp_table>;
df844a9a 109 cpu-idle-states = <&cpu_pd_wait>;
819779a9 110 #cooling-cells = <2>;
6c3debcb
AH		 111 };
112
113 A53_L2: l2-cache0 {
114 compatible = "cache";
115 };
116 };
117
01c49314
AH		 118 a53_opp_table: opp-table {
119 compatible = "operating-points-v2";
120 opp-shared;
121
122 opp-1200000000 {
123 opp-hz = /bits/ 64 <1200000000>;
8c30e7ca 124 opp-microvolt = <850000>;
01c49314
AH		 125 opp-supported-hw = <0xb00>, <0x7>;
126 clock-latency-ns = <150000>;
127 opp-suspend;
128 };
129
130 opp-1400000000 {
131 opp-hz = /bits/ 64 <1400000000>;
132 opp-microvolt = <950000>;
133 opp-supported-hw = <0x300>, <0x7>;
134 clock-latency-ns = <150000>;
135 opp-suspend;
136 };
137
138 opp-1500000000 {
139 opp-hz = /bits/ 64 <1500000000>;
140 opp-microvolt = <1000000>;
141 opp-supported-hw = <0x100>, <0x3>;
142 clock-latency-ns = <150000>;
143 opp-suspend;
144 };
145 };
146
6c3debcb
AH		 147 osc_32k: clock-osc-32k {
148 compatible = "fixed-clock";
149 #clock-cells = <0>;
150 clock-frequency = <32768>;
151 clock-output-names = "osc_32k";
152 };
153
154 osc_24m: clock-osc-24m {
155 compatible = "fixed-clock";
156 #clock-cells = <0>;
157 clock-frequency = <24000000>;
158 clock-output-names = "osc_24m";
159 };
160
161 clk_ext1: clock-ext1 {
162 compatible = "fixed-clock";
163 #clock-cells = <0>;
164 clock-frequency = <133000000>;
165 clock-output-names = "clk_ext1";
166 };
167
168 clk_ext2: clock-ext2 {
169 compatible = "fixed-clock";
170 #clock-cells = <0>;
171 clock-frequency = <133000000>;
172 clock-output-names = "clk_ext2";
173 };
174
175 clk_ext3: clock-ext3 {
176 compatible = "fixed-clock";
177 #clock-cells = <0>;
178 clock-frequency = <133000000>;
179 clock-output-names = "clk_ext3";
180 };
181
182 clk_ext4: clock-ext4 {
183 compatible = "fixed-clock";
184 #clock-cells = <0>;
185 clock-frequency= <133000000>;
186 clock-output-names = "clk_ext4";
187 };
188
c13a7d84
JB		 189 pmu {
190 compatible = "arm,cortex-a53-pmu";
191 interrupts = <GIC_PPI 7
192 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
193 interrupt-affinity = <&A53_0>, <&A53_1>, <&A53_2>, <&A53_3>;
194 };
195
6c3debcb
AH		 196 psci {
197 compatible = "arm,psci-1.0";
198 method = "smc";
199 };
200
819779a9
AH		 201 thermal-zones {
202 cpu-thermal {
203 polling-delay-passive = <250>;
204 polling-delay = <2000>;
205 thermal-sensors = <&tmu>;
206 trips {
207 cpu_alert0: trip0 {
208 temperature = <85000>;
209 hysteresis = <2000>;
210 type = "passive";
211 };
212
213 cpu_crit0: trip1 {
214 temperature = <95000>;
215 hysteresis = <2000>;
216 type = "critical";
217 };
218 };
219
220 cooling-maps {
221 map0 {
222 trip = <&cpu_alert0>;
223 cooling-device =
224 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
225 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
226 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
227 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
228 };
229 };
230 };
231 };
232
6c3debcb
AH		 233 timer {
234 compatible = "arm,armv8-timer";
0656e37a
KK		 235 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
236 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
237 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
238 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
6c3debcb
AH		 239 clock-frequency = <8000000>;
240 arm,no-tick-in-suspend;
241 };
242
243 soc@0 {
ce58459d 244 compatible = "fsl,imx8mn-soc", "simple-bus";
6c3debcb
AH		 245 #address-cells = <1>;
246 #size-cells = <1>;
247 ranges = <0x0 0x0 0x0 0x3e000000>;
cbff2379
AG		 248 nvmem-cells = <&imx8mn_uid>;
249 nvmem-cell-names = "soc_unique_id";
6c3debcb
AH		 250
251 aips1: bus@30000000 {
dc3efc6f 252 compatible = "fsl,aips-bus", "simple-bus";
921a6845 253 reg = <0x30000000 0x400000>;
6c3debcb
AH		 254 #address-cells = <1>;
255 #size-cells = <1>;
256 ranges;
257
970406ea
AF		 258 spba: bus@30000000 {
259 compatible = "fsl,spba-bus", "simple-bus";
260 #address-cells = <1>;
261 #size-cells = <1>;
262 reg = <0x30000000 0x100000>;
263 ranges;
264
9e986006
AF		 265 sai2: sai@30020000 {
266 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
267 reg = <0x30020000 0x10000>;
268 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
269 clocks = <&clk IMX8MN_CLK_SAI2_IPG>,
270 <&clk IMX8MN_CLK_DUMMY>,
271 <&clk IMX8MN_CLK_SAI2_ROOT>,
272 <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>;
273 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
274 dmas = <&sdma2 2 2 0>, <&sdma2 3 2 0>;
275 dma-names = "rx", "tx";
276 status = "disabled";
277 };
278
279 sai3: sai@30030000 {
280 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
281 reg = <0x30030000 0x10000>;
282 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
283 clocks = <&clk IMX8MN_CLK_SAI3_IPG>,
284 <&clk IMX8MN_CLK_DUMMY>,
285 <&clk IMX8MN_CLK_SAI3_ROOT>,
286 <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>;
287 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
288 dmas = <&sdma2 4 2 0>, <&sdma2 5 2 0>;
289 dma-names = "rx", "tx";
290 status = "disabled";
291 };
292
293 sai5: sai@30050000 {
294 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
295 reg = <0x30050000 0x10000>;
296 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
297 clocks = <&clk IMX8MN_CLK_SAI5_IPG>,
298 <&clk IMX8MN_CLK_DUMMY>,
299 <&clk IMX8MN_CLK_SAI5_ROOT>,
300 <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>;
301 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
302 dmas = <&sdma2 8 2 0>, <&sdma2 9 2 0>;
303 dma-names = "rx", "tx";
304 fsl,shared-interrupt;
305 fsl,dataline = <0 0xf 0xf>;
306 status = "disabled";
307 };
308
309 sai6: sai@30060000 {
310 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
311 reg = <0x30060000 0x10000>;
312 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
313 clocks = <&clk IMX8MN_CLK_SAI6_IPG>,
314 <&clk IMX8MN_CLK_DUMMY>,
315 <&clk IMX8MN_CLK_SAI6_ROOT>,
316 <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>;
317 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
318 dmas = <&sdma2 10 2 0>, <&sdma2 11 2 0>;
319 dma-names = "rx", "tx";
320 status = "disabled";
321 };
322
cca69ef6
AF		 323 micfil: audio-controller@30080000 {
324 compatible = "fsl,imx8mm-micfil";
325 reg = <0x30080000 0x10000>;
326 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
327 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
328 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
329 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
330 clocks = <&clk IMX8MN_CLK_PDM_IPG>,
331 <&clk IMX8MN_CLK_PDM_ROOT>,
332 <&clk IMX8MN_AUDIO_PLL1_OUT>,
333 <&clk IMX8MN_AUDIO_PLL2_OUT>,
334 <&clk IMX8MN_CLK_EXT3>;
335 clock-names = "ipg_clk", "ipg_clk_app",
336 "pll8k", "pll11k", "clkext3";
337 dmas = <&sdma2 24 25 0x80000000>;
338 dma-names = "rx";
339 status = "disabled";
340 };
341
b9cf7d3b
AF		 342 spdif1: spdif@30090000 {
343 compatible = "fsl,imx35-spdif";
344 reg = <0x30090000 0x10000>;
345 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
346 clocks = <&clk IMX8MN_CLK_AUDIO_AHB>, /* core */
347 <&clk IMX8MN_CLK_24M>, /* rxtx0 */
348 <&clk IMX8MN_CLK_SPDIF1>, /* rxtx1 */
349 <&clk IMX8MN_CLK_DUMMY>, /* rxtx2 */
350 <&clk IMX8MN_CLK_DUMMY>, /* rxtx3 */
351 <&clk IMX8MN_CLK_DUMMY>, /* rxtx4 */
352 <&clk IMX8MN_CLK_AUDIO_AHB>, /* rxtx5 */
353 <&clk IMX8MN_CLK_DUMMY>, /* rxtx6 */
354 <&clk IMX8MN_CLK_DUMMY>, /* rxtx7 */
355 <&clk IMX8MN_CLK_DUMMY>; /* spba */
356 clock-names = "core", "rxtx0",
357 "rxtx1", "rxtx2",
358 "rxtx3", "rxtx4",
359 "rxtx5", "rxtx6",
360 "rxtx7", "spba";
361 dmas = <&sdma2 28 18 0>, <&sdma2 29 18 0>;
362 dma-names = "rx", "tx";
363 status = "disabled";
364 };
365
9e986006
AF		 366 sai7: sai@300b0000 {
367 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
368 reg = <0x300b0000 0x10000>;
369 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
370 clocks = <&clk IMX8MN_CLK_SAI7_IPG>,
371 <&clk IMX8MN_CLK_DUMMY>,
372 <&clk IMX8MN_CLK_SAI7_ROOT>,
373 <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>;
374 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
375 dmas = <&sdma2 12 2 0>, <&sdma2 13 2 0>;
376 dma-names = "rx", "tx";
377 status = "disabled";
378 };
379
970406ea
AF		 380 easrc: easrc@300c0000 {
381 compatible = "fsl,imx8mn-easrc";
382 reg = <0x300c0000 0x10000>;
383 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
384 clocks = <&clk IMX8MN_CLK_ASRC_ROOT>;
385 clock-names = "mem";
386 dmas = <&sdma2 16 23 0> , <&sdma2 17 23 0>,
387 <&sdma2 18 23 0> , <&sdma2 19 23 0>,
388 <&sdma2 20 23 0> , <&sdma2 21 23 0>,
389 <&sdma2 22 23 0> , <&sdma2 23 23 0>;
390 dma-names = "ctx0_rx", "ctx0_tx",
391 "ctx1_rx", "ctx1_tx",
392 "ctx2_rx", "ctx2_tx",
393 "ctx3_rx", "ctx3_tx";
394 firmware-name = "imx/easrc/easrc-imx8mn.bin";
395 fsl,asrc-rate = <8000>;
396 fsl,asrc-format = <2>;
397 status = "disabled";
398 };
399 };
400
6c3debcb
AH		 401 gpio1: gpio@30200000 {
402 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
403 reg = <0x30200000 0x10000>;
404 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
405 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
406 clocks = <&clk IMX8MN_CLK_GPIO1_ROOT>;
407 gpio-controller;
408 #gpio-cells = <2>;
409 interrupt-controller;
410 #interrupt-cells = <2>;
ee8696be 411 gpio-ranges = <&iomuxc 0 10 30>;
6c3debcb
AH		 412 };
413
414 gpio2: gpio@30210000 {
415 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
416 reg = <0x30210000 0x10000>;
417 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
418 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
419 clocks = <&clk IMX8MN_CLK_GPIO2_ROOT>;
420 gpio-controller;
421 #gpio-cells = <2>;
422 interrupt-controller;
423 #interrupt-cells = <2>;
ee8696be 424 gpio-ranges = <&iomuxc 0 40 21>;
6c3debcb
AH		 425 };
426
427 gpio3: gpio@30220000 {
428 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
429 reg = <0x30220000 0x10000>;
430 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
431 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
432 clocks = <&clk IMX8MN_CLK_GPIO3_ROOT>;
433 gpio-controller;
434 #gpio-cells = <2>;
435 interrupt-controller;
436 #interrupt-cells = <2>;
ee8696be 437 gpio-ranges = <&iomuxc 0 61 26>;
6c3debcb
AH		 438 };
439
440 gpio4: gpio@30230000 {
441 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
442 reg = <0x30230000 0x10000>;
443 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
444 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
445 clocks = <&clk IMX8MN_CLK_GPIO4_ROOT>;
446 gpio-controller;
447 #gpio-cells = <2>;
448 interrupt-controller;
449 #interrupt-cells = <2>;
ee8696be 450 gpio-ranges = <&iomuxc 21 108 11>;
6c3debcb
AH		 451 };
452
453 gpio5: gpio@30240000 {
454 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
455 reg = <0x30240000 0x10000>;
456 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
457 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
458 clocks = <&clk IMX8MN_CLK_GPIO5_ROOT>;
459 gpio-controller;
460 #gpio-cells = <2>;
461 interrupt-controller;
462 #interrupt-cells = <2>;
ee8696be 463 gpio-ranges = <&iomuxc 0 119 30>;
6c3debcb
AH		 464 };
465
819779a9
AH		 466 tmu: tmu@30260000 {
467 compatible = "fsl,imx8mn-tmu", "fsl,imx8mm-tmu";
468 reg = <0x30260000 0x10000>;
469 clocks = <&clk IMX8MN_CLK_TMU_ROOT>;
470 #thermal-sensor-cells = <0>;
471 };
472
6c3debcb
AH		 473 wdog1: watchdog@30280000 {
474 compatible = "fsl,imx8mn-wdt", "fsl,imx21-wdt";
475 reg = <0x30280000 0x10000>;
476 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
477 clocks = <&clk IMX8MN_CLK_WDOG1_ROOT>;
478 status = "disabled";
479 };
480
481 wdog2: watchdog@30290000 {
482 compatible = "fsl,imx8mn-wdt", "fsl,imx21-wdt";
483 reg = <0x30290000 0x10000>;
484 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
485 clocks = <&clk IMX8MN_CLK_WDOG2_ROOT>;
486 status = "disabled";
487 };
488
489 wdog3: watchdog@302a0000 {
490 compatible = "fsl,imx8mn-wdt", "fsl,imx21-wdt";
491 reg = <0x302a0000 0x10000>;
492 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
493 clocks = <&clk IMX8MN_CLK_WDOG3_ROOT>;
494 status = "disabled";
495 };
496
497 sdma3: dma-controller@302b0000 {
958c6014 498 compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma";
6c3debcb
AH		 499 reg = <0x302b0000 0x10000>;
500 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
501 clocks = <&clk IMX8MN_CLK_SDMA3_ROOT>,
502 <&clk IMX8MN_CLK_SDMA3_ROOT>;
503 clock-names = "ipg", "ahb";
504 #dma-cells = <3>;
505 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
506 };
507
508 sdma2: dma-controller@302c0000 {
958c6014 509 compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma";
6c3debcb
AH		 510 reg = <0x302c0000 0x10000>;
511 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
512 clocks = <&clk IMX8MN_CLK_SDMA2_ROOT>,
513 <&clk IMX8MN_CLK_SDMA2_ROOT>;
514 clock-names = "ipg", "ahb";
515 #dma-cells = <3>;
516 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
517 };
518
519 iomuxc: pinctrl@30330000 {
520 compatible = "fsl,imx8mn-iomuxc";
521 reg = <0x30330000 0x10000>;
522 };
523
524 gpr: iomuxc-gpr@30340000 {
525 compatible = "fsl,imx8mn-iomuxc-gpr", "syscon";
526 reg = <0x30340000 0x10000>;
527 };
528
12fa1078 529 ocotp: efuse@30350000 {
2bad8c48 530 compatible = "fsl,imx8mn-ocotp", "fsl,imx8mm-ocotp", "syscon";
6c3debcb
AH		 531 reg = <0x30350000 0x10000>;
532 clocks = <&clk IMX8MN_CLK_OCOTP_ROOT>;
01c49314
AH		 533 #address-cells = <1>;
534 #size-cells = <1>;
535
cbff2379
AG		 536 imx8mn_uid: unique-id@410 {
537 reg = <0x4 0x8>;
538 };
539
01c49314
AH		 540 cpu_speed_grade: speed-grade@10 {
541 reg = <0x10 4>;
542 };
6c3debcb
AH		 543 };
544
545 anatop: anatop@30360000 {
546 compatible = "fsl,imx8mn-anatop", "fsl,imx8mm-anatop",
0f93eb28 547 "syscon";
6c3debcb
AH		 548 reg = <0x30360000 0x10000>;
549 };
550
551 snvs: snvs@30370000 {
552 compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd";
553 reg = <0x30370000 0x10000>;
554
555 snvs_rtc: snvs-rtc-lp {
556 compatible = "fsl,sec-v4.0-mon-rtc-lp";
557 regmap = <&snvs>;
558 offset = <0x34>;
559 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
560 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
42ef961b 561 clocks = <&clk IMX8MN_CLK_SNVS_ROOT>;
6c3debcb
AH		 562 clock-names = "snvs-rtc";
563 };
564
565 snvs_pwrkey: snvs-powerkey {
566 compatible = "fsl,sec-v4.0-pwrkey";
567 regmap = <&snvs>;
568 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
c2a2f446
AH		 569 clocks = <&clk IMX8MN_CLK_SNVS_ROOT>;
570 clock-names = "snvs-pwrkey";
6c3debcb
AH		 571 linux,keycode = <KEY_POWER>;
572 wakeup-source;
573 status = "disabled";
574 };
575 };
576
577 clk: clock-controller@30380000 {
578 compatible = "fsl,imx8mn-ccm";
579 reg = <0x30380000 0x10000>;
580 #clock-cells = <1>;
581 clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>,
582 <&clk_ext3>, <&clk_ext4>;
583 clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
584 "clk_ext3", "clk_ext4";
9e6337e6
PF		 585 assigned-clocks = <&clk IMX8MN_CLK_A53_SRC>,
586 <&clk IMX8MN_CLK_A53_CORE>,
587 <&clk IMX8MN_CLK_NOC>,
53458f86
PF		 588 <&clk IMX8MN_CLK_AUDIO_AHB>,
589 <&clk IMX8MN_CLK_IPG_AUDIO_ROOT>,
26442c79
SW		 590 <&clk IMX8MN_SYS_PLL3>,
591 <&clk IMX8MN_AUDIO_PLL1>,
592 <&clk IMX8MN_AUDIO_PLL2>;
9e6337e6
PF		 593 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_800M>,
594 <&clk IMX8MN_ARM_PLL_OUT>,
595 <&clk IMX8MN_SYS_PLL3_OUT>,
53458f86 596 <&clk IMX8MN_SYS_PLL1_800M>;
9e6337e6 597 assigned-clock-rates = <0>, <0>, <0>,
53458f86
PF		 598 <400000000>,
599 <400000000>,
26442c79
SW		 600 <600000000>,
601 <393216000>,
602 <361267200>;
6c3debcb
AH		 603 };
604
605 src: reset-controller@30390000 {
23b80c20 606 compatible = "fsl,imx8mn-src", "fsl,imx8mq-src", "syscon";
6c3debcb
AH		 607 reg = <0x30390000 0x10000>;
608 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
609 #reset-cells = <1>;
610 };
611 };
612
613 aips2: bus@30400000 {
dc3efc6f 614 compatible = "fsl,aips-bus", "simple-bus";
921a6845 615 reg = <0x30400000 0x400000>;
6c3debcb
AH		 616 #address-cells = <1>;
617 #size-cells = <1>;
618 ranges;
619
620 pwm1: pwm@30660000 {
621 compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm";
622 reg = <0x30660000 0x10000>;
623 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
624 clocks = <&clk IMX8MN_CLK_PWM1_ROOT>,
625 <&clk IMX8MN_CLK_PWM1_ROOT>;
626 clock-names = "ipg", "per";
627 #pwm-cells = <2>;
628 status = "disabled";
629 };
630
631 pwm2: pwm@30670000 {
632 compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm";
633 reg = <0x30670000 0x10000>;
634 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
635 clocks = <&clk IMX8MN_CLK_PWM2_ROOT>,
636 <&clk IMX8MN_CLK_PWM2_ROOT>;
637 clock-names = "ipg", "per";
638 #pwm-cells = <2>;
639 status = "disabled";
640 };
641
642 pwm3: pwm@30680000 {
643 compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm";
644 reg = <0x30680000 0x10000>;
645 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
646 clocks = <&clk IMX8MN_CLK_PWM3_ROOT>,
647 <&clk IMX8MN_CLK_PWM3_ROOT>;
648 clock-names = "ipg", "per";
649 #pwm-cells = <2>;
650 status = "disabled";
651 };
652
653 pwm4: pwm@30690000 {
654 compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm";
655 reg = <0x30690000 0x10000>;
656 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
657 clocks = <&clk IMX8MN_CLK_PWM4_ROOT>,
658 <&clk IMX8MN_CLK_PWM4_ROOT>;
659 clock-names = "ipg", "per";
660 #pwm-cells = <2>;
661 status = "disabled";
662 };
c4a21269
AH		 663
664 system_counter: timer@306a0000 {
665 compatible = "nxp,sysctr-timer";
666 reg = <0x306a0000 0x20000>;
667 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
668 clocks = <&osc_24m>;
669 clock-names = "per";
670 };
6c3debcb
AH		 671 };
672
673 aips3: bus@30800000 {
dc3efc6f 674 compatible = "fsl,aips-bus", "simple-bus";
921a6845 675 reg = <0x30800000 0x400000>;
6c3debcb
AH		 676 #address-cells = <1>;
677 #size-cells = <1>;
678 ranges;
679
680 ecspi1: spi@30820000 {
681 compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi";
682 #address-cells = <1>;
683 #size-cells = <0>;
684 reg = <0x30820000 0x10000>;
685 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
686 clocks = <&clk IMX8MN_CLK_ECSPI1_ROOT>,
687 <&clk IMX8MN_CLK_ECSPI1_ROOT>;
688 clock-names = "ipg", "per";
689 dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
690 dma-names = "rx", "tx";
691 status = "disabled";
692 };
693
694 ecspi2: spi@30830000 {
695 compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi";
696 #address-cells = <1>;
697 #size-cells = <0>;
698 reg = <0x30830000 0x10000>;
699 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
700 clocks = <&clk IMX8MN_CLK_ECSPI2_ROOT>,
701 <&clk IMX8MN_CLK_ECSPI2_ROOT>;
702 clock-names = "ipg", "per";
703 dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;
704 dma-names = "rx", "tx";
705 status = "disabled";
706 };
707
708 ecspi3: spi@30840000 {
709 compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi";
710 #address-cells = <1>;
711 #size-cells = <0>;
712 reg = <0x30840000 0x10000>;
713 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
714 clocks = <&clk IMX8MN_CLK_ECSPI3_ROOT>,
715 <&clk IMX8MN_CLK_ECSPI3_ROOT>;
716 clock-names = "ipg", "per";
717 dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;
718 dma-names = "rx", "tx";
719 status = "disabled";
720 };
721
722 uart1: serial@30860000 {
723 compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
724 reg = <0x30860000 0x10000>;
725 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
726 clocks = <&clk IMX8MN_CLK_UART1_ROOT>,
727 <&clk IMX8MN_CLK_UART1_ROOT>;
728 clock-names = "ipg", "per";
729 dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;
730 dma-names = "rx", "tx";
731 status = "disabled";
732 };
733
734 uart3: serial@30880000 {
735 compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
736 reg = <0x30880000 0x10000>;
737 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
738 clocks = <&clk IMX8MN_CLK_UART3_ROOT>,
739 <&clk IMX8MN_CLK_UART3_ROOT>;
740 clock-names = "ipg", "per";
741 dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;
742 dma-names = "rx", "tx";
743 status = "disabled";
744 };
745
746 uart2: serial@30890000 {
747 compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
748 reg = <0x30890000 0x10000>;
749 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
750 clocks = <&clk IMX8MN_CLK_UART2_ROOT>,
751 <&clk IMX8MN_CLK_UART2_ROOT>;
752 clock-names = "ipg", "per";
753 status = "disabled";
754 };
755
aad24175
HG		 756 crypto: crypto@30900000 {
757 compatible = "fsl,sec-v4.0";
758 #address-cells = <1>;
759 #size-cells = <1>;
760 reg = <0x30900000 0x40000>;
761 ranges = <0 0x30900000 0x40000>;
762 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
763 clocks = <&clk IMX8MN_CLK_AHB>,
764 <&clk IMX8MN_CLK_IPG_ROOT>;
765 clock-names = "aclk", "ipg";
766
f5ff5a21 767 sec_jr0: jr@1000 {
aad24175
HG		 768 compatible = "fsl,sec-v4.0-job-ring";
769 reg = <0x1000 0x1000>;
770 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
771 };
772
f5ff5a21 773 sec_jr1: jr@2000 {
aad24175
HG		 774 compatible = "fsl,sec-v4.0-job-ring";
775 reg = <0x2000 0x1000>;
776 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
777 };
778
f5ff5a21 779 sec_jr2: jr@3000 {
aad24175
HG		 780 compatible = "fsl,sec-v4.0-job-ring";
781 reg = <0x3000 0x1000>;
782 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
783 };
784 };
785
6c3debcb
AH		 786 i2c1: i2c@30a20000 {
787 compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c";
788 #address-cells = <1>;
789 #size-cells = <0>;
790 reg = <0x30a20000 0x10000>;
791 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
792 clocks = <&clk IMX8MN_CLK_I2C1_ROOT>;
793 status = "disabled";
794 };
795
796 i2c2: i2c@30a30000 {
797 compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c";
798 #address-cells = <1>;
799 #size-cells = <0>;
800 reg = <0x30a30000 0x10000>;
801 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
802 clocks = <&clk IMX8MN_CLK_I2C2_ROOT>;
803 status = "disabled";
804 };
805
806 i2c3: i2c@30a40000 {
807 #address-cells = <1>;
808 #size-cells = <0>;
809 compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c";
810 reg = <0x30a40000 0x10000>;
811 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
812 clocks = <&clk IMX8MN_CLK_I2C3_ROOT>;
813 status = "disabled";
814 };
815
816 i2c4: i2c@30a50000 {
817 compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c";
818 #address-cells = <1>;
819 #size-cells = <0>;
820 reg = <0x30a50000 0x10000>;
821 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
822 clocks = <&clk IMX8MN_CLK_I2C4_ROOT>;
823 status = "disabled";
824 };
825
826 uart4: serial@30a60000 {
827 compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
828 reg = <0x30a60000 0x10000>;
829 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
830 clocks = <&clk IMX8MN_CLK_UART4_ROOT>,
831 <&clk IMX8MN_CLK_UART4_ROOT>;
832 clock-names = "ipg", "per";
833 dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>;
834 dma-names = "rx", "tx";
835 status = "disabled";
836 };
837
bbfc59be
PF		 838 mu: mailbox@30aa0000 {
839 compatible = "fsl,imx8mn-mu", "fsl,imx6sx-mu";
840 reg = <0x30aa0000 0x10000>;
841 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
842 clocks = <&clk IMX8MN_CLK_MU_ROOT>;
843 #mbox-cells = <2>;
844 };
845
6c3debcb
AH		 846 usdhc1: mmc@30b40000 {
847 compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc";
848 reg = <0x30b40000 0x10000>;
849 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
ea65aba8 850 clocks = <&clk IMX8MN_CLK_IPG_ROOT>,
6c3debcb
AH		 851 <&clk IMX8MN_CLK_NAND_USDHC_BUS>,
852 <&clk IMX8MN_CLK_USDHC1_ROOT>;
853 clock-names = "ipg", "ahb", "per";
6c3debcb
AH		 854 fsl,tuning-start-tap = <20>;
855 fsl,tuning-step= <2>;
856 bus-width = <4>;
857 status = "disabled";
858 };
859
860 usdhc2: mmc@30b50000 {
861 compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc";
862 reg = <0x30b50000 0x10000>;
863 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
ea65aba8 864 clocks = <&clk IMX8MN_CLK_IPG_ROOT>,
6c3debcb
AH		 865 <&clk IMX8MN_CLK_NAND_USDHC_BUS>,
866 <&clk IMX8MN_CLK_USDHC2_ROOT>;
867 clock-names = "ipg", "ahb", "per";
868 fsl,tuning-start-tap = <20>;
869 fsl,tuning-step= <2>;
870 bus-width = <4>;
871 status = "disabled";
872 };
873
874 usdhc3: mmc@30b60000 {
875 compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc";
876 reg = <0x30b60000 0x10000>;
877 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
ea65aba8 878 clocks = <&clk IMX8MN_CLK_IPG_ROOT>,
6c3debcb
AH		 879 <&clk IMX8MN_CLK_NAND_USDHC_BUS>,
880 <&clk IMX8MN_CLK_USDHC3_ROOT>;
881 clock-names = "ipg", "ahb", "per";
6c3debcb
AH		 882 fsl,tuning-start-tap = <20>;
883 fsl,tuning-step= <2>;
884 bus-width = <4>;
885 status = "disabled";
886 };
887
888 sdma1: dma-controller@30bd0000 {
958c6014 889 compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma";
6c3debcb
AH		 890 reg = <0x30bd0000 0x10000>;
891 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
892 clocks = <&clk IMX8MN_CLK_SDMA1_ROOT>,
15ddc3e1 893 <&clk IMX8MN_CLK_AHB>;
6c3debcb
AH		 894 clock-names = "ipg", "ahb";
895 #dma-cells = <3>;
896 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
897 };
898
899 fec1: ethernet@30be0000 {
900 compatible = "fsl,imx8mn-fec", "fsl,imx6sx-fec";
901 reg = <0x30be0000 0x10000>;
902 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
903 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
d3762a47
FE		 904 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
905 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
6c3debcb
AH		 906 clocks = <&clk IMX8MN_CLK_ENET1_ROOT>,
907 <&clk IMX8MN_CLK_ENET1_ROOT>,
908 <&clk IMX8MN_CLK_ENET_TIMER>,
909 <&clk IMX8MN_CLK_ENET_REF>,
910 <&clk IMX8MN_CLK_ENET_PHY_REF>;
911 clock-names = "ipg", "ahb", "ptp",
912 "enet_clk_ref", "enet_out";
913 assigned-clocks = <&clk IMX8MN_CLK_ENET_AXI>,
914 <&clk IMX8MN_CLK_ENET_TIMER>,
915 <&clk IMX8MN_CLK_ENET_REF>,
70eacf42 916 <&clk IMX8MN_CLK_ENET_PHY_REF>;
6c3debcb
AH		 917 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_266M>,
918 <&clk IMX8MN_SYS_PLL2_100M>,
70eacf42
JZ		 919 <&clk IMX8MN_SYS_PLL2_125M>,
920 <&clk IMX8MN_SYS_PLL2_50M>;
921 assigned-clock-rates = <0>, <100000000>, <125000000>, <0>;
6c3debcb
AH		 922 fsl,num-tx-queues = <3>;
923 fsl,num-rx-queues = <3>;
924 status = "disabled";
925 };
926
927 };
928
929 aips4: bus@32c00000 {
dc3efc6f 930 compatible = "fsl,aips-bus", "simple-bus";
921a6845 931 reg = <0x32c00000 0x400000>;
6c3debcb
AH		 932 #address-cells = <1>;
933 #size-cells = <1>;
934 ranges;
935
936 usbotg1: usb@32e40000 {
937 compatible = "fsl,imx8mn-usb", "fsl,imx7d-usb";
938 reg = <0x32e40000 0x200>;
939 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
940 clocks = <&clk IMX8MN_CLK_USB1_CTRL_ROOT>;
941 clock-names = "usb1_ctrl_root_clk";
d51cb99c
LJ		 942 assigned-clocks = <&clk IMX8MN_CLK_USB_BUS>;
943 assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_500M>;
6c3debcb
AH		 944 fsl,usbphy = <&usbphynop1>;
945 fsl,usbmisc = <&usbmisc1 0>;
946 status = "disabled";
947 };
948
949 usbmisc1: usbmisc@32e40200 {
950 compatible = "fsl,imx8mn-usbmisc", "fsl,imx7d-usbmisc";
951 #index-cells = <1>;
952 reg = <0x32e40200 0x200>;
953 };
6c3debcb
AH		 954 };
955
956 dma_apbh: dma-controller@33000000 {
957 compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh";
958 reg = <0x33000000 0x2000>;
959 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
960 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
961 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
962 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
963 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
964 #dma-cells = <1>;
965 dma-channels = <4>;
966 clocks = <&clk IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK>;
967 };
968
969 gpmi: nand-controller@33002000 {
970 compatible = "fsl,imx8mn-gpmi-nand", "fsl,imx7d-gpmi-nand";
971 #address-cells = <1>;
972 #size-cells = <1>;
973 reg = <0x33002000 0x2000>, <0x33004000 0x4000>;
974 reg-names = "gpmi-nand", "bch";
975 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
976 interrupt-names = "bch";
977 clocks = <&clk IMX8MN_CLK_NAND_ROOT>,
978 <&clk IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK>;
979 clock-names = "gpmi_io", "gpmi_bch_apb";
980 dmas = <&dma_apbh 0>;
981 dma-names = "rx-tx";
982 status = "disabled";
983 };
984
985 gic: interrupt-controller@38800000 {
986 compatible = "arm,gic-v3";
987 reg = <0x38800000 0x10000>,
988 <0x38880000 0xc0000>;
989 #interrupt-cells = <3>;
990 interrupt-controller;
991 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
992 };
2d8e0747 993
0376f6ec
LC		 994 ddrc: memory-controller@3d400000 {
995 compatible = "fsl,imx8mn-ddrc", "fsl,imx8m-ddrc";
996 reg = <0x3d400000 0x400000>;
997 clock-names = "core", "pll", "alt", "apb";
998 clocks = <&clk IMX8MN_CLK_DRAM_CORE>,
999 <&clk IMX8MN_DRAM_PLL>,
1000 <&clk IMX8MN_CLK_DRAM_ALT>,
1001 <&clk IMX8MN_CLK_DRAM_APB>;
1002 };
1003
2d8e0747
JZ		 1004 ddr-pmu@3d800000 {
1005 compatible = "fsl,imx8mn-ddr-pmu", "fsl,imx8m-ddr-pmu";
1006 reg = <0x3d800000 0x400000>;
1007 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1008 };
6c3debcb
AH		 1009 };
1010
1011 usbphynop1: usbphynop1 {
1012 compatible = "usb-nop-xceiv";
1013 clocks = <&clk IMX8MN_CLK_USB_PHY_REF>;
1014 assigned-clocks = <&clk IMX8MN_CLK_USB_PHY_REF>;
1015 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_100M>;
1016 clock-names = "main_clk";
1017 };
6c3debcb 1018};
Linux 6.x block layer and io_uring tree(s)