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arm64: dts: imx8m: Document the fuse address calculation
[linux-2.6-block.git] / arch / arm64 / boot / dts / freescale / imx8mn.dtsi
CommitLineData
6c3debcb
AH		 1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2019 NXP
4 */
5
6#include <dt-bindings/clock/imx8mn-clock.h>
8b8ebec6
AF		 7#include <dt-bindings/power/imx8mn-power.h>
8#include <dt-bindings/reset/imx8mq-reset.h>
6c3debcb
AH		 9#include <dt-bindings/gpio/gpio.h>
10#include <dt-bindings/input/input.h>
11#include <dt-bindings/interrupt-controller/arm-gic.h>
819779a9 12#include <dt-bindings/thermal/thermal.h>
6c3debcb
AH		 13
14#include "imx8mn-pinfunc.h"
15
16/ {
6c3debcb
AH		 17 interrupt-parent = <&gic>;
18 #address-cells = <2>;
19 #size-cells = <2>;
20
21 aliases {
22 ethernet0 = &fec1;
23 gpio0 = &gpio1;
24 gpio1 = &gpio2;
25 gpio2 = &gpio3;
26 gpio3 = &gpio4;
27 gpio4 = &gpio5;
28 i2c0 = &i2c1;
29 i2c1 = &i2c2;
30 i2c2 = &i2c3;
31 i2c3 = &i2c4;
32 mmc0 = &usdhc1;
33 mmc1 = &usdhc2;
34 mmc2 = &usdhc3;
35 serial0 = &uart1;
36 serial1 = &uart2;
37 serial2 = &uart3;
38 serial3 = &uart4;
39 spi0 = &ecspi1;
40 spi1 = &ecspi2;
41 spi2 = &ecspi3;
42 };
43
44 cpus {
45 #address-cells = <1>;
46 #size-cells = <0>;
47
df844a9a
AH		 48 idle-states {
49 entry-method = "psci";
50
51 cpu_pd_wait: cpu-pd-wait {
52 compatible = "arm,idle-state";
53 arm,psci-suspend-param = <0x0010033>;
54 local-timer-stop;
55 entry-latency-us = <1000>;
56 exit-latency-us = <700>;
57 min-residency-us = <2700>;
58 };
59 };
60
6c3debcb
AH		 61 A53_0: cpu@0 {
62 device_type = "cpu";
63 compatible = "arm,cortex-a53";
64 reg = <0x0>;
65 clock-latency = <61036>;
66 clocks = <&clk IMX8MN_CLK_ARM>;
67 enable-method = "psci";
cb551b5e
PF		 68 i-cache-size = <0x8000>;
69 i-cache-line-size = <64>;
70 i-cache-sets = <256>;
71 d-cache-size = <0x8000>;
72 d-cache-line-size = <64>;
73 d-cache-sets = <128>;
6c3debcb 74 next-level-cache = <&A53_L2>;
01c49314
AH		 75 operating-points-v2 = <&a53_opp_table>;
76 nvmem-cells = <&cpu_speed_grade>;
77 nvmem-cell-names = "speed_grade";
df844a9a 78 cpu-idle-states = <&cpu_pd_wait>;
819779a9 79 #cooling-cells = <2>;
6c3debcb
AH		 80 };
81
82 A53_1: cpu@1 {
83 device_type = "cpu";
84 compatible = "arm,cortex-a53";
85 reg = <0x1>;
86 clock-latency = <61036>;
87 clocks = <&clk IMX8MN_CLK_ARM>;
88 enable-method = "psci";
cb551b5e
PF		 89 i-cache-size = <0x8000>;
90 i-cache-line-size = <64>;
91 i-cache-sets = <256>;
92 d-cache-size = <0x8000>;
93 d-cache-line-size = <64>;
94 d-cache-sets = <128>;
6c3debcb 95 next-level-cache = <&A53_L2>;
01c49314 96 operating-points-v2 = <&a53_opp_table>;
df844a9a 97 cpu-idle-states = <&cpu_pd_wait>;
819779a9 98 #cooling-cells = <2>;
6c3debcb
AH		 99 };
100
101 A53_2: cpu@2 {
102 device_type = "cpu";
103 compatible = "arm,cortex-a53";
104 reg = <0x2>;
105 clock-latency = <61036>;
106 clocks = <&clk IMX8MN_CLK_ARM>;
107 enable-method = "psci";
cb551b5e
PF		 108 i-cache-size = <0x8000>;
109 i-cache-line-size = <64>;
110 i-cache-sets = <256>;
111 d-cache-size = <0x8000>;
112 d-cache-line-size = <64>;
113 d-cache-sets = <128>;
6c3debcb 114 next-level-cache = <&A53_L2>;
01c49314 115 operating-points-v2 = <&a53_opp_table>;
df844a9a 116 cpu-idle-states = <&cpu_pd_wait>;
819779a9 117 #cooling-cells = <2>;
6c3debcb
AH		 118 };
119
120 A53_3: cpu@3 {
121 device_type = "cpu";
122 compatible = "arm,cortex-a53";
123 reg = <0x3>;
124 clock-latency = <61036>;
125 clocks = <&clk IMX8MN_CLK_ARM>;
126 enable-method = "psci";
cb551b5e
PF		 127 i-cache-size = <0x8000>;
128 i-cache-line-size = <64>;
129 i-cache-sets = <256>;
130 d-cache-size = <0x8000>;
131 d-cache-line-size = <64>;
132 d-cache-sets = <128>;
6c3debcb 133 next-level-cache = <&A53_L2>;
01c49314 134 operating-points-v2 = <&a53_opp_table>;
df844a9a 135 cpu-idle-states = <&cpu_pd_wait>;
819779a9 136 #cooling-cells = <2>;
6c3debcb
AH		 137 };
138
139 A53_L2: l2-cache0 {
140 compatible = "cache";
cb551b5e 141 cache-level = <2>;
3b450831 142 cache-unified;
cb551b5e
PF		 143 cache-size = <0x80000>;
144 cache-line-size = <64>;
145 cache-sets = <512>;
6c3debcb
AH		 146 };
147 };
148
01c49314
AH		 149 a53_opp_table: opp-table {
150 compatible = "operating-points-v2";
151 opp-shared;
152
153 opp-1200000000 {
154 opp-hz = /bits/ 64 <1200000000>;
8c30e7ca 155 opp-microvolt = <850000>;
01c49314
AH		 156 opp-supported-hw = <0xb00>, <0x7>;
157 clock-latency-ns = <150000>;
158 opp-suspend;
159 };
160
161 opp-1400000000 {
162 opp-hz = /bits/ 64 <1400000000>;
163 opp-microvolt = <950000>;
164 opp-supported-hw = <0x300>, <0x7>;
165 clock-latency-ns = <150000>;
166 opp-suspend;
167 };
168
169 opp-1500000000 {
170 opp-hz = /bits/ 64 <1500000000>;
171 opp-microvolt = <1000000>;
172 opp-supported-hw = <0x100>, <0x3>;
173 clock-latency-ns = <150000>;
174 opp-suspend;
175 };
176 };
177
6c3debcb
AH		 178 osc_32k: clock-osc-32k {
179 compatible = "fixed-clock";
180 #clock-cells = <0>;
181 clock-frequency = <32768>;
182 clock-output-names = "osc_32k";
183 };
184
185 osc_24m: clock-osc-24m {
186 compatible = "fixed-clock";
187 #clock-cells = <0>;
188 clock-frequency = <24000000>;
189 clock-output-names = "osc_24m";
190 };
191
192 clk_ext1: clock-ext1 {
193 compatible = "fixed-clock";
194 #clock-cells = <0>;
195 clock-frequency = <133000000>;
196 clock-output-names = "clk_ext1";
197 };
198
199 clk_ext2: clock-ext2 {
200 compatible = "fixed-clock";
201 #clock-cells = <0>;
202 clock-frequency = <133000000>;
203 clock-output-names = "clk_ext2";
204 };
205
206 clk_ext3: clock-ext3 {
207 compatible = "fixed-clock";
208 #clock-cells = <0>;
209 clock-frequency = <133000000>;
210 clock-output-names = "clk_ext3";
211 };
212
213 clk_ext4: clock-ext4 {
214 compatible = "fixed-clock";
215 #clock-cells = <0>;
33597c62 216 clock-frequency = <133000000>;
6c3debcb
AH		 217 clock-output-names = "clk_ext4";
218 };
219
c13a7d84
JB		 220 pmu {
221 compatible = "arm,cortex-a53-pmu";
222 interrupts = <GIC_PPI 7
223 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
c13a7d84
JB		 224 };
225
6c3debcb
AH		 226 psci {
227 compatible = "arm,psci-1.0";
228 method = "smc";
229 };
230
819779a9
AH		 231 thermal-zones {
232 cpu-thermal {
233 polling-delay-passive = <250>;
234 polling-delay = <2000>;
235 thermal-sensors = <&tmu>;
236 trips {
237 cpu_alert0: trip0 {
238 temperature = <85000>;
239 hysteresis = <2000>;
240 type = "passive";
241 };
242
243 cpu_crit0: trip1 {
244 temperature = <95000>;
245 hysteresis = <2000>;
246 type = "critical";
247 };
248 };
249
250 cooling-maps {
251 map0 {
252 trip = <&cpu_alert0>;
253 cooling-device =
254 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
255 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
256 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
257 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
258 };
259 };
260 };
261 };
262
6c3debcb
AH		 263 timer {
264 compatible = "arm,armv8-timer";
0656e37a
KK		 265 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
266 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
267 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
268 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
6c3debcb
AH		 269 clock-frequency = <8000000>;
270 arm,no-tick-in-suspend;
271 };
272
fcdef92b 273 soc: soc@0 {
ce58459d 274 compatible = "fsl,imx8mn-soc", "simple-bus";
6c3debcb
AH		 275 #address-cells = <1>;
276 #size-cells = <1>;
277 ranges = <0x0 0x0 0x0 0x3e000000>;
8d923cdf 278 dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>;
cbff2379
AG		 279 nvmem-cells = <&imx8mn_uid>;
280 nvmem-cell-names = "soc_unique_id";
6c3debcb
AH		 281
282 aips1: bus@30000000 {
dc3efc6f 283 compatible = "fsl,aips-bus", "simple-bus";
921a6845 284 reg = <0x30000000 0x400000>;
6c3debcb
AH		 285 #address-cells = <1>;
286 #size-cells = <1>;
287 ranges;
288
292e0f48 289 spba2: spba-bus@30000000 {
970406ea
AF		 290 compatible = "fsl,spba-bus", "simple-bus";
291 #address-cells = <1>;
292 #size-cells = <1>;
293 reg = <0x30000000 0x100000>;
294 ranges;
295
9e986006 296 sai2: sai@30020000 {
574518b7 297 compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai";
9e986006
AF		 298 reg = <0x30020000 0x10000>;
299 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
300 clocks = <&clk IMX8MN_CLK_SAI2_IPG>,
301 <&clk IMX8MN_CLK_DUMMY>,
302 <&clk IMX8MN_CLK_SAI2_ROOT>,
303 <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>;
304 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
305 dmas = <&sdma2 2 2 0>, <&sdma2 3 2 0>;
306 dma-names = "rx", "tx";
307 status = "disabled";
308 };
309
310 sai3: sai@30030000 {
574518b7 311 compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai";
9e986006
AF		 312 reg = <0x30030000 0x10000>;
313 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
314 clocks = <&clk IMX8MN_CLK_SAI3_IPG>,
315 <&clk IMX8MN_CLK_DUMMY>,
316 <&clk IMX8MN_CLK_SAI3_ROOT>,
317 <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>;
318 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
319 dmas = <&sdma2 4 2 0>, <&sdma2 5 2 0>;
320 dma-names = "rx", "tx";
321 status = "disabled";
322 };
323
324 sai5: sai@30050000 {
574518b7 325 compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai";
9e986006
AF		 326 reg = <0x30050000 0x10000>;
327 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
328 clocks = <&clk IMX8MN_CLK_SAI5_IPG>,
329 <&clk IMX8MN_CLK_DUMMY>,
330 <&clk IMX8MN_CLK_SAI5_ROOT>,
331 <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>;
332 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
333 dmas = <&sdma2 8 2 0>, <&sdma2 9 2 0>;
334 dma-names = "rx", "tx";
335 fsl,shared-interrupt;
336 fsl,dataline = <0 0xf 0xf>;
337 status = "disabled";
338 };
339
340 sai6: sai@30060000 {
574518b7 341 compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai";
9e986006
AF		 342 reg = <0x30060000 0x10000>;
343 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
344 clocks = <&clk IMX8MN_CLK_SAI6_IPG>,
345 <&clk IMX8MN_CLK_DUMMY>,
346 <&clk IMX8MN_CLK_SAI6_ROOT>,
347 <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>;
348 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
349 dmas = <&sdma2 10 2 0>, <&sdma2 11 2 0>;
350 dma-names = "rx", "tx";
351 status = "disabled";
352 };
353
cca69ef6
AF		 354 micfil: audio-controller@30080000 {
355 compatible = "fsl,imx8mm-micfil";
356 reg = <0x30080000 0x10000>;
357 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
358 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
359 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
360 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
361 clocks = <&clk IMX8MN_CLK_PDM_IPG>,
362 <&clk IMX8MN_CLK_PDM_ROOT>,
363 <&clk IMX8MN_AUDIO_PLL1_OUT>,
364 <&clk IMX8MN_AUDIO_PLL2_OUT>,
365 <&clk IMX8MN_CLK_EXT3>;
366 clock-names = "ipg_clk", "ipg_clk_app",
367 "pll8k", "pll11k", "clkext3";
368 dmas = <&sdma2 24 25 0x80000000>;
369 dma-names = "rx";
370 status = "disabled";
371 };
372
b9cf7d3b
AF		 373 spdif1: spdif@30090000 {
374 compatible = "fsl,imx35-spdif";
375 reg = <0x30090000 0x10000>;
376 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
377 clocks = <&clk IMX8MN_CLK_AUDIO_AHB>, /* core */
378 <&clk IMX8MN_CLK_24M>, /* rxtx0 */
379 <&clk IMX8MN_CLK_SPDIF1>, /* rxtx1 */
380 <&clk IMX8MN_CLK_DUMMY>, /* rxtx2 */
381 <&clk IMX8MN_CLK_DUMMY>, /* rxtx3 */
382 <&clk IMX8MN_CLK_DUMMY>, /* rxtx4 */
383 <&clk IMX8MN_CLK_AUDIO_AHB>, /* rxtx5 */
384 <&clk IMX8MN_CLK_DUMMY>, /* rxtx6 */
385 <&clk IMX8MN_CLK_DUMMY>, /* rxtx7 */
386 <&clk IMX8MN_CLK_DUMMY>; /* spba */
387 clock-names = "core", "rxtx0",
388 "rxtx1", "rxtx2",
389 "rxtx3", "rxtx4",
390 "rxtx5", "rxtx6",
391 "rxtx7", "spba";
392 dmas = <&sdma2 28 18 0>, <&sdma2 29 18 0>;
393 dma-names = "rx", "tx";
394 status = "disabled";
395 };
396
9e986006 397 sai7: sai@300b0000 {
574518b7 398 compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai";
9e986006
AF		 399 reg = <0x300b0000 0x10000>;
400 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
401 clocks = <&clk IMX8MN_CLK_SAI7_IPG>,
402 <&clk IMX8MN_CLK_DUMMY>,
403 <&clk IMX8MN_CLK_SAI7_ROOT>,
404 <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>;
405 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
406 dmas = <&sdma2 12 2 0>, <&sdma2 13 2 0>;
407 dma-names = "rx", "tx";
408 status = "disabled";
409 };
410
970406ea
AF		 411 easrc: easrc@300c0000 {
412 compatible = "fsl,imx8mn-easrc";
413 reg = <0x300c0000 0x10000>;
414 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
415 clocks = <&clk IMX8MN_CLK_ASRC_ROOT>;
416 clock-names = "mem";
417 dmas = <&sdma2 16 23 0> , <&sdma2 17 23 0>,
418 <&sdma2 18 23 0> , <&sdma2 19 23 0>,
419 <&sdma2 20 23 0> , <&sdma2 21 23 0>,
420 <&sdma2 22 23 0> , <&sdma2 23 23 0>;
421 dma-names = "ctx0_rx", "ctx0_tx",
422 "ctx1_rx", "ctx1_tx",
423 "ctx2_rx", "ctx2_tx",
424 "ctx3_rx", "ctx3_tx";
425 firmware-name = "imx/easrc/easrc-imx8mn.bin";
33597c62 426 fsl,asrc-rate = <8000>;
970406ea
AF		 427 fsl,asrc-format = <2>;
428 status = "disabled";
429 };
430 };
431
6c3debcb
AH		 432 gpio1: gpio@30200000 {
433 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
434 reg = <0x30200000 0x10000>;
435 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
436 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
437 clocks = <&clk IMX8MN_CLK_GPIO1_ROOT>;
438 gpio-controller;
439 #gpio-cells = <2>;
440 interrupt-controller;
441 #interrupt-cells = <2>;
ee8696be 442 gpio-ranges = <&iomuxc 0 10 30>;
6c3debcb
AH		 443 };
444
445 gpio2: gpio@30210000 {
446 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
447 reg = <0x30210000 0x10000>;
448 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
449 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
450 clocks = <&clk IMX8MN_CLK_GPIO2_ROOT>;
451 gpio-controller;
452 #gpio-cells = <2>;
453 interrupt-controller;
454 #interrupt-cells = <2>;
ee8696be 455 gpio-ranges = <&iomuxc 0 40 21>;
6c3debcb
AH		 456 };
457
458 gpio3: gpio@30220000 {
459 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
460 reg = <0x30220000 0x10000>;
461 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
462 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
463 clocks = <&clk IMX8MN_CLK_GPIO3_ROOT>;
464 gpio-controller;
465 #gpio-cells = <2>;
466 interrupt-controller;
467 #interrupt-cells = <2>;
ee8696be 468 gpio-ranges = <&iomuxc 0 61 26>;
6c3debcb
AH		 469 };
470
471 gpio4: gpio@30230000 {
472 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
473 reg = <0x30230000 0x10000>;
474 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
475 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
476 clocks = <&clk IMX8MN_CLK_GPIO4_ROOT>;
477 gpio-controller;
478 #gpio-cells = <2>;
479 interrupt-controller;
480 #interrupt-cells = <2>;
ee8696be 481 gpio-ranges = <&iomuxc 21 108 11>;
6c3debcb
AH		 482 };
483
484 gpio5: gpio@30240000 {
485 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
486 reg = <0x30240000 0x10000>;
487 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
488 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
489 clocks = <&clk IMX8MN_CLK_GPIO5_ROOT>;
490 gpio-controller;
491 #gpio-cells = <2>;
492 interrupt-controller;
493 #interrupt-cells = <2>;
ee8696be 494 gpio-ranges = <&iomuxc 0 119 30>;
6c3debcb
AH		 495 };
496
819779a9
AH		 497 tmu: tmu@30260000 {
498 compatible = "fsl,imx8mn-tmu", "fsl,imx8mm-tmu";
499 reg = <0x30260000 0x10000>;
500 clocks = <&clk IMX8MN_CLK_TMU_ROOT>;
501 #thermal-sensor-cells = <0>;
502 };
503
6c3debcb
AH		 504 wdog1: watchdog@30280000 {
505 compatible = "fsl,imx8mn-wdt", "fsl,imx21-wdt";
506 reg = <0x30280000 0x10000>;
507 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
508 clocks = <&clk IMX8MN_CLK_WDOG1_ROOT>;
509 status = "disabled";
510 };
511
512 wdog2: watchdog@30290000 {
513 compatible = "fsl,imx8mn-wdt", "fsl,imx21-wdt";
514 reg = <0x30290000 0x10000>;
515 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
516 clocks = <&clk IMX8MN_CLK_WDOG2_ROOT>;
517 status = "disabled";
518 };
519
520 wdog3: watchdog@302a0000 {
521 compatible = "fsl,imx8mn-wdt", "fsl,imx21-wdt";
522 reg = <0x302a0000 0x10000>;
523 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
524 clocks = <&clk IMX8MN_CLK_WDOG3_ROOT>;
525 status = "disabled";
526 };
527
528 sdma3: dma-controller@302b0000 {
958c6014 529 compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma";
6c3debcb
AH		 530 reg = <0x302b0000 0x10000>;
531 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
532 clocks = <&clk IMX8MN_CLK_SDMA3_ROOT>,
533 <&clk IMX8MN_CLK_SDMA3_ROOT>;
534 clock-names = "ipg", "ahb";
535 #dma-cells = <3>;
536 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
537 };
538
539 sdma2: dma-controller@302c0000 {
958c6014 540 compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma";
6c3debcb
AH		 541 reg = <0x302c0000 0x10000>;
542 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
543 clocks = <&clk IMX8MN_CLK_SDMA2_ROOT>,
544 <&clk IMX8MN_CLK_SDMA2_ROOT>;
545 clock-names = "ipg", "ahb";
546 #dma-cells = <3>;
547 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
548 };
549
550 iomuxc: pinctrl@30330000 {
551 compatible = "fsl,imx8mn-iomuxc";
552 reg = <0x30330000 0x10000>;
553 };
554
555 gpr: iomuxc-gpr@30340000 {
556 compatible = "fsl,imx8mn-iomuxc-gpr", "syscon";
557 reg = <0x30340000 0x10000>;
558 };
559
12fa1078 560 ocotp: efuse@30350000 {
2bad8c48 561 compatible = "fsl,imx8mn-ocotp", "fsl,imx8mm-ocotp", "syscon";
6c3debcb
AH		 562 reg = <0x30350000 0x10000>;
563 clocks = <&clk IMX8MN_CLK_OCOTP_ROOT>;
01c49314
AH		 564 #address-cells = <1>;
565 #size-cells = <1>;
566
5b81a87d
MV		 567 /*
568 * The register address below maps to the MX8M
569 * Fusemap Description Table entries this way.
570 * Assuming
571 * reg = <ADDR SIZE>;
572 * then
573 * Fuse Address = (ADDR * 4) + 0x400
574 * Note that if SIZE is greater than 4, then
575 * each subsequent fuse is located at offset
576 * +0x10 in Fusemap Description Table (e.g.
577 * reg = <0x4 0x8> describes fuses 0x410 and
578 * 0x420).
579 */
580 imx8mn_uid: unique-id@4 { /* 0x410-0x420 */
cbff2379
AG		 581 reg = <0x4 0x8>;
582 };
583
5b81a87d 584 cpu_speed_grade: speed-grade@10 { /* 0x440 */
01c49314
AH		 585 reg = <0x10 4>;
586 };
066438ae 587
5b81a87d 588 fec_mac_address: mac-address@90 { /* 0x640 */
066438ae
JZ		 589 reg = <0x90 6>;
590 };
6c3debcb
AH		 591 };
592
f98c2dfe
PF		 593 anatop: clock-controller@30360000 {
594 compatible = "fsl,imx8mn-anatop", "fsl,imx8mm-anatop";
6c3debcb 595 reg = <0x30360000 0x10000>;
f98c2dfe 596 #clock-cells = <1>;
6c3debcb
AH		 597 };
598
599 snvs: snvs@30370000 {
600 compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd";
601 reg = <0x30370000 0x10000>;
602
603 snvs_rtc: snvs-rtc-lp {
604 compatible = "fsl,sec-v4.0-mon-rtc-lp";
605 regmap = <&snvs>;
606 offset = <0x34>;
607 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
608 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
42ef961b 609 clocks = <&clk IMX8MN_CLK_SNVS_ROOT>;
6c3debcb
AH		 610 clock-names = "snvs-rtc";
611 };
612
613 snvs_pwrkey: snvs-powerkey {
614 compatible = "fsl,sec-v4.0-pwrkey";
615 regmap = <&snvs>;
616 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
c2a2f446
AH		 617 clocks = <&clk IMX8MN_CLK_SNVS_ROOT>;
618 clock-names = "snvs-pwrkey";
6c3debcb
AH		 619 linux,keycode = <KEY_POWER>;
620 wakeup-source;
621 status = "disabled";
622 };
623 };
624
625 clk: clock-controller@30380000 {
626 compatible = "fsl,imx8mn-ccm";
627 reg = <0x30380000 0x10000>;
628 #clock-cells = <1>;
629 clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>,
630 <&clk_ext3>, <&clk_ext4>;
631 clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
632 "clk_ext3", "clk_ext4";
9e6337e6
PF		 633 assigned-clocks = <&clk IMX8MN_CLK_A53_SRC>,
634 <&clk IMX8MN_CLK_A53_CORE>,
635 <&clk IMX8MN_CLK_NOC>,
53458f86
PF		 636 <&clk IMX8MN_CLK_AUDIO_AHB>,
637 <&clk IMX8MN_CLK_IPG_AUDIO_ROOT>,
26442c79
SW		 638 <&clk IMX8MN_SYS_PLL3>,
639 <&clk IMX8MN_AUDIO_PLL1>,
640 <&clk IMX8MN_AUDIO_PLL2>;
9e6337e6
PF		 641 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_800M>,
642 <&clk IMX8MN_ARM_PLL_OUT>,
643 <&clk IMX8MN_SYS_PLL3_OUT>,
53458f86 644 <&clk IMX8MN_SYS_PLL1_800M>;
9e6337e6 645 assigned-clock-rates = <0>, <0>, <0>,
53458f86
PF		 646 <400000000>,
647 <400000000>,
26442c79
SW		 648 <600000000>,
649 <393216000>,
650 <361267200>;
6c3debcb
AH		 651 };
652
653 src: reset-controller@30390000 {
23b80c20 654 compatible = "fsl,imx8mn-src", "fsl,imx8mq-src", "syscon";
6c3debcb
AH		 655 reg = <0x30390000 0x10000>;
656 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
657 #reset-cells = <1>;
658 };
8b8ebec6
AF		 659
660 gpc: gpc@303a0000 {
661 compatible = "fsl,imx8mn-gpc";
662 reg = <0x303a0000 0x10000>;
663 interrupt-parent = <&gic>;
664 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
665
666 pgc {
667 #address-cells = <1>;
668 #size-cells = <0>;
669
670 pgc_hsiomix: power-domain@0 {
671 #power-domain-cells = <0>;
672 reg = <IMX8MN_POWER_DOMAIN_HSIOMIX>;
673 clocks = <&clk IMX8MN_CLK_USB_BUS>;
674 };
675
676 pgc_otg1: power-domain@1 {
677 #power-domain-cells = <0>;
678 reg = <IMX8MN_POWER_DOMAIN_OTG1>;
8b8ebec6
AF		 679 };
680
681 pgc_gpumix: power-domain@2 {
682 #power-domain-cells = <0>;
683 reg = <IMX8MN_POWER_DOMAIN_GPUMIX>;
684 clocks = <&clk IMX8MN_CLK_GPU_CORE_ROOT>,
685 <&clk IMX8MN_CLK_GPU_SHADER>,
686 <&clk IMX8MN_CLK_GPU_BUS_ROOT>,
687 <&clk IMX8MN_CLK_GPU_AHB>;
8b8ebec6
AF		 688 };
689
690 pgc_dispmix: power-domain@3 {
691 #power-domain-cells = <0>;
692 reg = <IMX8MN_POWER_DOMAIN_DISPMIX>;
693 clocks = <&clk IMX8MN_CLK_DISP_AXI_ROOT>,
694 <&clk IMX8MN_CLK_DISP_APB_ROOT>;
695 };
696
697 pgc_mipi: power-domain@4 {
698 #power-domain-cells = <0>;
699 reg = <IMX8MN_POWER_DOMAIN_MIPI>;
700 power-domains = <&pgc_dispmix>;
701 };
702 };
703 };
6c3debcb
AH		 704 };
705
706 aips2: bus@30400000 {
dc3efc6f 707 compatible = "fsl,aips-bus", "simple-bus";
921a6845 708 reg = <0x30400000 0x400000>;
6c3debcb
AH		 709 #address-cells = <1>;
710 #size-cells = <1>;
711 ranges;
712
713 pwm1: pwm@30660000 {
714 compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm";
715 reg = <0x30660000 0x10000>;
716 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
717 clocks = <&clk IMX8MN_CLK_PWM1_ROOT>,
718 <&clk IMX8MN_CLK_PWM1_ROOT>;
719 clock-names = "ipg", "per";
6bc1e580 720 #pwm-cells = <3>;
6c3debcb
AH		 721 status = "disabled";
722 };
723
724 pwm2: pwm@30670000 {
725 compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm";
726 reg = <0x30670000 0x10000>;
727 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
728 clocks = <&clk IMX8MN_CLK_PWM2_ROOT>,
729 <&clk IMX8MN_CLK_PWM2_ROOT>;
730 clock-names = "ipg", "per";
6bc1e580 731 #pwm-cells = <3>;
6c3debcb
AH		 732 status = "disabled";
733 };
734
735 pwm3: pwm@30680000 {
736 compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm";
737 reg = <0x30680000 0x10000>;
738 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
739 clocks = <&clk IMX8MN_CLK_PWM3_ROOT>,
740 <&clk IMX8MN_CLK_PWM3_ROOT>;
741 clock-names = "ipg", "per";
6bc1e580 742 #pwm-cells = <3>;
6c3debcb
AH		 743 status = "disabled";
744 };
745
746 pwm4: pwm@30690000 {
747 compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm";
748 reg = <0x30690000 0x10000>;
749 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
750 clocks = <&clk IMX8MN_CLK_PWM4_ROOT>,
751 <&clk IMX8MN_CLK_PWM4_ROOT>;
752 clock-names = "ipg", "per";
6bc1e580 753 #pwm-cells = <3>;
6c3debcb
AH		 754 status = "disabled";
755 };
c4a21269
AH		 756
757 system_counter: timer@306a0000 {
758 compatible = "nxp,sysctr-timer";
759 reg = <0x306a0000 0x20000>;
760 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
761 clocks = <&osc_24m>;
762 clock-names = "per";
763 };
6c3debcb
AH		 764 };
765
766 aips3: bus@30800000 {
dc3efc6f 767 compatible = "fsl,aips-bus", "simple-bus";
921a6845 768 reg = <0x30800000 0x400000>;
6c3debcb
AH		 769 #address-cells = <1>;
770 #size-cells = <1>;
771 ranges;
772
292e0f48
AF		 773 spba1: spba-bus@30800000 {
774 compatible = "fsl,spba-bus", "simple-bus";
6c3debcb 775 #address-cells = <1>;
292e0f48
AF		 776 #size-cells = <1>;
777 reg = <0x30800000 0x100000>;
778 ranges;
6c3debcb 779
292e0f48
AF		 780 ecspi1: spi@30820000 {
781 compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi";
782 #address-cells = <1>;
783 #size-cells = <0>;
784 reg = <0x30820000 0x10000>;
785 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
786 clocks = <&clk IMX8MN_CLK_ECSPI1_ROOT>,
787 <&clk IMX8MN_CLK_ECSPI1_ROOT>;
788 clock-names = "ipg", "per";
789 dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
790 dma-names = "rx", "tx";
791 status = "disabled";
792 };
6c3debcb 793
292e0f48
AF		 794 ecspi2: spi@30830000 {
795 compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi";
796 #address-cells = <1>;
797 #size-cells = <0>;
798 reg = <0x30830000 0x10000>;
799 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
800 clocks = <&clk IMX8MN_CLK_ECSPI2_ROOT>,
801 <&clk IMX8MN_CLK_ECSPI2_ROOT>;
802 clock-names = "ipg", "per";
803 dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;
804 dma-names = "rx", "tx";
805 status = "disabled";
806 };
6c3debcb 807
292e0f48
AF		 808 ecspi3: spi@30840000 {
809 compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi";
810 #address-cells = <1>;
811 #size-cells = <0>;
812 reg = <0x30840000 0x10000>;
813 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
814 clocks = <&clk IMX8MN_CLK_ECSPI3_ROOT>,
815 <&clk IMX8MN_CLK_ECSPI3_ROOT>;
816 clock-names = "ipg", "per";
817 dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;
818 dma-names = "rx", "tx";
819 status = "disabled";
820 };
6c3debcb 821
292e0f48
AF		 822 uart1: serial@30860000 {
823 compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
824 reg = <0x30860000 0x10000>;
825 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
826 clocks = <&clk IMX8MN_CLK_UART1_ROOT>,
827 <&clk IMX8MN_CLK_UART1_ROOT>;
828 clock-names = "ipg", "per";
829 dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;
830 dma-names = "rx", "tx";
831 status = "disabled";
832 };
6c3debcb 833
292e0f48
AF		 834 uart3: serial@30880000 {
835 compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
836 reg = <0x30880000 0x10000>;
837 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
838 clocks = <&clk IMX8MN_CLK_UART3_ROOT>,
839 <&clk IMX8MN_CLK_UART3_ROOT>;
840 clock-names = "ipg", "per";
841 dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;
842 dma-names = "rx", "tx";
843 status = "disabled";
844 };
845
846 uart2: serial@30890000 {
847 compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
848 reg = <0x30890000 0x10000>;
849 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
850 clocks = <&clk IMX8MN_CLK_UART2_ROOT>,
851 <&clk IMX8MN_CLK_UART2_ROOT>;
852 clock-names = "ipg", "per";
853 status = "disabled";
854 };
6c3debcb
AH		 855 };
856
aad24175
HG		 857 crypto: crypto@30900000 {
858 compatible = "fsl,sec-v4.0";
859 #address-cells = <1>;
860 #size-cells = <1>;
861 reg = <0x30900000 0x40000>;
862 ranges = <0 0x30900000 0x40000>;
863 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
864 clocks = <&clk IMX8MN_CLK_AHB>,
865 <&clk IMX8MN_CLK_IPG_ROOT>;
866 clock-names = "aclk", "ipg";
867
f5ff5a21 868 sec_jr0: jr@1000 {
aad24175
HG		 869 compatible = "fsl,sec-v4.0-job-ring";
870 reg = <0x1000 0x1000>;
871 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
dc9c1ceb 872 status = "disabled";
aad24175
HG		 873 };
874
f5ff5a21 875 sec_jr1: jr@2000 {
aad24175
HG		 876 compatible = "fsl,sec-v4.0-job-ring";
877 reg = <0x2000 0x1000>;
878 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
879 };
880
f5ff5a21 881 sec_jr2: jr@3000 {
aad24175
HG		 882 compatible = "fsl,sec-v4.0-job-ring";
883 reg = <0x3000 0x1000>;
884 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
885 };
886 };
887
6c3debcb
AH		 888 i2c1: i2c@30a20000 {
889 compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c";
890 #address-cells = <1>;
891 #size-cells = <0>;
892 reg = <0x30a20000 0x10000>;
893 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
894 clocks = <&clk IMX8MN_CLK_I2C1_ROOT>;
895 status = "disabled";
896 };
897
898 i2c2: i2c@30a30000 {
899 compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c";
900 #address-cells = <1>;
901 #size-cells = <0>;
902 reg = <0x30a30000 0x10000>;
903 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
904 clocks = <&clk IMX8MN_CLK_I2C2_ROOT>;
905 status = "disabled";
906 };
907
908 i2c3: i2c@30a40000 {
909 #address-cells = <1>;
910 #size-cells = <0>;
911 compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c";
912 reg = <0x30a40000 0x10000>;
913 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
914 clocks = <&clk IMX8MN_CLK_I2C3_ROOT>;
915 status = "disabled";
916 };
917
918 i2c4: i2c@30a50000 {
919 compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c";
920 #address-cells = <1>;
921 #size-cells = <0>;
922 reg = <0x30a50000 0x10000>;
923 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
924 clocks = <&clk IMX8MN_CLK_I2C4_ROOT>;
925 status = "disabled";
926 };
927
928 uart4: serial@30a60000 {
929 compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
930 reg = <0x30a60000 0x10000>;
931 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
932 clocks = <&clk IMX8MN_CLK_UART4_ROOT>,
933 <&clk IMX8MN_CLK_UART4_ROOT>;
934 clock-names = "ipg", "per";
935 dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>;
936 dma-names = "rx", "tx";
937 status = "disabled";
938 };
939
bbfc59be
PF		 940 mu: mailbox@30aa0000 {
941 compatible = "fsl,imx8mn-mu", "fsl,imx6sx-mu";
942 reg = <0x30aa0000 0x10000>;
943 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
944 clocks = <&clk IMX8MN_CLK_MU_ROOT>;
945 #mbox-cells = <2>;
946 };
947
6c3debcb 948 usdhc1: mmc@30b40000 {
472f20b4 949 compatible = "fsl,imx8mn-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
6c3debcb
AH		 950 reg = <0x30b40000 0x10000>;
951 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
ea65aba8 952 clocks = <&clk IMX8MN_CLK_IPG_ROOT>,
6c3debcb
AH		 953 <&clk IMX8MN_CLK_NAND_USDHC_BUS>,
954 <&clk IMX8MN_CLK_USDHC1_ROOT>;
955 clock-names = "ipg", "ahb", "per";
6c3debcb 956 fsl,tuning-start-tap = <20>;
33597c62 957 fsl,tuning-step = <2>;
6c3debcb
AH		 958 bus-width = <4>;
959 status = "disabled";
960 };
961
962 usdhc2: mmc@30b50000 {
472f20b4 963 compatible = "fsl,imx8mn-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
6c3debcb
AH		 964 reg = <0x30b50000 0x10000>;
965 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
ea65aba8 966 clocks = <&clk IMX8MN_CLK_IPG_ROOT>,
6c3debcb
AH		 967 <&clk IMX8MN_CLK_NAND_USDHC_BUS>,
968 <&clk IMX8MN_CLK_USDHC2_ROOT>;
969 clock-names = "ipg", "ahb", "per";
970 fsl,tuning-start-tap = <20>;
33597c62 971 fsl,tuning-step = <2>;
6c3debcb
AH		 972 bus-width = <4>;
973 status = "disabled";
974 };
975
976 usdhc3: mmc@30b60000 {
472f20b4 977 compatible = "fsl,imx8mn-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
6c3debcb
AH		 978 reg = <0x30b60000 0x10000>;
979 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
ea65aba8 980 clocks = <&clk IMX8MN_CLK_IPG_ROOT>,
6c3debcb
AH		 981 <&clk IMX8MN_CLK_NAND_USDHC_BUS>,
982 <&clk IMX8MN_CLK_USDHC3_ROOT>;
983 clock-names = "ipg", "ahb", "per";
6c3debcb 984 fsl,tuning-start-tap = <20>;
33597c62 985 fsl,tuning-step = <2>;
6c3debcb
AH		 986 bus-width = <4>;
987 status = "disabled";
988 };
989
189f6586
AF		 990 flexspi: spi@30bb0000 {
991 #address-cells = <1>;
992 #size-cells = <0>;
993 compatible = "nxp,imx8mm-fspi";
994 reg = <0x30bb0000 0x10000>, <0x8000000 0x10000000>;
995 reg-names = "fspi_base", "fspi_mmap";
996 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
997 clocks = <&clk IMX8MN_CLK_QSPI_ROOT>,
998 <&clk IMX8MN_CLK_QSPI_ROOT>;
f29fa744 999 clock-names = "fspi_en", "fspi";
189f6586
AF		 1000 status = "disabled";
1001 };
1002
6c3debcb 1003 sdma1: dma-controller@30bd0000 {
958c6014 1004 compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma";
6c3debcb
AH		 1005 reg = <0x30bd0000 0x10000>;
1006 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
1007 clocks = <&clk IMX8MN_CLK_SDMA1_ROOT>,
15ddc3e1 1008 <&clk IMX8MN_CLK_AHB>;
6c3debcb
AH		 1009 clock-names = "ipg", "ahb";
1010 #dma-cells = <3>;
1011 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
1012 };
1013
1014 fec1: ethernet@30be0000 {
a758dee8 1015 compatible = "fsl,imx8mn-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec";
6c3debcb
AH		 1016 reg = <0x30be0000 0x10000>;
1017 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
1018 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
d3762a47
FE		 1019 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
1020 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
6c3debcb
AH		 1021 clocks = <&clk IMX8MN_CLK_ENET1_ROOT>,
1022 <&clk IMX8MN_CLK_ENET1_ROOT>,
1023 <&clk IMX8MN_CLK_ENET_TIMER>,
1024 <&clk IMX8MN_CLK_ENET_REF>,
1025 <&clk IMX8MN_CLK_ENET_PHY_REF>;
1026 clock-names = "ipg", "ahb", "ptp",
1027 "enet_clk_ref", "enet_out";
1028 assigned-clocks = <&clk IMX8MN_CLK_ENET_AXI>,
1029 <&clk IMX8MN_CLK_ENET_TIMER>,
1030 <&clk IMX8MN_CLK_ENET_REF>,
70eacf42 1031 <&clk IMX8MN_CLK_ENET_PHY_REF>;
6c3debcb
AH		 1032 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_266M>,
1033 <&clk IMX8MN_SYS_PLL2_100M>,
70eacf42
JZ		 1034 <&clk IMX8MN_SYS_PLL2_125M>,
1035 <&clk IMX8MN_SYS_PLL2_50M>;
1036 assigned-clock-rates = <0>, <100000000>, <125000000>, <0>;
6c3debcb
AH		 1037 fsl,num-tx-queues = <3>;
1038 fsl,num-rx-queues = <3>;
066438ae
JZ		 1039 nvmem-cells = <&fec_mac_address>;
1040 nvmem-cell-names = "mac-address";
afe99354 1041 fsl,stop-mode = <&gpr 0x10 3>;
6c3debcb
AH		 1042 status = "disabled";
1043 };
1044
1045 };
1046
1047 aips4: bus@32c00000 {
dc3efc6f 1048 compatible = "fsl,aips-bus", "simple-bus";
921a6845 1049 reg = <0x32c00000 0x400000>;
6c3debcb
AH		 1050 #address-cells = <1>;
1051 #size-cells = <1>;
1052 ranges;
1053
18d4a6c9
AF		 1054 disp_blk_ctrl: blk-ctrl@32e28000 {
1055 compatible = "fsl,imx8mn-disp-blk-ctrl", "syscon";
1056 reg = <0x32e28000 0x100>;
1057 power-domains = <&pgc_dispmix>, <&pgc_dispmix>,
1058 <&pgc_dispmix>, <&pgc_mipi>,
1059 <&pgc_mipi>;
1060 power-domain-names = "bus", "isi",
1061 "lcdif", "mipi-dsi",
1062 "mipi-csi";
1063 clocks = <&clk IMX8MN_CLK_DISP_AXI>,
1064 <&clk IMX8MN_CLK_DISP_APB>,
1065 <&clk IMX8MN_CLK_DISP_AXI_ROOT>,
1066 <&clk IMX8MN_CLK_DISP_APB_ROOT>,
1067 <&clk IMX8MN_CLK_DISP_AXI_ROOT>,
1068 <&clk IMX8MN_CLK_DISP_APB_ROOT>,
1069 <&clk IMX8MN_CLK_DISP_PIXEL_ROOT>,
1070 <&clk IMX8MN_CLK_DSI_CORE>,
1071 <&clk IMX8MN_CLK_DSI_PHY_REF>,
1072 <&clk IMX8MN_CLK_CSI1_PHY_REF>,
1073 <&clk IMX8MN_CLK_CAMERA_PIXEL_ROOT>;
1074 clock-names = "disp_axi", "disp_apb",
1075 "disp_axi_root", "disp_apb_root",
1076 "lcdif-axi", "lcdif-apb", "lcdif-pix",
1077 "dsi-pclk", "dsi-ref",
1078 "csi-aclk", "csi-pclk";
1079 #power-domain-cells = <1>;
1080 };
1081
6c3debcb
AH		 1082 usbotg1: usb@32e40000 {
1083 compatible = "fsl,imx8mn-usb", "fsl,imx7d-usb";
1084 reg = <0x32e40000 0x200>;
1085 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
1086 clocks = <&clk IMX8MN_CLK_USB1_CTRL_ROOT>;
1087 clock-names = "usb1_ctrl_root_clk";
d51cb99c
LJ		 1088 assigned-clocks = <&clk IMX8MN_CLK_USB_BUS>;
1089 assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_500M>;
78e80c4b 1090 phys = <&usbphynop1>;
6c3debcb 1091 fsl,usbmisc = <&usbmisc1 0>;
ee895139 1092 power-domains = <&pgc_hsiomix>;
6c3debcb
AH		 1093 status = "disabled";
1094 };
1095
1096 usbmisc1: usbmisc@32e40200 {
1097 compatible = "fsl,imx8mn-usbmisc", "fsl,imx7d-usbmisc";
1098 #index-cells = <1>;
1099 reg = <0x32e40200 0x200>;
1100 };
6c3debcb
AH		 1101 };
1102
1103 dma_apbh: dma-controller@33000000 {
1104 compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh";
1105 reg = <0x33000000 0x2000>;
1106 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
1107 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
1108 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
1109 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1110 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
1111 #dma-cells = <1>;
1112 dma-channels = <4>;
1113 clocks = <&clk IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK>;
1114 };
1115
1116 gpmi: nand-controller@33002000 {
1117 compatible = "fsl,imx8mn-gpmi-nand", "fsl,imx7d-gpmi-nand";
1118 #address-cells = <1>;
5468e93b 1119 #size-cells = <0>;
6c3debcb
AH		 1120 reg = <0x33002000 0x2000>, <0x33004000 0x4000>;
1121 reg-names = "gpmi-nand", "bch";
1122 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1123 interrupt-names = "bch";
1124 clocks = <&clk IMX8MN_CLK_NAND_ROOT>,
1125 <&clk IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK>;
1126 clock-names = "gpmi_io", "gpmi_bch_apb";
1127 dmas = <&dma_apbh 0>;
1128 dma-names = "rx-tx";
1129 status = "disabled";
1130 };
1131
9a0f3b15
AF		 1132 gpu: gpu@38000000 {
1133 compatible = "vivante,gc";
1134 reg = <0x38000000 0x8000>;
1135 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
1136 clocks = <&clk IMX8MN_CLK_GPU_AHB>,
1137 <&clk IMX8MN_CLK_GPU_BUS_ROOT>,
1138 <&clk IMX8MN_CLK_GPU_CORE_ROOT>,
1139 <&clk IMX8MN_CLK_GPU_SHADER>;
1140 clock-names = "reg", "bus", "core", "shader";
1141 assigned-clocks = <&clk IMX8MN_CLK_GPU_CORE>,
1142 <&clk IMX8MN_CLK_GPU_SHADER>,
1143 <&clk IMX8MN_CLK_GPU_AXI>,
1144 <&clk IMX8MN_CLK_GPU_AHB>,
1145 <&clk IMX8MN_GPU_PLL>;
1146 assigned-clock-parents = <&clk IMX8MN_GPU_PLL_OUT>,
1147 <&clk IMX8MN_GPU_PLL_OUT>,
1148 <&clk IMX8MN_SYS_PLL1_800M>,
1149 <&clk IMX8MN_SYS_PLL1_800M>;
1150 assigned-clock-rates = <400000000>,
1151 <400000000>,
1152 <800000000>,
1153 <400000000>,
1154 <1200000000>;
1155 power-domains = <&pgc_gpumix>;
1156 };
1157
6c3debcb
AH		 1158 gic: interrupt-controller@38800000 {
1159 compatible = "arm,gic-v3";
1160 reg = <0x38800000 0x10000>,
1161 <0x38880000 0xc0000>;
1162 #interrupt-cells = <3>;
1163 interrupt-controller;
1164 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
1165 };
2d8e0747 1166
0376f6ec
LC		 1167 ddrc: memory-controller@3d400000 {
1168 compatible = "fsl,imx8mn-ddrc", "fsl,imx8m-ddrc";
1169 reg = <0x3d400000 0x400000>;
1170 clock-names = "core", "pll", "alt", "apb";
1171 clocks = <&clk IMX8MN_CLK_DRAM_CORE>,
1172 <&clk IMX8MN_DRAM_PLL>,
1173 <&clk IMX8MN_CLK_DRAM_ALT>,
1174 <&clk IMX8MN_CLK_DRAM_APB>;
1175 };
1176
2d8e0747
JZ		 1177 ddr-pmu@3d800000 {
1178 compatible = "fsl,imx8mn-ddr-pmu", "fsl,imx8m-ddr-pmu";
1179 reg = <0x3d800000 0x400000>;
1180 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1181 };
6c3debcb
AH		 1182 };
1183
1184 usbphynop1: usbphynop1 {
78e80c4b 1185 #phy-cells = <0>;
6c3debcb
AH		 1186 compatible = "usb-nop-xceiv";
1187 clocks = <&clk IMX8MN_CLK_USB_PHY_REF>;
1188 assigned-clocks = <&clk IMX8MN_CLK_USB_PHY_REF>;
1189 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_100M>;
1190 clock-names = "main_clk";
ee895139 1191 power-domains = <&pgc_otg1>;
6c3debcb 1192 };
6c3debcb 1193};
Linux 6.x block layer and io_uring tree(s)