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arm64: dts: imx8mn: Add "fsl,imx8mq-src" as src's fallback compatible
[linux-2.6-block.git] / arch / arm64 / boot / dts / freescale / imx8mn.dtsi
CommitLineData
6c3debcb
AH		 1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2019 NXP
4 */
5
6#include <dt-bindings/clock/imx8mn-clock.h>
7#include <dt-bindings/gpio/gpio.h>
8#include <dt-bindings/input/input.h>
9#include <dt-bindings/interrupt-controller/arm-gic.h>
10
11#include "imx8mn-pinfunc.h"
12
13/ {
14 compatible = "fsl,imx8mn";
15 interrupt-parent = <&gic>;
16 #address-cells = <2>;
17 #size-cells = <2>;
18
19 aliases {
20 ethernet0 = &fec1;
21 gpio0 = &gpio1;
22 gpio1 = &gpio2;
23 gpio2 = &gpio3;
24 gpio3 = &gpio4;
25 gpio4 = &gpio5;
26 i2c0 = &i2c1;
27 i2c1 = &i2c2;
28 i2c2 = &i2c3;
29 i2c3 = &i2c4;
30 mmc0 = &usdhc1;
31 mmc1 = &usdhc2;
32 mmc2 = &usdhc3;
33 serial0 = &uart1;
34 serial1 = &uart2;
35 serial2 = &uart3;
36 serial3 = &uart4;
37 spi0 = &ecspi1;
38 spi1 = &ecspi2;
39 spi2 = &ecspi3;
40 };
41
42 cpus {
43 #address-cells = <1>;
44 #size-cells = <0>;
45
46 A53_0: cpu@0 {
47 device_type = "cpu";
48 compatible = "arm,cortex-a53";
49 reg = <0x0>;
50 clock-latency = <61036>;
51 clocks = <&clk IMX8MN_CLK_ARM>;
52 enable-method = "psci";
53 next-level-cache = <&A53_L2>;
01c49314
AH		 54 operating-points-v2 = <&a53_opp_table>;
55 nvmem-cells = <&cpu_speed_grade>;
56 nvmem-cell-names = "speed_grade";
6c3debcb
AH		 57 };
58
59 A53_1: cpu@1 {
60 device_type = "cpu";
61 compatible = "arm,cortex-a53";
62 reg = <0x1>;
63 clock-latency = <61036>;
64 clocks = <&clk IMX8MN_CLK_ARM>;
65 enable-method = "psci";
66 next-level-cache = <&A53_L2>;
01c49314 67 operating-points-v2 = <&a53_opp_table>;
6c3debcb
AH		 68 };
69
70 A53_2: cpu@2 {
71 device_type = "cpu";
72 compatible = "arm,cortex-a53";
73 reg = <0x2>;
74 clock-latency = <61036>;
75 clocks = <&clk IMX8MN_CLK_ARM>;
76 enable-method = "psci";
77 next-level-cache = <&A53_L2>;
01c49314 78 operating-points-v2 = <&a53_opp_table>;
6c3debcb
AH		 79 };
80
81 A53_3: cpu@3 {
82 device_type = "cpu";
83 compatible = "arm,cortex-a53";
84 reg = <0x3>;
85 clock-latency = <61036>;
86 clocks = <&clk IMX8MN_CLK_ARM>;
87 enable-method = "psci";
88 next-level-cache = <&A53_L2>;
01c49314 89 operating-points-v2 = <&a53_opp_table>;
6c3debcb
AH		 90 };
91
92 A53_L2: l2-cache0 {
93 compatible = "cache";
94 };
95 };
96
01c49314
AH		 97 a53_opp_table: opp-table {
98 compatible = "operating-points-v2";
99 opp-shared;
100
101 opp-1200000000 {
102 opp-hz = /bits/ 64 <1200000000>;
103 opp-microvolt = <850000>;
104 opp-supported-hw = <0xb00>, <0x7>;
105 clock-latency-ns = <150000>;
106 opp-suspend;
107 };
108
109 opp-1400000000 {
110 opp-hz = /bits/ 64 <1400000000>;
111 opp-microvolt = <950000>;
112 opp-supported-hw = <0x300>, <0x7>;
113 clock-latency-ns = <150000>;
114 opp-suspend;
115 };
116
117 opp-1500000000 {
118 opp-hz = /bits/ 64 <1500000000>;
119 opp-microvolt = <1000000>;
120 opp-supported-hw = <0x100>, <0x3>;
121 clock-latency-ns = <150000>;
122 opp-suspend;
123 };
124 };
125
6c3debcb
AH		 126 memory@40000000 {
127 device_type = "memory";
128 reg = <0x0 0x40000000 0 0x80000000>;
129 };
130
131 osc_32k: clock-osc-32k {
132 compatible = "fixed-clock";
133 #clock-cells = <0>;
134 clock-frequency = <32768>;
135 clock-output-names = "osc_32k";
136 };
137
138 osc_24m: clock-osc-24m {
139 compatible = "fixed-clock";
140 #clock-cells = <0>;
141 clock-frequency = <24000000>;
142 clock-output-names = "osc_24m";
143 };
144
145 clk_ext1: clock-ext1 {
146 compatible = "fixed-clock";
147 #clock-cells = <0>;
148 clock-frequency = <133000000>;
149 clock-output-names = "clk_ext1";
150 };
151
152 clk_ext2: clock-ext2 {
153 compatible = "fixed-clock";
154 #clock-cells = <0>;
155 clock-frequency = <133000000>;
156 clock-output-names = "clk_ext2";
157 };
158
159 clk_ext3: clock-ext3 {
160 compatible = "fixed-clock";
161 #clock-cells = <0>;
162 clock-frequency = <133000000>;
163 clock-output-names = "clk_ext3";
164 };
165
166 clk_ext4: clock-ext4 {
167 compatible = "fixed-clock";
168 #clock-cells = <0>;
169 clock-frequency= <133000000>;
170 clock-output-names = "clk_ext4";
171 };
172
173 psci {
174 compatible = "arm,psci-1.0";
175 method = "smc";
176 };
177
178 timer {
179 compatible = "arm,armv8-timer";
180 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
181 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
182 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
183 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
184 clock-frequency = <8000000>;
185 arm,no-tick-in-suspend;
186 };
187
188 soc@0 {
189 compatible = "simple-bus";
190 #address-cells = <1>;
191 #size-cells = <1>;
192 ranges = <0x0 0x0 0x0 0x3e000000>;
193
194 aips1: bus@30000000 {
195 compatible = "fsl,aips-bus", "simple-bus";
196 reg = <0x30000000 0x400000>;
197 #address-cells = <1>;
198 #size-cells = <1>;
199 ranges;
200
201 gpio1: gpio@30200000 {
202 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
203 reg = <0x30200000 0x10000>;
204 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
205 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
206 clocks = <&clk IMX8MN_CLK_GPIO1_ROOT>;
207 gpio-controller;
208 #gpio-cells = <2>;
209 interrupt-controller;
210 #interrupt-cells = <2>;
ee8696be 211 gpio-ranges = <&iomuxc 0 10 30>;
6c3debcb
AH		 212 };
213
214 gpio2: gpio@30210000 {
215 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
216 reg = <0x30210000 0x10000>;
217 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
218 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
219 clocks = <&clk IMX8MN_CLK_GPIO2_ROOT>;
220 gpio-controller;
221 #gpio-cells = <2>;
222 interrupt-controller;
223 #interrupt-cells = <2>;
ee8696be 224 gpio-ranges = <&iomuxc 0 40 21>;
6c3debcb
AH		 225 };
226
227 gpio3: gpio@30220000 {
228 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
229 reg = <0x30220000 0x10000>;
230 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
231 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
232 clocks = <&clk IMX8MN_CLK_GPIO3_ROOT>;
233 gpio-controller;
234 #gpio-cells = <2>;
235 interrupt-controller;
236 #interrupt-cells = <2>;
ee8696be 237 gpio-ranges = <&iomuxc 0 61 26>;
6c3debcb
AH		 238 };
239
240 gpio4: gpio@30230000 {
241 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
242 reg = <0x30230000 0x10000>;
243 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
244 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
245 clocks = <&clk IMX8MN_CLK_GPIO4_ROOT>;
246 gpio-controller;
247 #gpio-cells = <2>;
248 interrupt-controller;
249 #interrupt-cells = <2>;
ee8696be 250 gpio-ranges = <&iomuxc 21 108 11>;
6c3debcb
AH		 251 };
252
253 gpio5: gpio@30240000 {
254 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
255 reg = <0x30240000 0x10000>;
256 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
257 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
258 clocks = <&clk IMX8MN_CLK_GPIO5_ROOT>;
259 gpio-controller;
260 #gpio-cells = <2>;
261 interrupt-controller;
262 #interrupt-cells = <2>;
ee8696be 263 gpio-ranges = <&iomuxc 0 119 30>;
6c3debcb
AH		 264 };
265
266 wdog1: watchdog@30280000 {
267 compatible = "fsl,imx8mn-wdt", "fsl,imx21-wdt";
268 reg = <0x30280000 0x10000>;
269 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
270 clocks = <&clk IMX8MN_CLK_WDOG1_ROOT>;
271 status = "disabled";
272 };
273
274 wdog2: watchdog@30290000 {
275 compatible = "fsl,imx8mn-wdt", "fsl,imx21-wdt";
276 reg = <0x30290000 0x10000>;
277 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
278 clocks = <&clk IMX8MN_CLK_WDOG2_ROOT>;
279 status = "disabled";
280 };
281
282 wdog3: watchdog@302a0000 {
283 compatible = "fsl,imx8mn-wdt", "fsl,imx21-wdt";
284 reg = <0x302a0000 0x10000>;
285 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
286 clocks = <&clk IMX8MN_CLK_WDOG3_ROOT>;
287 status = "disabled";
288 };
289
290 sdma3: dma-controller@302b0000 {
291 compatible = "fsl,imx8mn-sdma", "fsl,imx7d-sdma";
292 reg = <0x302b0000 0x10000>;
293 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
294 clocks = <&clk IMX8MN_CLK_SDMA3_ROOT>,
295 <&clk IMX8MN_CLK_SDMA3_ROOT>;
296 clock-names = "ipg", "ahb";
297 #dma-cells = <3>;
298 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
299 };
300
301 sdma2: dma-controller@302c0000 {
302 compatible = "fsl,imx8mn-sdma", "fsl,imx7d-sdma";
303 reg = <0x302c0000 0x10000>;
304 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
305 clocks = <&clk IMX8MN_CLK_SDMA2_ROOT>,
306 <&clk IMX8MN_CLK_SDMA2_ROOT>;
307 clock-names = "ipg", "ahb";
308 #dma-cells = <3>;
309 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
310 };
311
312 iomuxc: pinctrl@30330000 {
313 compatible = "fsl,imx8mn-iomuxc";
314 reg = <0x30330000 0x10000>;
315 };
316
317 gpr: iomuxc-gpr@30340000 {
318 compatible = "fsl,imx8mn-iomuxc-gpr", "syscon";
319 reg = <0x30340000 0x10000>;
320 };
321
322 ocotp: ocotp-ctrl@30350000 {
323 compatible = "fsl,imx8mn-ocotp", "fsl,imx7d-ocotp", "syscon";
324 reg = <0x30350000 0x10000>;
325 clocks = <&clk IMX8MN_CLK_OCOTP_ROOT>;
01c49314
AH		 326 #address-cells = <1>;
327 #size-cells = <1>;
328
329 cpu_speed_grade: speed-grade@10 {
330 reg = <0x10 4>;
331 };
6c3debcb
AH		 332 };
333
334 anatop: anatop@30360000 {
335 compatible = "fsl,imx8mn-anatop", "fsl,imx8mm-anatop",
336 "syscon", "simple-bus";
337 reg = <0x30360000 0x10000>;
338 };
339
340 snvs: snvs@30370000 {
341 compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd";
342 reg = <0x30370000 0x10000>;
343
344 snvs_rtc: snvs-rtc-lp {
345 compatible = "fsl,sec-v4.0-mon-rtc-lp";
346 regmap = <&snvs>;
347 offset = <0x34>;
348 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
349 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
350 clock-names = "snvs-rtc";
351 };
352
353 snvs_pwrkey: snvs-powerkey {
354 compatible = "fsl,sec-v4.0-pwrkey";
355 regmap = <&snvs>;
356 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
357 linux,keycode = <KEY_POWER>;
358 wakeup-source;
359 status = "disabled";
360 };
361 };
362
363 clk: clock-controller@30380000 {
364 compatible = "fsl,imx8mn-ccm";
365 reg = <0x30380000 0x10000>;
366 #clock-cells = <1>;
367 clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>,
368 <&clk_ext3>, <&clk_ext4>;
369 clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
370 "clk_ext3", "clk_ext4";
371 };
372
373 src: reset-controller@30390000 {
23b80c20 374 compatible = "fsl,imx8mn-src", "fsl,imx8mq-src", "syscon";
6c3debcb
AH		 375 reg = <0x30390000 0x10000>;
376 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
377 #reset-cells = <1>;
378 };
379 };
380
381 aips2: bus@30400000 {
382 compatible = "fsl,aips-bus", "simple-bus";
383 reg = <0x30400000 0x400000>;
384 #address-cells = <1>;
385 #size-cells = <1>;
386 ranges;
387
388 pwm1: pwm@30660000 {
389 compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm";
390 reg = <0x30660000 0x10000>;
391 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
392 clocks = <&clk IMX8MN_CLK_PWM1_ROOT>,
393 <&clk IMX8MN_CLK_PWM1_ROOT>;
394 clock-names = "ipg", "per";
395 #pwm-cells = <2>;
396 status = "disabled";
397 };
398
399 pwm2: pwm@30670000 {
400 compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm";
401 reg = <0x30670000 0x10000>;
402 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
403 clocks = <&clk IMX8MN_CLK_PWM2_ROOT>,
404 <&clk IMX8MN_CLK_PWM2_ROOT>;
405 clock-names = "ipg", "per";
406 #pwm-cells = <2>;
407 status = "disabled";
408 };
409
410 pwm3: pwm@30680000 {
411 compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm";
412 reg = <0x30680000 0x10000>;
413 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
414 clocks = <&clk IMX8MN_CLK_PWM3_ROOT>,
415 <&clk IMX8MN_CLK_PWM3_ROOT>;
416 clock-names = "ipg", "per";
417 #pwm-cells = <2>;
418 status = "disabled";
419 };
420
421 pwm4: pwm@30690000 {
422 compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm";
423 reg = <0x30690000 0x10000>;
424 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
425 clocks = <&clk IMX8MN_CLK_PWM4_ROOT>,
426 <&clk IMX8MN_CLK_PWM4_ROOT>;
427 clock-names = "ipg", "per";
428 #pwm-cells = <2>;
429 status = "disabled";
430 };
431 };
432
433 aips3: bus@30800000 {
434 compatible = "fsl,aips-bus", "simple-bus";
435 reg = <0x30800000 0x400000>;
436 #address-cells = <1>;
437 #size-cells = <1>;
438 ranges;
439
440 ecspi1: spi@30820000 {
441 compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi";
442 #address-cells = <1>;
443 #size-cells = <0>;
444 reg = <0x30820000 0x10000>;
445 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
446 clocks = <&clk IMX8MN_CLK_ECSPI1_ROOT>,
447 <&clk IMX8MN_CLK_ECSPI1_ROOT>;
448 clock-names = "ipg", "per";
449 dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
450 dma-names = "rx", "tx";
451 status = "disabled";
452 };
453
454 ecspi2: spi@30830000 {
455 compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi";
456 #address-cells = <1>;
457 #size-cells = <0>;
458 reg = <0x30830000 0x10000>;
459 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
460 clocks = <&clk IMX8MN_CLK_ECSPI2_ROOT>,
461 <&clk IMX8MN_CLK_ECSPI2_ROOT>;
462 clock-names = "ipg", "per";
463 dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;
464 dma-names = "rx", "tx";
465 status = "disabled";
466 };
467
468 ecspi3: spi@30840000 {
469 compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi";
470 #address-cells = <1>;
471 #size-cells = <0>;
472 reg = <0x30840000 0x10000>;
473 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
474 clocks = <&clk IMX8MN_CLK_ECSPI3_ROOT>,
475 <&clk IMX8MN_CLK_ECSPI3_ROOT>;
476 clock-names = "ipg", "per";
477 dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;
478 dma-names = "rx", "tx";
479 status = "disabled";
480 };
481
482 uart1: serial@30860000 {
483 compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
484 reg = <0x30860000 0x10000>;
485 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
486 clocks = <&clk IMX8MN_CLK_UART1_ROOT>,
487 <&clk IMX8MN_CLK_UART1_ROOT>;
488 clock-names = "ipg", "per";
489 dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;
490 dma-names = "rx", "tx";
491 status = "disabled";
492 };
493
494 uart3: serial@30880000 {
495 compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
496 reg = <0x30880000 0x10000>;
497 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
498 clocks = <&clk IMX8MN_CLK_UART3_ROOT>,
499 <&clk IMX8MN_CLK_UART3_ROOT>;
500 clock-names = "ipg", "per";
501 dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;
502 dma-names = "rx", "tx";
503 status = "disabled";
504 };
505
506 uart2: serial@30890000 {
507 compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
508 reg = <0x30890000 0x10000>;
509 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
510 clocks = <&clk IMX8MN_CLK_UART2_ROOT>,
511 <&clk IMX8MN_CLK_UART2_ROOT>;
512 clock-names = "ipg", "per";
513 status = "disabled";
514 };
515
516 i2c1: i2c@30a20000 {
517 compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c";
518 #address-cells = <1>;
519 #size-cells = <0>;
520 reg = <0x30a20000 0x10000>;
521 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
522 clocks = <&clk IMX8MN_CLK_I2C1_ROOT>;
523 status = "disabled";
524 };
525
526 i2c2: i2c@30a30000 {
527 compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c";
528 #address-cells = <1>;
529 #size-cells = <0>;
530 reg = <0x30a30000 0x10000>;
531 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
532 clocks = <&clk IMX8MN_CLK_I2C2_ROOT>;
533 status = "disabled";
534 };
535
536 i2c3: i2c@30a40000 {
537 #address-cells = <1>;
538 #size-cells = <0>;
539 compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c";
540 reg = <0x30a40000 0x10000>;
541 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
542 clocks = <&clk IMX8MN_CLK_I2C3_ROOT>;
543 status = "disabled";
544 };
545
546 i2c4: i2c@30a50000 {
547 compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c";
548 #address-cells = <1>;
549 #size-cells = <0>;
550 reg = <0x30a50000 0x10000>;
551 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
552 clocks = <&clk IMX8MN_CLK_I2C4_ROOT>;
553 status = "disabled";
554 };
555
556 uart4: serial@30a60000 {
557 compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
558 reg = <0x30a60000 0x10000>;
559 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
560 clocks = <&clk IMX8MN_CLK_UART4_ROOT>,
561 <&clk IMX8MN_CLK_UART4_ROOT>;
562 clock-names = "ipg", "per";
563 dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>;
564 dma-names = "rx", "tx";
565 status = "disabled";
566 };
567
568 usdhc1: mmc@30b40000 {
569 compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc";
570 reg = <0x30b40000 0x10000>;
571 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
572 clocks = <&clk IMX8MN_CLK_DUMMY>,
573 <&clk IMX8MN_CLK_NAND_USDHC_BUS>,
574 <&clk IMX8MN_CLK_USDHC1_ROOT>;
575 clock-names = "ipg", "ahb", "per";
576 assigned-clocks = <&clk IMX8MN_CLK_USDHC1>;
577 assigned-clock-rates = <400000000>;
578 fsl,tuning-start-tap = <20>;
579 fsl,tuning-step= <2>;
580 bus-width = <4>;
581 status = "disabled";
582 };
583
584 usdhc2: mmc@30b50000 {
585 compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc";
586 reg = <0x30b50000 0x10000>;
587 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
588 clocks = <&clk IMX8MN_CLK_DUMMY>,
589 <&clk IMX8MN_CLK_NAND_USDHC_BUS>,
590 <&clk IMX8MN_CLK_USDHC2_ROOT>;
591 clock-names = "ipg", "ahb", "per";
592 fsl,tuning-start-tap = <20>;
593 fsl,tuning-step= <2>;
594 bus-width = <4>;
595 status = "disabled";
596 };
597
598 usdhc3: mmc@30b60000 {
599 compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc";
600 reg = <0x30b60000 0x10000>;
601 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
602 clocks = <&clk IMX8MN_CLK_DUMMY>,
603 <&clk IMX8MN_CLK_NAND_USDHC_BUS>,
604 <&clk IMX8MN_CLK_USDHC3_ROOT>;
605 clock-names = "ipg", "ahb", "per";
606 assigned-clocks = <&clk IMX8MN_CLK_USDHC3_ROOT>;
607 assigned-clock-rates = <400000000>;
608 fsl,tuning-start-tap = <20>;
609 fsl,tuning-step= <2>;
610 bus-width = <4>;
611 status = "disabled";
612 };
613
614 sdma1: dma-controller@30bd0000 {
615 compatible = "fsl,imx8mn-sdma", "fsl,imx7d-sdma";
616 reg = <0x30bd0000 0x10000>;
617 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
618 clocks = <&clk IMX8MN_CLK_SDMA1_ROOT>,
619 <&clk IMX8MN_CLK_SDMA1_ROOT>;
620 clock-names = "ipg", "ahb";
621 #dma-cells = <3>;
622 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
623 };
624
625 fec1: ethernet@30be0000 {
626 compatible = "fsl,imx8mn-fec", "fsl,imx6sx-fec";
627 reg = <0x30be0000 0x10000>;
628 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
629 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
630 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
631 clocks = <&clk IMX8MN_CLK_ENET1_ROOT>,
632 <&clk IMX8MN_CLK_ENET1_ROOT>,
633 <&clk IMX8MN_CLK_ENET_TIMER>,
634 <&clk IMX8MN_CLK_ENET_REF>,
635 <&clk IMX8MN_CLK_ENET_PHY_REF>;
636 clock-names = "ipg", "ahb", "ptp",
637 "enet_clk_ref", "enet_out";
638 assigned-clocks = <&clk IMX8MN_CLK_ENET_AXI>,
639 <&clk IMX8MN_CLK_ENET_TIMER>,
640 <&clk IMX8MN_CLK_ENET_REF>,
641 <&clk IMX8MN_CLK_ENET_TIMER>;
642 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_266M>,
643 <&clk IMX8MN_SYS_PLL2_100M>,
644 <&clk IMX8MN_SYS_PLL2_125M>;
645 assigned-clock-rates = <0>, <0>, <125000000>, <100000000>;
646 fsl,num-tx-queues = <3>;
647 fsl,num-rx-queues = <3>;
648 status = "disabled";
649 };
650
651 };
652
653 aips4: bus@32c00000 {
654 compatible = "fsl,aips-bus", "simple-bus";
655 reg = <0x32c00000 0x400000>;
656 #address-cells = <1>;
657 #size-cells = <1>;
658 ranges;
659
660 usbotg1: usb@32e40000 {
661 compatible = "fsl,imx8mn-usb", "fsl,imx7d-usb";
662 reg = <0x32e40000 0x200>;
663 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
664 clocks = <&clk IMX8MN_CLK_USB1_CTRL_ROOT>;
665 clock-names = "usb1_ctrl_root_clk";
666 assigned-clocks = <&clk IMX8MN_CLK_USB_BUS>,
667 <&clk IMX8MN_CLK_USB_CORE_REF>;
668 assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_500M>,
669 <&clk IMX8MN_SYS_PLL1_100M>;
670 fsl,usbphy = <&usbphynop1>;
671 fsl,usbmisc = <&usbmisc1 0>;
672 status = "disabled";
673 };
674
675 usbmisc1: usbmisc@32e40200 {
676 compatible = "fsl,imx8mn-usbmisc", "fsl,imx7d-usbmisc";
677 #index-cells = <1>;
678 reg = <0x32e40200 0x200>;
679 };
680
681 usbotg2: usb@32e50000 {
682 compatible = "fsl,imx8mn-usb", "fsl,imx7d-usb";
683 reg = <0x32e50000 0x200>;
684 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
685 clocks = <&clk IMX8MN_CLK_USB1_CTRL_ROOT>;
686 clock-names = "usb1_ctrl_root_clk";
687 assigned-clocks = <&clk IMX8MN_CLK_USB_BUS>,
688 <&clk IMX8MN_CLK_USB_CORE_REF>;
689 assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_500M>,
690 <&clk IMX8MN_SYS_PLL1_100M>;
691 fsl,usbphy = <&usbphynop2>;
692 fsl,usbmisc = <&usbmisc2 0>;
693 status = "disabled";
694 };
695
696 usbmisc2: usbmisc@32e50200 {
697 compatible = "fsl,imx8mn-usbmisc", "fsl,imx7d-usbmisc";
698 #index-cells = <1>;
699 reg = <0x32e50200 0x200>;
700 };
701
702 };
703
704 dma_apbh: dma-controller@33000000 {
705 compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh";
706 reg = <0x33000000 0x2000>;
707 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
708 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
709 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
710 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
711 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
712 #dma-cells = <1>;
713 dma-channels = <4>;
714 clocks = <&clk IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK>;
715 };
716
717 gpmi: nand-controller@33002000 {
718 compatible = "fsl,imx8mn-gpmi-nand", "fsl,imx7d-gpmi-nand";
719 #address-cells = <1>;
720 #size-cells = <1>;
721 reg = <0x33002000 0x2000>, <0x33004000 0x4000>;
722 reg-names = "gpmi-nand", "bch";
723 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
724 interrupt-names = "bch";
725 clocks = <&clk IMX8MN_CLK_NAND_ROOT>,
726 <&clk IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK>;
727 clock-names = "gpmi_io", "gpmi_bch_apb";
728 dmas = <&dma_apbh 0>;
729 dma-names = "rx-tx";
730 status = "disabled";
731 };
732
733 gic: interrupt-controller@38800000 {
734 compatible = "arm,gic-v3";
735 reg = <0x38800000 0x10000>,
736 <0x38880000 0xc0000>;
737 #interrupt-cells = <3>;
738 interrupt-controller;
739 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
740 };
741 };
742
743 usbphynop1: usbphynop1 {
744 compatible = "usb-nop-xceiv";
745 clocks = <&clk IMX8MN_CLK_USB_PHY_REF>;
746 assigned-clocks = <&clk IMX8MN_CLK_USB_PHY_REF>;
747 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_100M>;
748 clock-names = "main_clk";
749 };
750
751 usbphynop2: usbphynop2 {
752 compatible = "usb-nop-xceiv";
753 clocks = <&clk IMX8MN_CLK_USB_PHY_REF>;
754 assigned-clocks = <&clk IMX8MN_CLK_USB_PHY_REF>;
755 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_100M>;
756 clock-names = "main_clk";
757 };
758};
Linux 6.x block layer and io_uring tree(s)