projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
arm64: dts: imx8mn-evk: add two parameters for samsung picophy tuning
[linux-2.6-block.git] / arch / arm64 / boot / dts / freescale / imx8mn.dtsi
CommitLineData
6c3debcb
AH		 1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2019 NXP
4 */
5
6#include <dt-bindings/clock/imx8mn-clock.h>
7#include <dt-bindings/gpio/gpio.h>
8#include <dt-bindings/input/input.h>
9#include <dt-bindings/interrupt-controller/arm-gic.h>
819779a9 10#include <dt-bindings/thermal/thermal.h>
6c3debcb
AH		 11
12#include "imx8mn-pinfunc.h"
13
14/ {
6c3debcb
AH		 15 interrupt-parent = <&gic>;
16 #address-cells = <2>;
17 #size-cells = <2>;
18
19 aliases {
20 ethernet0 = &fec1;
21 gpio0 = &gpio1;
22 gpio1 = &gpio2;
23 gpio2 = &gpio3;
24 gpio3 = &gpio4;
25 gpio4 = &gpio5;
26 i2c0 = &i2c1;
27 i2c1 = &i2c2;
28 i2c2 = &i2c3;
29 i2c3 = &i2c4;
30 mmc0 = &usdhc1;
31 mmc1 = &usdhc2;
32 mmc2 = &usdhc3;
33 serial0 = &uart1;
34 serial1 = &uart2;
35 serial2 = &uart3;
36 serial3 = &uart4;
37 spi0 = &ecspi1;
38 spi1 = &ecspi2;
39 spi2 = &ecspi3;
40 };
41
42 cpus {
43 #address-cells = <1>;
44 #size-cells = <0>;
45
df844a9a
AH		 46 idle-states {
47 entry-method = "psci";
48
49 cpu_pd_wait: cpu-pd-wait {
50 compatible = "arm,idle-state";
51 arm,psci-suspend-param = <0x0010033>;
52 local-timer-stop;
53 entry-latency-us = <1000>;
54 exit-latency-us = <700>;
55 min-residency-us = <2700>;
56 };
57 };
58
6c3debcb
AH		 59 A53_0: cpu@0 {
60 device_type = "cpu";
61 compatible = "arm,cortex-a53";
62 reg = <0x0>;
63 clock-latency = <61036>;
64 clocks = <&clk IMX8MN_CLK_ARM>;
65 enable-method = "psci";
66 next-level-cache = <&A53_L2>;
01c49314
AH		 67 operating-points-v2 = <&a53_opp_table>;
68 nvmem-cells = <&cpu_speed_grade>;
69 nvmem-cell-names = "speed_grade";
df844a9a 70 cpu-idle-states = <&cpu_pd_wait>;
819779a9 71 #cooling-cells = <2>;
6c3debcb
AH		 72 };
73
74 A53_1: cpu@1 {
75 device_type = "cpu";
76 compatible = "arm,cortex-a53";
77 reg = <0x1>;
78 clock-latency = <61036>;
79 clocks = <&clk IMX8MN_CLK_ARM>;
80 enable-method = "psci";
81 next-level-cache = <&A53_L2>;
01c49314 82 operating-points-v2 = <&a53_opp_table>;
df844a9a 83 cpu-idle-states = <&cpu_pd_wait>;
819779a9 84 #cooling-cells = <2>;
6c3debcb
AH		 85 };
86
87 A53_2: cpu@2 {
88 device_type = "cpu";
89 compatible = "arm,cortex-a53";
90 reg = <0x2>;
91 clock-latency = <61036>;
92 clocks = <&clk IMX8MN_CLK_ARM>;
93 enable-method = "psci";
94 next-level-cache = <&A53_L2>;
01c49314 95 operating-points-v2 = <&a53_opp_table>;
df844a9a 96 cpu-idle-states = <&cpu_pd_wait>;
819779a9 97 #cooling-cells = <2>;
6c3debcb
AH		 98 };
99
100 A53_3: cpu@3 {
101 device_type = "cpu";
102 compatible = "arm,cortex-a53";
103 reg = <0x3>;
104 clock-latency = <61036>;
105 clocks = <&clk IMX8MN_CLK_ARM>;
106 enable-method = "psci";
107 next-level-cache = <&A53_L2>;
01c49314 108 operating-points-v2 = <&a53_opp_table>;
df844a9a 109 cpu-idle-states = <&cpu_pd_wait>;
819779a9 110 #cooling-cells = <2>;
6c3debcb
AH		 111 };
112
113 A53_L2: l2-cache0 {
114 compatible = "cache";
115 };
116 };
117
01c49314
AH		 118 a53_opp_table: opp-table {
119 compatible = "operating-points-v2";
120 opp-shared;
121
122 opp-1200000000 {
123 opp-hz = /bits/ 64 <1200000000>;
8c30e7ca 124 opp-microvolt = <850000>;
01c49314
AH		 125 opp-supported-hw = <0xb00>, <0x7>;
126 clock-latency-ns = <150000>;
127 opp-suspend;
128 };
129
130 opp-1400000000 {
131 opp-hz = /bits/ 64 <1400000000>;
132 opp-microvolt = <950000>;
133 opp-supported-hw = <0x300>, <0x7>;
134 clock-latency-ns = <150000>;
135 opp-suspend;
136 };
137
138 opp-1500000000 {
139 opp-hz = /bits/ 64 <1500000000>;
140 opp-microvolt = <1000000>;
141 opp-supported-hw = <0x100>, <0x3>;
142 clock-latency-ns = <150000>;
143 opp-suspend;
144 };
145 };
146
6c3debcb
AH		 147 osc_32k: clock-osc-32k {
148 compatible = "fixed-clock";
149 #clock-cells = <0>;
150 clock-frequency = <32768>;
151 clock-output-names = "osc_32k";
152 };
153
154 osc_24m: clock-osc-24m {
155 compatible = "fixed-clock";
156 #clock-cells = <0>;
157 clock-frequency = <24000000>;
158 clock-output-names = "osc_24m";
159 };
160
161 clk_ext1: clock-ext1 {
162 compatible = "fixed-clock";
163 #clock-cells = <0>;
164 clock-frequency = <133000000>;
165 clock-output-names = "clk_ext1";
166 };
167
168 clk_ext2: clock-ext2 {
169 compatible = "fixed-clock";
170 #clock-cells = <0>;
171 clock-frequency = <133000000>;
172 clock-output-names = "clk_ext2";
173 };
174
175 clk_ext3: clock-ext3 {
176 compatible = "fixed-clock";
177 #clock-cells = <0>;
178 clock-frequency = <133000000>;
179 clock-output-names = "clk_ext3";
180 };
181
182 clk_ext4: clock-ext4 {
183 compatible = "fixed-clock";
184 #clock-cells = <0>;
185 clock-frequency= <133000000>;
186 clock-output-names = "clk_ext4";
187 };
188
189 psci {
190 compatible = "arm,psci-1.0";
191 method = "smc";
192 };
193
819779a9
AH		 194 thermal-zones {
195 cpu-thermal {
196 polling-delay-passive = <250>;
197 polling-delay = <2000>;
198 thermal-sensors = <&tmu>;
199 trips {
200 cpu_alert0: trip0 {
201 temperature = <85000>;
202 hysteresis = <2000>;
203 type = "passive";
204 };
205
206 cpu_crit0: trip1 {
207 temperature = <95000>;
208 hysteresis = <2000>;
209 type = "critical";
210 };
211 };
212
213 cooling-maps {
214 map0 {
215 trip = <&cpu_alert0>;
216 cooling-device =
217 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
218 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
219 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
220 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
221 };
222 };
223 };
224 };
225
6c3debcb
AH		 226 timer {
227 compatible = "arm,armv8-timer";
228 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
229 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
230 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
231 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
232 clock-frequency = <8000000>;
233 arm,no-tick-in-suspend;
234 };
235
236 soc@0 {
237 compatible = "simple-bus";
238 #address-cells = <1>;
239 #size-cells = <1>;
240 ranges = <0x0 0x0 0x0 0x3e000000>;
241
242 aips1: bus@30000000 {
dc3efc6f 243 compatible = "fsl,aips-bus", "simple-bus";
921a6845 244 reg = <0x30000000 0x400000>;
6c3debcb
AH		 245 #address-cells = <1>;
246 #size-cells = <1>;
247 ranges;
248
249 gpio1: gpio@30200000 {
250 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
251 reg = <0x30200000 0x10000>;
252 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
253 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
254 clocks = <&clk IMX8MN_CLK_GPIO1_ROOT>;
255 gpio-controller;
256 #gpio-cells = <2>;
257 interrupt-controller;
258 #interrupt-cells = <2>;
ee8696be 259 gpio-ranges = <&iomuxc 0 10 30>;
6c3debcb
AH		 260 };
261
262 gpio2: gpio@30210000 {
263 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
264 reg = <0x30210000 0x10000>;
265 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
266 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
267 clocks = <&clk IMX8MN_CLK_GPIO2_ROOT>;
268 gpio-controller;
269 #gpio-cells = <2>;
270 interrupt-controller;
271 #interrupt-cells = <2>;
ee8696be 272 gpio-ranges = <&iomuxc 0 40 21>;
6c3debcb
AH		 273 };
274
275 gpio3: gpio@30220000 {
276 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
277 reg = <0x30220000 0x10000>;
278 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
279 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
280 clocks = <&clk IMX8MN_CLK_GPIO3_ROOT>;
281 gpio-controller;
282 #gpio-cells = <2>;
283 interrupt-controller;
284 #interrupt-cells = <2>;
ee8696be 285 gpio-ranges = <&iomuxc 0 61 26>;
6c3debcb
AH		 286 };
287
288 gpio4: gpio@30230000 {
289 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
290 reg = <0x30230000 0x10000>;
291 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
292 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
293 clocks = <&clk IMX8MN_CLK_GPIO4_ROOT>;
294 gpio-controller;
295 #gpio-cells = <2>;
296 interrupt-controller;
297 #interrupt-cells = <2>;
ee8696be 298 gpio-ranges = <&iomuxc 21 108 11>;
6c3debcb
AH		 299 };
300
301 gpio5: gpio@30240000 {
302 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
303 reg = <0x30240000 0x10000>;
304 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
305 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
306 clocks = <&clk IMX8MN_CLK_GPIO5_ROOT>;
307 gpio-controller;
308 #gpio-cells = <2>;
309 interrupt-controller;
310 #interrupt-cells = <2>;
ee8696be 311 gpio-ranges = <&iomuxc 0 119 30>;
6c3debcb
AH		 312 };
313
819779a9
AH		 314 tmu: tmu@30260000 {
315 compatible = "fsl,imx8mn-tmu", "fsl,imx8mm-tmu";
316 reg = <0x30260000 0x10000>;
317 clocks = <&clk IMX8MN_CLK_TMU_ROOT>;
318 #thermal-sensor-cells = <0>;
319 };
320
6c3debcb
AH		 321 wdog1: watchdog@30280000 {
322 compatible = "fsl,imx8mn-wdt", "fsl,imx21-wdt";
323 reg = <0x30280000 0x10000>;
324 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
325 clocks = <&clk IMX8MN_CLK_WDOG1_ROOT>;
326 status = "disabled";
327 };
328
329 wdog2: watchdog@30290000 {
330 compatible = "fsl,imx8mn-wdt", "fsl,imx21-wdt";
331 reg = <0x30290000 0x10000>;
332 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
333 clocks = <&clk IMX8MN_CLK_WDOG2_ROOT>;
334 status = "disabled";
335 };
336
337 wdog3: watchdog@302a0000 {
338 compatible = "fsl,imx8mn-wdt", "fsl,imx21-wdt";
339 reg = <0x302a0000 0x10000>;
340 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
341 clocks = <&clk IMX8MN_CLK_WDOG3_ROOT>;
342 status = "disabled";
343 };
344
345 sdma3: dma-controller@302b0000 {
958c6014 346 compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma";
6c3debcb
AH		 347 reg = <0x302b0000 0x10000>;
348 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
349 clocks = <&clk IMX8MN_CLK_SDMA3_ROOT>,
350 <&clk IMX8MN_CLK_SDMA3_ROOT>;
351 clock-names = "ipg", "ahb";
352 #dma-cells = <3>;
353 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
354 };
355
356 sdma2: dma-controller@302c0000 {
958c6014 357 compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma";
6c3debcb
AH		 358 reg = <0x302c0000 0x10000>;
359 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
360 clocks = <&clk IMX8MN_CLK_SDMA2_ROOT>,
361 <&clk IMX8MN_CLK_SDMA2_ROOT>;
362 clock-names = "ipg", "ahb";
363 #dma-cells = <3>;
364 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
365 };
366
367 iomuxc: pinctrl@30330000 {
368 compatible = "fsl,imx8mn-iomuxc";
369 reg = <0x30330000 0x10000>;
370 };
371
372 gpr: iomuxc-gpr@30340000 {
373 compatible = "fsl,imx8mn-iomuxc-gpr", "syscon";
374 reg = <0x30340000 0x10000>;
375 };
376
12fa1078 377 ocotp: efuse@30350000 {
2bad8c48 378 compatible = "fsl,imx8mn-ocotp", "fsl,imx8mm-ocotp", "syscon";
6c3debcb
AH		 379 reg = <0x30350000 0x10000>;
380 clocks = <&clk IMX8MN_CLK_OCOTP_ROOT>;
01c49314
AH		 381 #address-cells = <1>;
382 #size-cells = <1>;
383
384 cpu_speed_grade: speed-grade@10 {
385 reg = <0x10 4>;
386 };
6c3debcb
AH		 387 };
388
389 anatop: anatop@30360000 {
390 compatible = "fsl,imx8mn-anatop", "fsl,imx8mm-anatop",
0f93eb28 391 "syscon";
6c3debcb
AH		 392 reg = <0x30360000 0x10000>;
393 };
394
395 snvs: snvs@30370000 {
396 compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd";
397 reg = <0x30370000 0x10000>;
398
399 snvs_rtc: snvs-rtc-lp {
400 compatible = "fsl,sec-v4.0-mon-rtc-lp";
401 regmap = <&snvs>;
402 offset = <0x34>;
403 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
404 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
42ef961b 405 clocks = <&clk IMX8MN_CLK_SNVS_ROOT>;
6c3debcb
AH		 406 clock-names = "snvs-rtc";
407 };
408
409 snvs_pwrkey: snvs-powerkey {
410 compatible = "fsl,sec-v4.0-pwrkey";
411 regmap = <&snvs>;
412 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
c2a2f446
AH		 413 clocks = <&clk IMX8MN_CLK_SNVS_ROOT>;
414 clock-names = "snvs-pwrkey";
6c3debcb
AH		 415 linux,keycode = <KEY_POWER>;
416 wakeup-source;
417 status = "disabled";
418 };
419 };
420
421 clk: clock-controller@30380000 {
422 compatible = "fsl,imx8mn-ccm";
423 reg = <0x30380000 0x10000>;
424 #clock-cells = <1>;
425 clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>,
426 <&clk_ext3>, <&clk_ext4>;
427 clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
428 "clk_ext3", "clk_ext4";
9e6337e6
PF		 429 assigned-clocks = <&clk IMX8MN_CLK_A53_SRC>,
430 <&clk IMX8MN_CLK_A53_CORE>,
431 <&clk IMX8MN_CLK_NOC>,
53458f86
PF		 432 <&clk IMX8MN_CLK_AUDIO_AHB>,
433 <&clk IMX8MN_CLK_IPG_AUDIO_ROOT>,
434 <&clk IMX8MN_SYS_PLL3>;
9e6337e6
PF		 435 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_800M>,
436 <&clk IMX8MN_ARM_PLL_OUT>,
437 <&clk IMX8MN_SYS_PLL3_OUT>,
53458f86 438 <&clk IMX8MN_SYS_PLL1_800M>;
9e6337e6 439 assigned-clock-rates = <0>, <0>, <0>,
53458f86
PF		 440 <400000000>,
441 <400000000>,
442 <600000000>;
6c3debcb
AH		 443 };
444
445 src: reset-controller@30390000 {
23b80c20 446 compatible = "fsl,imx8mn-src", "fsl,imx8mq-src", "syscon";
6c3debcb
AH		 447 reg = <0x30390000 0x10000>;
448 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
449 #reset-cells = <1>;
450 };
451 };
452
453 aips2: bus@30400000 {
dc3efc6f 454 compatible = "fsl,aips-bus", "simple-bus";
921a6845 455 reg = <0x30400000 0x400000>;
6c3debcb
AH		 456 #address-cells = <1>;
457 #size-cells = <1>;
458 ranges;
459
460 pwm1: pwm@30660000 {
461 compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm";
462 reg = <0x30660000 0x10000>;
463 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
464 clocks = <&clk IMX8MN_CLK_PWM1_ROOT>,
465 <&clk IMX8MN_CLK_PWM1_ROOT>;
466 clock-names = "ipg", "per";
467 #pwm-cells = <2>;
468 status = "disabled";
469 };
470
471 pwm2: pwm@30670000 {
472 compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm";
473 reg = <0x30670000 0x10000>;
474 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
475 clocks = <&clk IMX8MN_CLK_PWM2_ROOT>,
476 <&clk IMX8MN_CLK_PWM2_ROOT>;
477 clock-names = "ipg", "per";
478 #pwm-cells = <2>;
479 status = "disabled";
480 };
481
482 pwm3: pwm@30680000 {
483 compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm";
484 reg = <0x30680000 0x10000>;
485 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
486 clocks = <&clk IMX8MN_CLK_PWM3_ROOT>,
487 <&clk IMX8MN_CLK_PWM3_ROOT>;
488 clock-names = "ipg", "per";
489 #pwm-cells = <2>;
490 status = "disabled";
491 };
492
493 pwm4: pwm@30690000 {
494 compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm";
495 reg = <0x30690000 0x10000>;
496 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
497 clocks = <&clk IMX8MN_CLK_PWM4_ROOT>,
498 <&clk IMX8MN_CLK_PWM4_ROOT>;
499 clock-names = "ipg", "per";
500 #pwm-cells = <2>;
501 status = "disabled";
502 };
c4a21269
AH		 503
504 system_counter: timer@306a0000 {
505 compatible = "nxp,sysctr-timer";
506 reg = <0x306a0000 0x20000>;
507 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
508 clocks = <&osc_24m>;
509 clock-names = "per";
510 };
6c3debcb
AH		 511 };
512
513 aips3: bus@30800000 {
dc3efc6f 514 compatible = "fsl,aips-bus", "simple-bus";
921a6845 515 reg = <0x30800000 0x400000>;
6c3debcb
AH		 516 #address-cells = <1>;
517 #size-cells = <1>;
518 ranges;
519
520 ecspi1: spi@30820000 {
521 compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi";
522 #address-cells = <1>;
523 #size-cells = <0>;
524 reg = <0x30820000 0x10000>;
525 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
526 clocks = <&clk IMX8MN_CLK_ECSPI1_ROOT>,
527 <&clk IMX8MN_CLK_ECSPI1_ROOT>;
528 clock-names = "ipg", "per";
529 dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
530 dma-names = "rx", "tx";
531 status = "disabled";
532 };
533
534 ecspi2: spi@30830000 {
535 compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi";
536 #address-cells = <1>;
537 #size-cells = <0>;
538 reg = <0x30830000 0x10000>;
539 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
540 clocks = <&clk IMX8MN_CLK_ECSPI2_ROOT>,
541 <&clk IMX8MN_CLK_ECSPI2_ROOT>;
542 clock-names = "ipg", "per";
543 dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;
544 dma-names = "rx", "tx";
545 status = "disabled";
546 };
547
548 ecspi3: spi@30840000 {
549 compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi";
550 #address-cells = <1>;
551 #size-cells = <0>;
552 reg = <0x30840000 0x10000>;
553 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
554 clocks = <&clk IMX8MN_CLK_ECSPI3_ROOT>,
555 <&clk IMX8MN_CLK_ECSPI3_ROOT>;
556 clock-names = "ipg", "per";
557 dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;
558 dma-names = "rx", "tx";
559 status = "disabled";
560 };
561
562 uart1: serial@30860000 {
563 compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
564 reg = <0x30860000 0x10000>;
565 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
566 clocks = <&clk IMX8MN_CLK_UART1_ROOT>,
567 <&clk IMX8MN_CLK_UART1_ROOT>;
568 clock-names = "ipg", "per";
569 dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;
570 dma-names = "rx", "tx";
571 status = "disabled";
572 };
573
574 uart3: serial@30880000 {
575 compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
576 reg = <0x30880000 0x10000>;
577 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
578 clocks = <&clk IMX8MN_CLK_UART3_ROOT>,
579 <&clk IMX8MN_CLK_UART3_ROOT>;
580 clock-names = "ipg", "per";
581 dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;
582 dma-names = "rx", "tx";
583 status = "disabled";
584 };
585
586 uart2: serial@30890000 {
587 compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
588 reg = <0x30890000 0x10000>;
589 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
590 clocks = <&clk IMX8MN_CLK_UART2_ROOT>,
591 <&clk IMX8MN_CLK_UART2_ROOT>;
592 clock-names = "ipg", "per";
593 status = "disabled";
594 };
595
aad24175
HG		 596 crypto: crypto@30900000 {
597 compatible = "fsl,sec-v4.0";
598 #address-cells = <1>;
599 #size-cells = <1>;
600 reg = <0x30900000 0x40000>;
601 ranges = <0 0x30900000 0x40000>;
602 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
603 clocks = <&clk IMX8MN_CLK_AHB>,
604 <&clk IMX8MN_CLK_IPG_ROOT>;
605 clock-names = "aclk", "ipg";
606
f5ff5a21 607 sec_jr0: jr@1000 {
aad24175
HG		 608 compatible = "fsl,sec-v4.0-job-ring";
609 reg = <0x1000 0x1000>;
610 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
611 };
612
f5ff5a21 613 sec_jr1: jr@2000 {
aad24175
HG		 614 compatible = "fsl,sec-v4.0-job-ring";
615 reg = <0x2000 0x1000>;
616 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
617 };
618
f5ff5a21 619 sec_jr2: jr@3000 {
aad24175
HG		 620 compatible = "fsl,sec-v4.0-job-ring";
621 reg = <0x3000 0x1000>;
622 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
623 };
624 };
625
6c3debcb
AH		 626 i2c1: i2c@30a20000 {
627 compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c";
628 #address-cells = <1>;
629 #size-cells = <0>;
630 reg = <0x30a20000 0x10000>;
631 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
632 clocks = <&clk IMX8MN_CLK_I2C1_ROOT>;
633 status = "disabled";
634 };
635
636 i2c2: i2c@30a30000 {
637 compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c";
638 #address-cells = <1>;
639 #size-cells = <0>;
640 reg = <0x30a30000 0x10000>;
641 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
642 clocks = <&clk IMX8MN_CLK_I2C2_ROOT>;
643 status = "disabled";
644 };
645
646 i2c3: i2c@30a40000 {
647 #address-cells = <1>;
648 #size-cells = <0>;
649 compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c";
650 reg = <0x30a40000 0x10000>;
651 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
652 clocks = <&clk IMX8MN_CLK_I2C3_ROOT>;
653 status = "disabled";
654 };
655
656 i2c4: i2c@30a50000 {
657 compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c";
658 #address-cells = <1>;
659 #size-cells = <0>;
660 reg = <0x30a50000 0x10000>;
661 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
662 clocks = <&clk IMX8MN_CLK_I2C4_ROOT>;
663 status = "disabled";
664 };
665
666 uart4: serial@30a60000 {
667 compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
668 reg = <0x30a60000 0x10000>;
669 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
670 clocks = <&clk IMX8MN_CLK_UART4_ROOT>,
671 <&clk IMX8MN_CLK_UART4_ROOT>;
672 clock-names = "ipg", "per";
673 dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>;
674 dma-names = "rx", "tx";
675 status = "disabled";
676 };
677
bbfc59be
PF		 678 mu: mailbox@30aa0000 {
679 compatible = "fsl,imx8mn-mu", "fsl,imx6sx-mu";
680 reg = <0x30aa0000 0x10000>;
681 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
682 clocks = <&clk IMX8MN_CLK_MU_ROOT>;
683 #mbox-cells = <2>;
684 };
685
6c3debcb
AH		 686 usdhc1: mmc@30b40000 {
687 compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc";
688 reg = <0x30b40000 0x10000>;
689 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
ea65aba8 690 clocks = <&clk IMX8MN_CLK_IPG_ROOT>,
6c3debcb
AH		 691 <&clk IMX8MN_CLK_NAND_USDHC_BUS>,
692 <&clk IMX8MN_CLK_USDHC1_ROOT>;
693 clock-names = "ipg", "ahb", "per";
6c3debcb
AH		 694 fsl,tuning-start-tap = <20>;
695 fsl,tuning-step= <2>;
696 bus-width = <4>;
697 status = "disabled";
698 };
699
700 usdhc2: mmc@30b50000 {
701 compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc";
702 reg = <0x30b50000 0x10000>;
703 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
ea65aba8 704 clocks = <&clk IMX8MN_CLK_IPG_ROOT>,
6c3debcb
AH		 705 <&clk IMX8MN_CLK_NAND_USDHC_BUS>,
706 <&clk IMX8MN_CLK_USDHC2_ROOT>;
707 clock-names = "ipg", "ahb", "per";
708 fsl,tuning-start-tap = <20>;
709 fsl,tuning-step= <2>;
710 bus-width = <4>;
711 status = "disabled";
712 };
713
714 usdhc3: mmc@30b60000 {
715 compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc";
716 reg = <0x30b60000 0x10000>;
717 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
ea65aba8 718 clocks = <&clk IMX8MN_CLK_IPG_ROOT>,
6c3debcb
AH		 719 <&clk IMX8MN_CLK_NAND_USDHC_BUS>,
720 <&clk IMX8MN_CLK_USDHC3_ROOT>;
721 clock-names = "ipg", "ahb", "per";
6c3debcb
AH		 722 fsl,tuning-start-tap = <20>;
723 fsl,tuning-step= <2>;
724 bus-width = <4>;
725 status = "disabled";
726 };
727
728 sdma1: dma-controller@30bd0000 {
958c6014 729 compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma";
6c3debcb
AH		 730 reg = <0x30bd0000 0x10000>;
731 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
732 clocks = <&clk IMX8MN_CLK_SDMA1_ROOT>,
15ddc3e1 733 <&clk IMX8MN_CLK_AHB>;
6c3debcb
AH		 734 clock-names = "ipg", "ahb";
735 #dma-cells = <3>;
736 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
737 };
738
739 fec1: ethernet@30be0000 {
740 compatible = "fsl,imx8mn-fec", "fsl,imx6sx-fec";
741 reg = <0x30be0000 0x10000>;
742 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
743 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
744 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
745 clocks = <&clk IMX8MN_CLK_ENET1_ROOT>,
746 <&clk IMX8MN_CLK_ENET1_ROOT>,
747 <&clk IMX8MN_CLK_ENET_TIMER>,
748 <&clk IMX8MN_CLK_ENET_REF>,
749 <&clk IMX8MN_CLK_ENET_PHY_REF>;
750 clock-names = "ipg", "ahb", "ptp",
751 "enet_clk_ref", "enet_out";
752 assigned-clocks = <&clk IMX8MN_CLK_ENET_AXI>,
753 <&clk IMX8MN_CLK_ENET_TIMER>,
754 <&clk IMX8MN_CLK_ENET_REF>,
755 <&clk IMX8MN_CLK_ENET_TIMER>;
756 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_266M>,
757 <&clk IMX8MN_SYS_PLL2_100M>,
758 <&clk IMX8MN_SYS_PLL2_125M>;
759 assigned-clock-rates = <0>, <0>, <125000000>, <100000000>;
760 fsl,num-tx-queues = <3>;
761 fsl,num-rx-queues = <3>;
762 status = "disabled";
763 };
764
765 };
766
767 aips4: bus@32c00000 {
dc3efc6f 768 compatible = "fsl,aips-bus", "simple-bus";
921a6845 769 reg = <0x32c00000 0x400000>;
6c3debcb
AH		 770 #address-cells = <1>;
771 #size-cells = <1>;
772 ranges;
773
774 usbotg1: usb@32e40000 {
775 compatible = "fsl,imx8mn-usb", "fsl,imx7d-usb";
776 reg = <0x32e40000 0x200>;
777 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
778 clocks = <&clk IMX8MN_CLK_USB1_CTRL_ROOT>;
779 clock-names = "usb1_ctrl_root_clk";
d51cb99c
LJ		 780 assigned-clocks = <&clk IMX8MN_CLK_USB_BUS>;
781 assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_500M>;
6c3debcb
AH		 782 fsl,usbphy = <&usbphynop1>;
783 fsl,usbmisc = <&usbmisc1 0>;
784 status = "disabled";
785 };
786
787 usbmisc1: usbmisc@32e40200 {
788 compatible = "fsl,imx8mn-usbmisc", "fsl,imx7d-usbmisc";
789 #index-cells = <1>;
790 reg = <0x32e40200 0x200>;
791 };
792
793 usbotg2: usb@32e50000 {
794 compatible = "fsl,imx8mn-usb", "fsl,imx7d-usb";
795 reg = <0x32e50000 0x200>;
796 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
797 clocks = <&clk IMX8MN_CLK_USB1_CTRL_ROOT>;
798 clock-names = "usb1_ctrl_root_clk";
799 assigned-clocks = <&clk IMX8MN_CLK_USB_BUS>,
800 <&clk IMX8MN_CLK_USB_CORE_REF>;
801 assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_500M>,
802 <&clk IMX8MN_SYS_PLL1_100M>;
803 fsl,usbphy = <&usbphynop2>;
804 fsl,usbmisc = <&usbmisc2 0>;
805 status = "disabled";
806 };
807
808 usbmisc2: usbmisc@32e50200 {
809 compatible = "fsl,imx8mn-usbmisc", "fsl,imx7d-usbmisc";
810 #index-cells = <1>;
811 reg = <0x32e50200 0x200>;
812 };
813
814 };
815
816 dma_apbh: dma-controller@33000000 {
817 compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh";
818 reg = <0x33000000 0x2000>;
819 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
820 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
821 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
822 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
823 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
824 #dma-cells = <1>;
825 dma-channels = <4>;
826 clocks = <&clk IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK>;
827 };
828
829 gpmi: nand-controller@33002000 {
830 compatible = "fsl,imx8mn-gpmi-nand", "fsl,imx7d-gpmi-nand";
831 #address-cells = <1>;
832 #size-cells = <1>;
833 reg = <0x33002000 0x2000>, <0x33004000 0x4000>;
834 reg-names = "gpmi-nand", "bch";
835 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
836 interrupt-names = "bch";
837 clocks = <&clk IMX8MN_CLK_NAND_ROOT>,
838 <&clk IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK>;
839 clock-names = "gpmi_io", "gpmi_bch_apb";
840 dmas = <&dma_apbh 0>;
841 dma-names = "rx-tx";
842 status = "disabled";
843 };
844
845 gic: interrupt-controller@38800000 {
846 compatible = "arm,gic-v3";
847 reg = <0x38800000 0x10000>,
848 <0x38880000 0xc0000>;
849 #interrupt-cells = <3>;
850 interrupt-controller;
851 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
852 };
2d8e0747 853
0376f6ec
LC		 854 ddrc: memory-controller@3d400000 {
855 compatible = "fsl,imx8mn-ddrc", "fsl,imx8m-ddrc";
856 reg = <0x3d400000 0x400000>;
857 clock-names = "core", "pll", "alt", "apb";
858 clocks = <&clk IMX8MN_CLK_DRAM_CORE>,
859 <&clk IMX8MN_DRAM_PLL>,
860 <&clk IMX8MN_CLK_DRAM_ALT>,
861 <&clk IMX8MN_CLK_DRAM_APB>;
862 };
863
2d8e0747
JZ		 864 ddr-pmu@3d800000 {
865 compatible = "fsl,imx8mn-ddr-pmu", "fsl,imx8m-ddr-pmu";
866 reg = <0x3d800000 0x400000>;
867 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
868 };
6c3debcb
AH		 869 };
870
871 usbphynop1: usbphynop1 {
872 compatible = "usb-nop-xceiv";
873 clocks = <&clk IMX8MN_CLK_USB_PHY_REF>;
874 assigned-clocks = <&clk IMX8MN_CLK_USB_PHY_REF>;
875 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_100M>;
876 clock-names = "main_clk";
877 };
878
879 usbphynop2: usbphynop2 {
880 compatible = "usb-nop-xceiv";
881 clocks = <&clk IMX8MN_CLK_USB_PHY_REF>;
882 assigned-clocks = <&clk IMX8MN_CLK_USB_PHY_REF>;
883 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_100M>;
884 clock-names = "main_clk";
885 };
886};
Linux 6.x block layer and io_uring tree(s)