[linux-2.6-block.git] / arch / arm64 / boot / dts / freescale / imx8mm-beacon-som.dtsi

// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
 * Copyright 2020 Compass Electronics Group, LLC
 */

#include "imx8mm-overdrive.dtsi"

/ {
	aliases {
		rtc0 = &rtc;
		rtc1 = &snvs_rtc;
	};

	usdhc1_pwrseq: usdhc1_pwrseq {
		compatible = "mmc-pwrseq-simple";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_usdhc1_gpio>;
		reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
		clocks = <&osc_32k>;
		clock-names = "ext_clock";
		post-power-on-delay-ms = <80>;
	};

	memory@40000000 {
		device_type = "memory";
		reg = <0x0 0x40000000 0 0x80000000>;
	};
};

&A53_0 {
	cpu-supply = <&buck2_reg>;
};

&A53_1 {
	cpu-supply = <&buck2_reg>;
};

&A53_2 {
	cpu-supply = <&buck2_reg>;
};

&A53_3 {
	cpu-supply = <&buck2_reg>;
};

&ddrc {
	operating-points-v2 = <&ddrc_opp_table>;

	ddrc_opp_table: opp-table {
		compatible = "operating-points-v2";

		opp-25000000 {
			opp-hz = /bits/ 64 <25000000>;
		};

		opp-100000000 {
			opp-hz = /bits/ 64 <100000000>;
		};

		opp-750000000 {
			opp-hz = /bits/ 64 <750000000>;
		};
	};
};

&fec1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_fec1>;
	phy-mode = "rgmii-id";
	phy-handle = <&ethphy0>;
	fsl,magic-packet;
	status = "okay";

	mdio {
		#address-cells = <1>;
		#size-cells = <0>;

		ethphy0: ethernet-phy@0 {
			compatible = "ethernet-phy-ieee802.3-c22";
			reg = <0>;
		};
	};
};

&flexspi {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_flexspi>;
	status = "okay";

	flash@0 {
		reg = <0>;
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "jedec,spi-nor";
		spi-max-frequency = <80000000>;
		spi-tx-bus-width = <1>;
		spi-rx-bus-width = <4>;
	};
};

&i2c1 {
	clock-frequency = <400000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c1>;
	status = "okay";

	pmic@4b {
		compatible = "rohm,bd71847";
		reg = <0x4b>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_pmic>;
		interrupt-parent = <&gpio1>;
		interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
		rohm,reset-snvs-powered;

		#clock-cells = <0>;
		clocks = <&osc_32k>;
		clock-output-names = "clk-32k-out";

		regulators {
			buck1_reg: BUCK1 {
				regulator-name = "buck1";
				regulator-min-microvolt = <700000>;
				regulator-max-microvolt = <1300000>;
				regulator-boot-on;
				regulator-always-on;
				regulator-ramp-delay = <1250>;
			};

			buck2_reg: BUCK2 {
				regulator-name = "buck2";
				regulator-min-microvolt = <700000>;
				regulator-max-microvolt = <1300000>;
				regulator-boot-on;
				regulator-always-on;
				regulator-ramp-delay = <1250>;
				rohm,dvs-run-voltage = <1000000>;
				rohm,dvs-idle-voltage = <900000>;
			};

			buck3_reg: BUCK3 {
				// BUCK5 in datasheet
				regulator-name = "buck3";
				regulator-min-microvolt = <700000>;
				regulator-max-microvolt = <1350000>;
				regulator-boot-on;
				regulator-always-on;
			};

			buck4_reg: BUCK4 {
				// BUCK6 in datasheet
				regulator-name = "buck4";
				regulator-min-microvolt = <3000000>;
				regulator-max-microvolt = <3300000>;
				regulator-boot-on;
				regulator-always-on;
			};

			buck5_reg: BUCK5 {
				// BUCK7 in datasheet
				regulator-name = "buck5";
				regulator-min-microvolt = <1605000>;
				regulator-max-microvolt = <1995000>;
				regulator-boot-on;
				regulator-always-on;
			};

			buck6_reg: BUCK6 {
				// BUCK8 in datasheet
				regulator-name = "buck6";
				regulator-min-microvolt = <800000>;
				regulator-max-microvolt = <1400000>;
				regulator-boot-on;
				regulator-always-on;
			};

			ldo1_reg: LDO1 {
				regulator-name = "ldo1";
				regulator-min-microvolt = <1600000>;
				regulator-max-microvolt = <3300000>;
				regulator-boot-on;
				regulator-always-on;
			};

			ldo2_reg: LDO2 {
				regulator-name = "ldo2";
				regulator-min-microvolt = <800000>;
				regulator-max-microvolt = <900000>;
				regulator-boot-on;
				regulator-always-on;
			};

			ldo3_reg: LDO3 {
				regulator-name = "ldo3";
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <3300000>;
				regulator-boot-on;
				regulator-always-on;
			};

			ldo4_reg: LDO4 {
				regulator-name = "ldo4";
				regulator-min-microvolt = <900000>;
				regulator-max-microvolt = <1800000>;
				regulator-boot-on;
				regulator-always-on;
			};

			ldo6_reg: LDO6 {
				regulator-name = "ldo6";
				regulator-min-microvolt = <900000>;
				regulator-max-microvolt = <1800000>;
				regulator-boot-on;
				regulator-always-on;
			};
		};
	};
};

&i2c3 {
	clock-frequency = <400000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c3>;
	status = "okay";

	eeprom@50 {
		compatible = "microchip,24c64", "atmel,24c64";
		pagesize = <32>;
		read-only;	/* Manufacturing EEPROM programmed at factory */
		reg = <0x50>;
	};

	rtc: rtc@51 {
		compatible = "nxp,pcf85263";
		reg = <0x51>;
	};
};

&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1>;
	assigned-clocks = <&clk IMX8MM_CLK_UART1>;
	assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
	uart-has-rtscts;
	status = "okay";

	bluetooth {
		compatible = "brcm,bcm43438-bt";
		shutdown-gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>;
		host-wakeup-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>;
		device-wakeup-gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>;
		clocks = <&osc_32k>;
		max-speed = <4000000>;
		clock-names = "extclk";
	};
};

&usdhc1 {
	#address-cells = <1>;
	#size-cells = <0>;
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc1>;
	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
	bus-width = <4>;
	non-removable;
	cap-power-off-card;
	keep-power-in-suspend;
	mmc-pwrseq = <&usdhc1_pwrseq>;
	status = "okay";

	brcmf: bcrmf@1 {
		reg = <1>;
		compatible = "brcm,bcm4329-fmac";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_wlan>;
		interrupt-parent = <&gpio2>;
		interrupts = <9 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "host-wake";
	};
};

&usdhc3 {
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc3>;
	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
	bus-width = <8>;
	non-removable;
	status = "okay";
};

&wdog1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_wdog>;
	fsl,ext-reset-output;
	status = "okay";
};

&iomuxc {
	pinctrl_fec1: fec1grp {
		fsl,pins = <
			MX8MM_IOMUXC_ENET_MDC_ENET1_MDC		0x3
			MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO	0x3
			MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3	0x1f
			MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2	0x1f
			MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1	0x1f
			MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0	0x1f
			MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3	0x91
			MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2	0x91
			MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1	0x91
			MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0	0x91
			MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC	0x1f
			MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC	0x91
			MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91
			MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f
			MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22	0x19
		>;
	};

	pinctrl_i2c1: i2c1grp {
		fsl,pins = <
			MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL		0x400001c3
			MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA		0x400001c3
		>;
	};

	pinctrl_i2c3: i2c3grp {
		fsl,pins = <
			MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL		0x400001c3
			MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA		0x400001c3
		>;
	};

	pinctrl_flexspi: flexspigrp {
		fsl,pins = <
			MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK               0x1c2
			MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B            0x82
			MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0           0x82
			MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1           0x82
			MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2           0x82
			MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3           0x82
		>;
	};

	pinctrl_pmic: pmicirqgrp {
		fsl,pins = <
			MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3	0x141
		>;
	};

	pinctrl_uart1: uart1grp {
		fsl,pins = <
			MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX	0x140
			MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX	0x140
			MX8MM_IOMUXC_UART3_RXD_UART1_DCE_CTS_B	0x140
			MX8MM_IOMUXC_UART3_TXD_UART1_DCE_RTS_B	0x140
			MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6	0x19
			MX8MM_IOMUXC_SD1_DATA5_GPIO2_IO7	0x19
			MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8	0x19
			MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K	0x141
		>;
	};

	pinctrl_usdhc1_gpio: usdhc1gpiogrp {
		fsl,pins = <
			MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10	0x41
		>;
	};

	pinctrl_usdhc1: usdhc1grp {
		fsl,pins = <
			MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK		0x190
			MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD		0x1d0
			MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0	0x1d0
			MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1	0x1d0
			MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2	0x1d0
			MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3	0x1d0
		>;
	};

	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
		fsl,pins = <
			MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK		0x194
			MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD		0x1d4
			MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0	0x1d4
			MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1	0x1d4
			MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2	0x1d4
			MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3	0x1d4
		>;
	};

	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
		fsl,pins = <
			MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK		0x196
			MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD		0x1d6
			MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0	0x1d6
			MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1	0x1d6
			MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2	0x1d6
			MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3	0x1d6
		>;
	};

	pinctrl_usdhc3: usdhc3grp {
		fsl,pins = <
			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK		0x190
			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d0
			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x1d0
			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x1d0
			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x1d0
			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x1d0
			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4		0x1d0
			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5		0x1d0
			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6		0x1d0
			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7		0x1d0
			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE		0x190
		>;
	};

	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
		fsl,pins = <
			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK		0x194
			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d4
			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x1d4
			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x1d4
			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x1d4
			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x1d4
			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4		0x1d4
			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5		0x1d4
			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6		0x1d4
			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7		0x1d4
			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE		0x194
		>;
	};

	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
		fsl,pins = <
			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK		0x196
			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d6
			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x1d6
			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x1d6
			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x1d6
			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x1d6
			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4		0x1d6
			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5		0x1d6
			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6		0x1d6
			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7		0x1d6
			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE		0x196
		>;
	};

	pinctrl_wdog: wdoggrp {
		fsl,pins = <
			MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B		0x166
		>;
	};

	pinctrl_wlan: wlangrp {
		fsl,pins = <
			MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9		0x111
		>;
	};
};
Commit	Line	Data
593816fa AF	1	// SPDX-License-Identifier: (GPL-2.0 OR MIT)
	2	/*
	3	* Copyright 2020 Compass Electronics Group, LLC
	4	*/
	5
6557e92e AF	6	#include "imx8mm-overdrive.dtsi"
6557e92e AF	7
593816fa	8	/ {
6b5cd773 AF	9	aliases {
	10	rtc0 = &rtc;
	11	rtc1 = &snvs_rtc;
	12	};
	13
593816fa AF	14	usdhc1_pwrseq: usdhc1_pwrseq {
	15	compatible = "mmc-pwrseq-simple";
	16	pinctrl-names = "default";
	17	pinctrl-0 = <&pinctrl_usdhc1_gpio>;
	18	reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
	19	clocks = <&osc_32k>;
	20	clock-names = "ext_clock";
	21	post-power-on-delay-ms = <80>;
	22	};
	23
	24	memory@40000000 {
	25	device_type = "memory";
	26	reg = <0x0 0x40000000 0 0x80000000>;
	27	};
	28	};
	29
	30	&A53_0 {
	31	cpu-supply = <&buck2_reg>;
	32	};
	33
56c6b4dd AF	34	&A53_1 {
	35	cpu-supply = <&buck2_reg>;
	36	};
	37
	38	&A53_2 {
	39	cpu-supply = <&buck2_reg>;
	40	};
	41
	42	&A53_3 {
	43	cpu-supply = <&buck2_reg>;
	44	};
	45
593816fa AF	46	&ddrc {
	47	operating-points-v2 = <&ddrc_opp_table>;
	48
	49	ddrc_opp_table: opp-table {
	50	compatible = "operating-points-v2";
	51
0c068a36	52	opp-25000000 {
593816fa AF	53	opp-hz = /bits/ 64 <25000000>;
	54	};
	55
0c068a36	56	opp-100000000 {
593816fa AF	57	opp-hz = /bits/ 64 <100000000>;
	58	};
	59
0c068a36	60	opp-750000000 {
593816fa AF	61	opp-hz = /bits/ 64 <750000000>;
	62	};
	63	};
	64	};
	65
	66	&fec1 {
	67	pinctrl-names = "default";
	68	pinctrl-0 = <&pinctrl_fec1>;
	69	phy-mode = "rgmii-id";
	70	phy-handle = <&ethphy0>;
	71	fsl,magic-packet;
	72	status = "okay";
	73
	74	mdio {
	75	#address-cells = <1>;
	76	#size-cells = <0>;
	77
	78	ethphy0: ethernet-phy@0 {
	79	compatible = "ethernet-phy-ieee802.3-c22";
	80	reg = <0>;
	81	};
	82	};
	83	};
	84
582b6d8b AF	85	&flexspi {
	86	pinctrl-names = "default";
	87	pinctrl-0 = <&pinctrl_flexspi>;
	88	status = "okay";
	89
	90	flash@0 {
	91	reg = <0>;
	92	#address-cells = <1>;
	93	#size-cells = <1>;
	94	compatible = "jedec,spi-nor";
	95	spi-max-frequency = <80000000>;
04aa946d	96	spi-tx-bus-width = <1>;
582b6d8b AF	97	spi-rx-bus-width = <4>;
	98	};
	99	};
	100
593816fa AF	101	&i2c1 {
	102	clock-frequency = <400000>;
	103	pinctrl-names = "default";
	104	pinctrl-0 = <&pinctrl_i2c1>;
	105	status = "okay";
	106
	107	pmic@4b {
	108	compatible = "rohm,bd71847";
	109	reg = <0x4b>;
0710e438	110	pinctrl-names = "default";
593816fa AF	111	pinctrl-0 = <&pinctrl_pmic>;
593816fa AF	112	interrupt-parent = <&gpio1>;
5f67317b	113	interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
593816fa AF	114	rohm,reset-snvs-powered;
593816fa AF	115
0b848626	116	#clock-cells = <0>;
ebb8dbec	117	clocks = <&osc_32k>;
0b848626 AF	118	clock-output-names = "clk-32k-out";
0b848626 AF	119
593816fa AF	120	regulators {
593816fa AF	121	buck1_reg: BUCK1 {
a265046d	122	regulator-name = "buck1";
593816fa AF	123	regulator-min-microvolt = <700000>;
	124	regulator-max-microvolt = <1300000>;
	125	regulator-boot-on;
	126	regulator-always-on;
	127	regulator-ramp-delay = <1250>;
	128	};
	129
	130	buck2_reg: BUCK2 {
a265046d	131	regulator-name = "buck2";
593816fa AF	132	regulator-min-microvolt = <700000>;
	133	regulator-max-microvolt = <1300000>;
	134	regulator-boot-on;
	135	regulator-always-on;
	136	regulator-ramp-delay = <1250>;
	137	rohm,dvs-run-voltage = <1000000>;
	138	rohm,dvs-idle-voltage = <900000>;
	139	};
	140
	141	buck3_reg: BUCK3 {
	142	// BUCK5 in datasheet
a265046d	143	regulator-name = "buck3";
593816fa AF	144	regulator-min-microvolt = <700000>;
	145	regulator-max-microvolt = <1350000>;
	146	regulator-boot-on;
	147	regulator-always-on;
	148	};
	149
	150	buck4_reg: BUCK4 {
	151	// BUCK6 in datasheet
a265046d	152	regulator-name = "buck4";
593816fa AF	153	regulator-min-microvolt = <3000000>;
	154	regulator-max-microvolt = <3300000>;
	155	regulator-boot-on;
	156	regulator-always-on;
	157	};
	158
	159	buck5_reg: BUCK5 {
	160	// BUCK7 in datasheet
a265046d	161	regulator-name = "buck5";
593816fa AF	162	regulator-min-microvolt = <1605000>;
	163	regulator-max-microvolt = <1995000>;
	164	regulator-boot-on;
	165	regulator-always-on;
	166	};
	167
	168	buck6_reg: BUCK6 {
	169	// BUCK8 in datasheet
a265046d	170	regulator-name = "buck6";
593816fa AF	171	regulator-min-microvolt = <800000>;
	172	regulator-max-microvolt = <1400000>;
	173	regulator-boot-on;
	174	regulator-always-on;
	175	};
	176
	177	ldo1_reg: LDO1 {
a265046d	178	regulator-name = "ldo1";
e353b325	179	regulator-min-microvolt = <1600000>;
593816fa AF	180	regulator-max-microvolt = <3300000>;
	181	regulator-boot-on;
	182	regulator-always-on;
	183	};
	184
	185	ldo2_reg: LDO2 {
a265046d	186	regulator-name = "ldo2";
e353b325	187	regulator-min-microvolt = <800000>;
593816fa AF	188	regulator-max-microvolt = <900000>;
	189	regulator-boot-on;
	190	regulator-always-on;
	191	};
	192
	193	ldo3_reg: LDO3 {
a265046d	194	regulator-name = "ldo3";
593816fa AF	195	regulator-min-microvolt = <1800000>;
	196	regulator-max-microvolt = <3300000>;
	197	regulator-boot-on;
	198	regulator-always-on;
	199	};
	200
	201	ldo4_reg: LDO4 {
a265046d	202	regulator-name = "ldo4";
593816fa AF	203	regulator-min-microvolt = <900000>;
	204	regulator-max-microvolt = <1800000>;
	205	regulator-boot-on;
	206	regulator-always-on;
	207	};
	208
	209	ldo6_reg: LDO6 {
a265046d	210	regulator-name = "ldo6";
593816fa AF	211	regulator-min-microvolt = <900000>;
	212	regulator-max-microvolt = <1800000>;
	213	regulator-boot-on;
	214	regulator-always-on;
	215	};
	216	};
	217	};
	218	};
	219
	220	&i2c3 {
	221	clock-frequency = <400000>;
	222	pinctrl-names = "default";
	223	pinctrl-0 = <&pinctrl_i2c3>;
	224	status = "okay";
	225
	226	eeprom@50 {
31c78242	227	compatible = "microchip,24c64", "atmel,24c64";
593816fa AF	228	pagesize = <32>;
	229	read-only; /* Manufacturing EEPROM programmed at factory */
	230	reg = <0x50>;
	231	};
	232
6b5cd773	233	rtc: rtc@51 {
593816fa AF	234	compatible = "nxp,pcf85263";
	235	reg = <0x51>;
	236	};
	237	};
	238
	239	&uart1 {
	240	pinctrl-names = "default";
	241	pinctrl-0 = <&pinctrl_uart1>;
	242	assigned-clocks = <&clk IMX8MM_CLK_UART1>;
	243	assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
	244	uart-has-rtscts;
	245	status = "okay";
	246
	247	bluetooth {
	248	compatible = "brcm,bcm43438-bt";
	249	shutdown-gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>;
	250	host-wakeup-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>;
	251	device-wakeup-gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>;
	252	clocks = <&osc_32k>;
587258ed	253	max-speed = <4000000>;
593816fa AF	254	clock-names = "extclk";
	255	};
	256	};
	257
	258	&usdhc1 {
	259	#address-cells = <1>;
	260	#size-cells = <0>;
e8d08d80	261	pinctrl-names = "default", "state_100mhz", "state_200mhz";
593816fa	262	pinctrl-0 = <&pinctrl_usdhc1>;
e8d08d80 AF	263	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
e8d08d80 AF	264	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
593816fa AF	265	bus-width = <4>;
	266	non-removable;
	267	cap-power-off-card;
593816fa AF	268	keep-power-in-suspend;
	269	mmc-pwrseq = <&usdhc1_pwrseq>;
	270	status = "okay";
	271
	272	brcmf: bcrmf@1 {
	273	reg = <1>;
	274	compatible = "brcm,bcm4329-fmac";
	275	pinctrl-names = "default";
	276	pinctrl-0 = <&pinctrl_wlan>;
	277	interrupt-parent = <&gpio2>;
	278	interrupts = <9 IRQ_TYPE_LEVEL_HIGH>;
	279	interrupt-names = "host-wake";
	280	};
	281	};
	282
	283	&usdhc3 {
	284	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	285	pinctrl-0 = <&pinctrl_usdhc3>;
	286	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
	287	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
	288	bus-width = <8>;
	289	non-removable;
	290	status = "okay";
	291	};
	292
	293	&wdog1 {
	294	pinctrl-names = "default";
	295	pinctrl-0 = <&pinctrl_wdog>;
	296	fsl,ext-reset-output;
	297	status = "okay";
	298	};
	299
	300	&iomuxc {
60a9d6ab AF	301	pinctrl_fec1: fec1grp {
	302	fsl,pins = <
	303	MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
	304	MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
	305	MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
	306	MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
	307	MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
	308	MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
	309	MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
	310	MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
	311	MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
	312	MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
	313	MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
	314	MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
	315	MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
	316	MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
	317	MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19
	318	>;
	319	};
593816fa	320
60a9d6ab AF	321	pinctrl_i2c1: i2c1grp {
	322	fsl,pins = <
	323	MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
	324	MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
	325	>;
	326	};
593816fa	327
60a9d6ab AF	328	pinctrl_i2c3: i2c3grp {
	329	fsl,pins = <
	330	MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
	331	MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
	332	>;
	333	};
593816fa	334
60a9d6ab AF	335	pinctrl_flexspi: flexspigrp {
	336	fsl,pins = <
	337	MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2
	338	MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82
	339	MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82
	340	MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82
	341	MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82
	342	MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82
	343	>;
	344	};
593816fa	345
60a9d6ab AF	346	pinctrl_pmic: pmicirqgrp {
	347	fsl,pins = <
	348	MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141
	349	>;
	350	};
593816fa	351
60a9d6ab AF	352	pinctrl_uart1: uart1grp {
	353	fsl,pins = <
	354	MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140
	355	MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140
	356	MX8MM_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x140
	357	MX8MM_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x140
	358	MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x19
	359	MX8MM_IOMUXC_SD1_DATA5_GPIO2_IO7 0x19
	360	MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x19
	361	MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x141
	362	>;
	363	};
593816fa	364
60a9d6ab AF	365	pinctrl_usdhc1_gpio: usdhc1gpiogrp {
	366	fsl,pins = <
	367	MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x41
	368	>;
	369	};
593816fa	370
60a9d6ab AF	371	pinctrl_usdhc1: usdhc1grp {
	372	fsl,pins = <
	373	MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190
	374	MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0
	375	MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0
	376	MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0
	377	MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0
	378	MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0
	379	>;
	380	};
593816fa	381
60a9d6ab AF	382	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
	383	fsl,pins = <
	384	MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194
	385	MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4
	386	MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4
	387	MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4
	388	MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4
	389	MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4
	390	>;
	391	};
593816fa	392
60a9d6ab AF	393	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
	394	fsl,pins = <
	395	MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196
	396	MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6
	397	MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6
	398	MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6
	399	MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6
	400	MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6
	401	>;
	402	};
593816fa	403
60a9d6ab AF	404	pinctrl_usdhc3: usdhc3grp {
	405	fsl,pins = <
	406	MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
	407	MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
	408	MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
	409	MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
	410	MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
	411	MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
	412	MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
	413	MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
	414	MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
	415	MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
	416	MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
	417	>;
	418	};
593816fa	419
60a9d6ab AF	420	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
	421	fsl,pins = <
	422	MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
	423	MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
	424	MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
	425	MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
	426	MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
	427	MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
	428	MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
	429	MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
	430	MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
	431	MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
	432	MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
	433	>;
	434	};
593816fa	435
60a9d6ab AF	436	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
	437	fsl,pins = <
	438	MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
	439	MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
	440	MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
	441	MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
	442	MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
	443	MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
	444	MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
	445	MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
	446	MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
	447	MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
	448	MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
	449	>;
	450	};
593816fa	451
60a9d6ab AF	452	pinctrl_wdog: wdoggrp {
	453	fsl,pins = <
	454	MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x166
	455	>;
	456	};
593816fa	457
60a9d6ab AF	458	pinctrl_wlan: wlangrp {
	459	fsl,pins = <
	460	MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9 0x111
	461	>;
	462	};
593816fa	463	};