[linux-2.6-block.git] / arch / arm64 / boot / dts / freescale / imx8-ss-dma.dtsi

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright 2018-2019 NXP
 *	Dong Aisheng <aisheng.dong@nxp.com>
 */

#include <dt-bindings/clock/imx8-lpcg.h>
#include <dt-bindings/firmware/imx/rsrc.h>

dma_ipg_clk: clock-dma-ipg {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <120000000>;
	clock-output-names = "dma_ipg_clk";
};

dma_subsys: bus@5a000000 {
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x5a000000 0x0 0x5a000000 0x1000000>;

	lpspi0: spi@5a000000 {
		compatible = "fsl,imx7ulp-spi";
		reg = <0x5a000000 0x10000>;
		#address-cells = <1>;
		#size-cells = <0>;
		interrupts = <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-parent = <&gic>;
		clocks = <&spi0_lpcg 0>,
			 <&spi0_lpcg 1>;
		clock-names = "per", "ipg";
		assigned-clocks = <&clk IMX_SC_R_SPI_0 IMX_SC_PM_CLK_PER>;
		assigned-clock-rates = <60000000>;
		power-domains = <&pd IMX_SC_R_SPI_0>;
		status = "disabled";
	};

	lpspi1: spi@5a010000 {
		compatible = "fsl,imx7ulp-spi";
		reg = <0x5a010000 0x10000>;
		#address-cells = <1>;
		#size-cells = <0>;
		interrupts = <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-parent = <&gic>;
		clocks = <&spi1_lpcg 0>,
			 <&spi1_lpcg 1>;
		clock-names = "per", "ipg";
		assigned-clocks = <&clk IMX_SC_R_SPI_1 IMX_SC_PM_CLK_PER>;
		assigned-clock-rates = <60000000>;
		power-domains = <&pd IMX_SC_R_SPI_1>;
		status = "disabled";
	};

	lpspi2: spi@5a020000 {
		compatible = "fsl,imx7ulp-spi";
		reg = <0x5a020000 0x10000>;
		#address-cells = <1>;
		#size-cells = <0>;
		interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-parent = <&gic>;
		clocks = <&spi2_lpcg 0>,
			 <&spi2_lpcg 1>;
		clock-names = "per", "ipg";
		assigned-clocks = <&clk IMX_SC_R_SPI_2 IMX_SC_PM_CLK_PER>;
		assigned-clock-rates = <60000000>;
		power-domains = <&pd IMX_SC_R_SPI_2>;
		status = "disabled";
	};

	lpspi3: spi@5a030000 {
		compatible = "fsl,imx7ulp-spi";
		reg = <0x5a030000 0x10000>;
		#address-cells = <1>;
		#size-cells = <0>;
		interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-parent = <&gic>;
		clocks = <&spi3_lpcg 0>,
			 <&spi3_lpcg 1>;
		clock-names = "per", "ipg";
		assigned-clocks = <&clk IMX_SC_R_SPI_3 IMX_SC_PM_CLK_PER>;
		assigned-clock-rates = <60000000>;
		power-domains = <&pd IMX_SC_R_SPI_3>;
		status = "disabled";
	};

	lpuart0: serial@5a060000 {
		reg = <0x5a060000 0x1000>;
		interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&uart0_lpcg IMX_LPCG_CLK_4>,
			 <&uart0_lpcg IMX_LPCG_CLK_0>;
		clock-names = "ipg", "baud";
		assigned-clocks = <&clk IMX_SC_R_UART_0 IMX_SC_PM_CLK_PER>;
		assigned-clock-rates = <80000000>;
		power-domains = <&pd IMX_SC_R_UART_0>;
		status = "disabled";
	};

	lpuart1: serial@5a070000 {
		reg = <0x5a070000 0x1000>;
		interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&uart1_lpcg IMX_LPCG_CLK_4>,
			 <&uart1_lpcg IMX_LPCG_CLK_0>;
		clock-names = "ipg", "baud";
		assigned-clocks = <&clk IMX_SC_R_UART_1 IMX_SC_PM_CLK_PER>;
		assigned-clock-rates = <80000000>;
		power-domains = <&pd IMX_SC_R_UART_1>;
		status = "disabled";
	};

	lpuart2: serial@5a080000 {
		reg = <0x5a080000 0x1000>;
		interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&uart2_lpcg IMX_LPCG_CLK_4>,
			 <&uart2_lpcg IMX_LPCG_CLK_0>;
		clock-names = "ipg", "baud";
		assigned-clocks = <&clk IMX_SC_R_UART_2 IMX_SC_PM_CLK_PER>;
		assigned-clock-rates = <80000000>;
		power-domains = <&pd IMX_SC_R_UART_2>;
		status = "disabled";
	};

	lpuart3: serial@5a090000 {
		reg = <0x5a090000 0x1000>;
		interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&uart3_lpcg IMX_LPCG_CLK_4>,
			 <&uart3_lpcg IMX_LPCG_CLK_0>;
		clock-names = "ipg", "baud";
		assigned-clocks = <&clk IMX_SC_R_UART_3 IMX_SC_PM_CLK_PER>;
		assigned-clock-rates = <80000000>;
		power-domains = <&pd IMX_SC_R_UART_3>;
		status = "disabled";
	};

	adma_pwm: pwm@5a190000 {
		compatible = "fsl,imx8qxp-pwm", "fsl,imx27-pwm";
		reg = <0x5a190000 0x1000>;
		interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&adma_pwm_lpcg 1>,
			 <&adma_pwm_lpcg 0>;
		clock-names = "ipg", "per";
		assigned-clocks = <&clk IMX_SC_R_LCD_0_PWM_0 IMX_SC_PM_CLK_PER>;
		assigned-clock-rates = <24000000>;
		#pwm-cells = <2>;
		power-domains = <&pd IMX_SC_R_LCD_0_PWM_0>;
	};

	edma2: dma-controller@5a1f0000 {
		compatible = "fsl,imx8qm-edma";
		reg = <0x5a1f0000 0x170000>;
		#dma-cells = <3>;
		dma-channels = <16>;
		interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>;
		power-domains = <&pd IMX_SC_R_DMA_2_CH0>,
				<&pd IMX_SC_R_DMA_2_CH1>,
				<&pd IMX_SC_R_DMA_2_CH2>,
				<&pd IMX_SC_R_DMA_2_CH3>,
				<&pd IMX_SC_R_DMA_2_CH4>,
				<&pd IMX_SC_R_DMA_2_CH5>,
				<&pd IMX_SC_R_DMA_2_CH6>,
				<&pd IMX_SC_R_DMA_2_CH7>,
				<&pd IMX_SC_R_DMA_2_CH8>,
				<&pd IMX_SC_R_DMA_2_CH9>,
				<&pd IMX_SC_R_DMA_2_CH10>,
				<&pd IMX_SC_R_DMA_2_CH11>,
				<&pd IMX_SC_R_DMA_2_CH12>,
				<&pd IMX_SC_R_DMA_2_CH13>,
				<&pd IMX_SC_R_DMA_2_CH14>,
				<&pd IMX_SC_R_DMA_2_CH15>;
	};

	edma3: dma-controller@5a9f0000 {
		compatible = "fsl,imx8qm-edma";
		reg = <0x5a9f0000 0x90000>;
		#dma-cells = <3>;
		dma-channels = <8>;
		interrupts = <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>;
		power-domains = <&pd IMX_SC_R_DMA_3_CH0>,
				<&pd IMX_SC_R_DMA_3_CH1>,
				<&pd IMX_SC_R_DMA_3_CH2>,
				<&pd IMX_SC_R_DMA_3_CH3>,
				<&pd IMX_SC_R_DMA_3_CH4>,
				<&pd IMX_SC_R_DMA_3_CH5>,
				<&pd IMX_SC_R_DMA_3_CH6>,
				<&pd IMX_SC_R_DMA_3_CH7>;
	};

	spi0_lpcg: clock-controller@5a400000 {
		compatible = "fsl,imx8qxp-lpcg";
		reg = <0x5a400000 0x10000>;
		#clock-cells = <1>;
		clocks = <&clk IMX_SC_R_SPI_0 IMX_SC_PM_CLK_PER>,
			 <&dma_ipg_clk>;
		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
		clock-output-names = "spi0_lpcg_clk",
				     "spi0_lpcg_ipg_clk";
		power-domains = <&pd IMX_SC_R_SPI_0>;
	};

	spi1_lpcg: clock-controller@5a410000 {
		compatible = "fsl,imx8qxp-lpcg";
		reg = <0x5a410000 0x10000>;
		#clock-cells = <1>;
		clocks = <&clk IMX_SC_R_SPI_1 IMX_SC_PM_CLK_PER>,
			 <&dma_ipg_clk>;
		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
		clock-output-names = "spi1_lpcg_clk",
				     "spi1_lpcg_ipg_clk";
		power-domains = <&pd IMX_SC_R_SPI_1>;
	};

	spi2_lpcg: clock-controller@5a420000 {
		compatible = "fsl,imx8qxp-lpcg";
		reg = <0x5a420000 0x10000>;
		#clock-cells = <1>;
		clocks = <&clk IMX_SC_R_SPI_2 IMX_SC_PM_CLK_PER>,
			 <&dma_ipg_clk>;
		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
		clock-output-names = "spi2_lpcg_clk",
				     "spi2_lpcg_ipg_clk";
		power-domains = <&pd IMX_SC_R_SPI_2>;
	};

	spi3_lpcg: clock-controller@5a430000 {
		compatible = "fsl,imx8qxp-lpcg";
		reg = <0x5a430000 0x10000>;
		#clock-cells = <1>;
		clocks = <&clk IMX_SC_R_SPI_3 IMX_SC_PM_CLK_PER>,
			 <&dma_ipg_clk>;
		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
		clock-output-names = "spi3_lpcg_clk",
				     "spi3_lpcg_ipg_clk";
		power-domains = <&pd IMX_SC_R_SPI_3>;
	};

	uart0_lpcg: clock-controller@5a460000 {
		compatible = "fsl,imx8qxp-lpcg";
		reg = <0x5a460000 0x10000>;
		#clock-cells = <1>;
		clocks = <&clk IMX_SC_R_UART_0 IMX_SC_PM_CLK_PER>,
			 <&dma_ipg_clk>;
		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
		clock-output-names = "uart0_lpcg_baud_clk",
				     "uart0_lpcg_ipg_clk";
		power-domains = <&pd IMX_SC_R_UART_0>;
	};

	uart1_lpcg: clock-controller@5a470000 {
		compatible = "fsl,imx8qxp-lpcg";
		reg = <0x5a470000 0x10000>;
		#clock-cells = <1>;
		clocks = <&clk IMX_SC_R_UART_1 IMX_SC_PM_CLK_PER>,
			 <&dma_ipg_clk>;
		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
		clock-output-names = "uart1_lpcg_baud_clk",
				     "uart1_lpcg_ipg_clk";
		power-domains = <&pd IMX_SC_R_UART_1>;
	};

	uart2_lpcg: clock-controller@5a480000 {
		compatible = "fsl,imx8qxp-lpcg";
		reg = <0x5a480000 0x10000>;
		#clock-cells = <1>;
		clocks = <&clk IMX_SC_R_UART_2 IMX_SC_PM_CLK_PER>,
			 <&dma_ipg_clk>;
		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
		clock-output-names = "uart2_lpcg_baud_clk",
				     "uart2_lpcg_ipg_clk";
		power-domains = <&pd IMX_SC_R_UART_2>;
	};

	uart3_lpcg: clock-controller@5a490000 {
		compatible = "fsl,imx8qxp-lpcg";
		reg = <0x5a490000 0x10000>;
		#clock-cells = <1>;
		clocks = <&clk IMX_SC_R_UART_3 IMX_SC_PM_CLK_PER>,
			 <&dma_ipg_clk>;
		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
		clock-output-names = "uart3_lpcg_baud_clk",
				     "uart3_lpcg_ipg_clk";
		power-domains = <&pd IMX_SC_R_UART_3>;
	};

	adma_pwm_lpcg: clock-controller@5a590000 {
		compatible = "fsl,imx8qxp-lpcg";
		reg = <0x5a590000 0x10000>;
		#clock-cells = <1>;
		clocks = <&clk IMX_SC_R_LCD_0_PWM_0 IMX_SC_PM_CLK_PER>,
			 <&dma_ipg_clk>;
		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
		clock-output-names = "adma_pwm_lpcg_clk",
				     "adma_pwm_lpcg_ipg_clk";
		power-domains = <&pd IMX_SC_R_LCD_0_PWM_0>;
	};

	i2c0: i2c@5a800000 {
		reg = <0x5a800000 0x4000>;
		interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&i2c0_lpcg IMX_LPCG_CLK_0>,
			 <&i2c0_lpcg IMX_LPCG_CLK_4>;
		clock-names = "per", "ipg";
		assigned-clocks = <&clk IMX_SC_R_I2C_0 IMX_SC_PM_CLK_PER>;
		assigned-clock-rates = <24000000>;
		power-domains = <&pd IMX_SC_R_I2C_0>;
		status = "disabled";
	};

	i2c1: i2c@5a810000 {
		reg = <0x5a810000 0x4000>;
		interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&i2c1_lpcg IMX_LPCG_CLK_0>,
			 <&i2c1_lpcg IMX_LPCG_CLK_4>;
		clock-names = "per", "ipg";
		assigned-clocks = <&clk IMX_SC_R_I2C_1 IMX_SC_PM_CLK_PER>;
		assigned-clock-rates = <24000000>;
		power-domains = <&pd IMX_SC_R_I2C_1>;
		status = "disabled";
	};

	i2c2: i2c@5a820000 {
		reg = <0x5a820000 0x4000>;
		interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&i2c2_lpcg IMX_LPCG_CLK_0>,
			 <&i2c2_lpcg IMX_LPCG_CLK_4>;
		clock-names = "per", "ipg";
		assigned-clocks = <&clk IMX_SC_R_I2C_2 IMX_SC_PM_CLK_PER>;
		assigned-clock-rates = <24000000>;
		power-domains = <&pd IMX_SC_R_I2C_2>;
		status = "disabled";
	};

	i2c3: i2c@5a830000 {
		reg = <0x5a830000 0x4000>;
		interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&i2c3_lpcg IMX_LPCG_CLK_0>,
			 <&i2c3_lpcg IMX_LPCG_CLK_4>;
		clock-names = "per", "ipg";
		assigned-clocks = <&clk IMX_SC_R_I2C_3 IMX_SC_PM_CLK_PER>;
		assigned-clock-rates = <24000000>;
		power-domains = <&pd IMX_SC_R_I2C_3>;
		status = "disabled";
	};

	adc0: adc@5a880000 {
		compatible = "nxp,imx8qxp-adc";
		#io-channel-cells = <1>;
		reg = <0x5a880000 0x10000>;
		interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-parent = <&gic>;
		clocks = <&adc0_lpcg 0>,
			 <&adc0_lpcg 1>;
		clock-names = "per", "ipg";
		assigned-clocks = <&clk IMX_SC_R_ADC_0 IMX_SC_PM_CLK_PER>;
		assigned-clock-rates = <24000000>;
		power-domains = <&pd IMX_SC_R_ADC_0>;
		status = "disabled";
	 };

	adc1: adc@5a890000 {
		compatible = "nxp,imx8qxp-adc";
		#io-channel-cells = <1>;
		reg = <0x5a890000 0x10000>;
		interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-parent = <&gic>;
		clocks = <&adc1_lpcg 0>,
			 <&adc1_lpcg 1>;
		clock-names = "per", "ipg";
		assigned-clocks = <&clk IMX_SC_R_ADC_1 IMX_SC_PM_CLK_PER>;
		assigned-clock-rates = <24000000>;
		power-domains = <&pd IMX_SC_R_ADC_1>;
		status = "disabled";
	};

	flexcan1: can@5a8d0000 {
		compatible = "fsl,imx8qm-flexcan";
		reg = <0x5a8d0000 0x10000>;
		interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-parent = <&gic>;
		clocks = <&can0_lpcg 1>,
			 <&can0_lpcg 0>;
		clock-names = "ipg", "per";
		assigned-clocks = <&clk IMX_SC_R_CAN_0 IMX_SC_PM_CLK_PER>;
		assigned-clock-rates = <40000000>;
		power-domains = <&pd IMX_SC_R_CAN_0>;
		/* SLSlice[4] */
		fsl,clk-source = /bits/ 8 <0>;
		fsl,scu-index = /bits/ 8 <0>;
		status = "disabled";
	};

	flexcan2: can@5a8e0000 {
		compatible = "fsl,imx8qm-flexcan";
		reg = <0x5a8e0000 0x10000>;
		interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-parent = <&gic>;
		/* CAN0 clock and PD is shared among all CAN instances as
		 * CAN1 shares CAN0's clock and to enable CAN0's clock it
		 * has to be powered on.
		 */
		clocks = <&can0_lpcg 1>,
			 <&can0_lpcg 0>;
		clock-names = "ipg", "per";
		assigned-clocks = <&clk IMX_SC_R_CAN_0 IMX_SC_PM_CLK_PER>;
		assigned-clock-rates = <40000000>;
		power-domains = <&pd IMX_SC_R_CAN_1>;
		/* SLSlice[4] */
		fsl,clk-source = /bits/ 8 <0>;
		fsl,scu-index = /bits/ 8 <1>;
		status = "disabled";
	};

	flexcan3: can@5a8f0000 {
		compatible = "fsl,imx8qm-flexcan";
		reg = <0x5a8f0000 0x10000>;
		interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-parent = <&gic>;
		/* CAN0 clock and PD is shared among all CAN instances as
		 * CAN2 shares CAN0's clock and to enable CAN0's clock it
		 * has to be powered on.
		 */
		clocks = <&can0_lpcg 1>,
			 <&can0_lpcg 0>;
		clock-names = "ipg", "per";
		assigned-clocks = <&clk IMX_SC_R_CAN_0 IMX_SC_PM_CLK_PER>;
		assigned-clock-rates = <40000000>;
		power-domains = <&pd IMX_SC_R_CAN_2>;
		/* SLSlice[4] */
		fsl,clk-source = /bits/ 8 <0>;
		fsl,scu-index = /bits/ 8 <2>;
		status = "disabled";
	};

	i2c0_lpcg: clock-controller@5ac00000 {
		compatible = "fsl,imx8qxp-lpcg";
		reg = <0x5ac00000 0x10000>;
		#clock-cells = <1>;
		clocks = <&clk IMX_SC_R_I2C_0 IMX_SC_PM_CLK_PER>,
			 <&dma_ipg_clk>;
		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
		clock-output-names = "i2c0_lpcg_clk",
				     "i2c0_lpcg_ipg_clk";
		power-domains = <&pd IMX_SC_R_I2C_0>;
	};

	i2c1_lpcg: clock-controller@5ac10000 {
		compatible = "fsl,imx8qxp-lpcg";
		reg = <0x5ac10000 0x10000>;
		#clock-cells = <1>;
		clocks = <&clk IMX_SC_R_I2C_1 IMX_SC_PM_CLK_PER>,
			 <&dma_ipg_clk>;
		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
		clock-output-names = "i2c1_lpcg_clk",
				     "i2c1_lpcg_ipg_clk";
		power-domains = <&pd IMX_SC_R_I2C_1>;
	};

	i2c2_lpcg: clock-controller@5ac20000 {
		compatible = "fsl,imx8qxp-lpcg";
		reg = <0x5ac20000 0x10000>;
		#clock-cells = <1>;
		clocks = <&clk IMX_SC_R_I2C_2 IMX_SC_PM_CLK_PER>,
			 <&dma_ipg_clk>;
		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
		clock-output-names = "i2c2_lpcg_clk",
				     "i2c2_lpcg_ipg_clk";
		power-domains = <&pd IMX_SC_R_I2C_2>;
	};

	i2c3_lpcg: clock-controller@5ac30000 {
		compatible = "fsl,imx8qxp-lpcg";
		reg = <0x5ac30000 0x10000>;
		#clock-cells = <1>;
		clocks = <&clk IMX_SC_R_I2C_3 IMX_SC_PM_CLK_PER>,
			 <&dma_ipg_clk>;
		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
		clock-output-names = "i2c3_lpcg_clk",
				     "i2c3_lpcg_ipg_clk";
		power-domains = <&pd IMX_SC_R_I2C_3>;
	};

	adc0_lpcg: clock-controller@5ac80000 {
		compatible = "fsl,imx8qxp-lpcg";
		reg = <0x5ac80000 0x10000>;
		#clock-cells = <1>;
		clocks = <&clk IMX_SC_R_ADC_0 IMX_SC_PM_CLK_PER>,
			 <&dma_ipg_clk>;
		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
		clock-output-names = "adc0_lpcg_clk",
				     "adc0_lpcg_ipg_clk";
		power-domains = <&pd IMX_SC_R_ADC_0>;
	};

	adc1_lpcg: clock-controller@5ac90000 {
		compatible = "fsl,imx8qxp-lpcg";
		reg = <0x5ac90000 0x10000>;
		#clock-cells = <1>;
		clocks = <&clk IMX_SC_R_ADC_1 IMX_SC_PM_CLK_PER>,
			 <&dma_ipg_clk>;
		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
		clock-output-names = "adc1_lpcg_clk",
				     "adc1_lpcg_ipg_clk";
		power-domains = <&pd IMX_SC_R_ADC_1>;
	};

	can0_lpcg: clock-controller@5acd0000 {
		compatible = "fsl,imx8qxp-lpcg";
		reg = <0x5acd0000 0x10000>;
		#clock-cells = <1>;
		clocks = <&clk IMX_SC_R_CAN_0 IMX_SC_PM_CLK_PER>,
			 <&dma_ipg_clk>, <&dma_ipg_clk>;
		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>;
		clock-output-names = "can0_lpcg_pe_clk",
				     "can0_lpcg_ipg_clk",
				     "can0_lpcg_chi_clk";
		power-domains = <&pd IMX_SC_R_CAN_0>;
	};
};
Commit	Line	Data
35f4e9d7 DA	1	// SPDX-License-Identifier: GPL-2.0+
	2	/*
	3	* Copyright 2018-2019 NXP
	4	* Dong Aisheng <aisheng.dong@nxp.com>
	5	*/
	6
	7	#include <dt-bindings/clock/imx8-lpcg.h>
	8	#include <dt-bindings/firmware/imx/rsrc.h>
	9
9a69f768 FE	10	dma_ipg_clk: clock-dma-ipg {
	11	compatible = "fixed-clock";
	12	#clock-cells = <0>;
	13	clock-frequency = <120000000>;
	14	clock-output-names = "dma_ipg_clk";
	15	};
	16
35f4e9d7 DA	17	dma_subsys: bus@5a000000 {
	18	compatible = "simple-bus";
	19	#address-cells = <1>;
	20	#size-cells = <1>;
	21	ranges = <0x5a000000 0x0 0x5a000000 0x1000000>;
	22
c4098885 FL	23	lpspi0: spi@5a000000 {
	24	compatible = "fsl,imx7ulp-spi";
	25	reg = <0x5a000000 0x10000>;
	26	#address-cells = <1>;
	27	#size-cells = <0>;
	28	interrupts = <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>;
	29	interrupt-parent = <&gic>;
	30	clocks = <&spi0_lpcg 0>,
	31	<&spi0_lpcg 1>;
	32	clock-names = "per", "ipg";
	33	assigned-clocks = <&clk IMX_SC_R_SPI_0 IMX_SC_PM_CLK_PER>;
033f5e7e	34	assigned-clock-rates = <60000000>;
c4098885 FL	35	power-domains = <&pd IMX_SC_R_SPI_0>;
	36	status = "disabled";
	37	};
	38
	39	lpspi1: spi@5a010000 {
	40	compatible = "fsl,imx7ulp-spi";
	41	reg = <0x5a010000 0x10000>;
	42	#address-cells = <1>;
	43	#size-cells = <0>;
	44	interrupts = <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>;
	45	interrupt-parent = <&gic>;
	46	clocks = <&spi1_lpcg 0>,
	47	<&spi1_lpcg 1>;
	48	clock-names = "per", "ipg";
	49	assigned-clocks = <&clk IMX_SC_R_SPI_1 IMX_SC_PM_CLK_PER>;
	50	assigned-clock-rates = <60000000>;
	51	power-domains = <&pd IMX_SC_R_SPI_1>;
	52	status = "disabled";
	53	};
	54
	55	lpspi2: spi@5a020000 {
	56	compatible = "fsl,imx7ulp-spi";
	57	reg = <0x5a020000 0x10000>;
	58	#address-cells = <1>;
	59	#size-cells = <0>;
	60	interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>;
	61	interrupt-parent = <&gic>;
	62	clocks = <&spi2_lpcg 0>,
	63	<&spi2_lpcg 1>;
	64	clock-names = "per", "ipg";
	65	assigned-clocks = <&clk IMX_SC_R_SPI_2 IMX_SC_PM_CLK_PER>;
	66	assigned-clock-rates = <60000000>;
	67	power-domains = <&pd IMX_SC_R_SPI_2>;
	68	status = "disabled";
	69	};
	70
	71	lpspi3: spi@5a030000 {
	72	compatible = "fsl,imx7ulp-spi";
	73	reg = <0x5a030000 0x10000>;
	74	#address-cells = <1>;
	75	#size-cells = <0>;
	76	interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>;
	77	interrupt-parent = <&gic>;
	78	clocks = <&spi3_lpcg 0>,
	79	<&spi3_lpcg 1>;
	80	clock-names = "per", "ipg";
	81	assigned-clocks = <&clk IMX_SC_R_SPI_3 IMX_SC_PM_CLK_PER>;
	82	assigned-clock-rates = <60000000>;
	83	power-domains = <&pd IMX_SC_R_SPI_3>;
	84	status = "disabled";
	85	};
	86
35f4e9d7 DA	87	lpuart0: serial@5a060000 {
	88	reg = <0x5a060000 0x1000>;
	89	interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
	90	clocks = <&uart0_lpcg IMX_LPCG_CLK_4>,
	91	<&uart0_lpcg IMX_LPCG_CLK_0>;
	92	clock-names = "ipg", "baud";
ca50d776 SW	93	assigned-clocks = <&clk IMX_SC_R_UART_0 IMX_SC_PM_CLK_PER>;
ca50d776 SW	94	assigned-clock-rates = <80000000>;
35f4e9d7 DA	95	power-domains = <&pd IMX_SC_R_UART_0>;
	96	status = "disabled";
	97	};
	98
	99	lpuart1: serial@5a070000 {
	100	reg = <0x5a070000 0x1000>;
	101	interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
	102	clocks = <&uart1_lpcg IMX_LPCG_CLK_4>,
	103	<&uart1_lpcg IMX_LPCG_CLK_0>;
	104	clock-names = "ipg", "baud";
ca50d776 SW	105	assigned-clocks = <&clk IMX_SC_R_UART_1 IMX_SC_PM_CLK_PER>;
ca50d776 SW	106	assigned-clock-rates = <80000000>;
35f4e9d7 DA	107	power-domains = <&pd IMX_SC_R_UART_1>;
	108	status = "disabled";
	109	};
	110
	111	lpuart2: serial@5a080000 {
	112	reg = <0x5a080000 0x1000>;
	113	interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
	114	clocks = <&uart2_lpcg IMX_LPCG_CLK_4>,
	115	<&uart2_lpcg IMX_LPCG_CLK_0>;
	116	clock-names = "ipg", "baud";
ca50d776 SW	117	assigned-clocks = <&clk IMX_SC_R_UART_2 IMX_SC_PM_CLK_PER>;
ca50d776 SW	118	assigned-clock-rates = <80000000>;
35f4e9d7 DA	119	power-domains = <&pd IMX_SC_R_UART_2>;
	120	status = "disabled";
	121	};
	122
	123	lpuart3: serial@5a090000 {
	124	reg = <0x5a090000 0x1000>;
	125	interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
	126	clocks = <&uart3_lpcg IMX_LPCG_CLK_4>,
	127	<&uart3_lpcg IMX_LPCG_CLK_0>;
	128	clock-names = "ipg", "baud";
ca50d776 SW	129	assigned-clocks = <&clk IMX_SC_R_UART_3 IMX_SC_PM_CLK_PER>;
ca50d776 SW	130	assigned-clock-rates = <80000000>;
35f4e9d7 DA	131	power-domains = <&pd IMX_SC_R_UART_3>;
	132	status = "disabled";
	133	};
	134
f1d6a6b9 AS	135	adma_pwm: pwm@5a190000 {
	136	compatible = "fsl,imx8qxp-pwm", "fsl,imx27-pwm";
	137	reg = <0x5a190000 0x1000>;
	138	interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
	139	clocks = <&adma_pwm_lpcg 1>,
	140	<&adma_pwm_lpcg 0>;
	141	clock-names = "ipg", "per";
	142	assigned-clocks = <&clk IMX_SC_R_LCD_0_PWM_0 IMX_SC_PM_CLK_PER>;
	143	assigned-clock-rates = <24000000>;
	144	#pwm-cells = <2>;
	145	power-domains = <&pd IMX_SC_R_LCD_0_PWM_0>;
	146	};
	147
e4d7a330 FL	148	edma2: dma-controller@5a1f0000 {
	149	compatible = "fsl,imx8qm-edma";
	150	reg = <0x5a1f0000 0x170000>;
	151	#dma-cells = <3>;
	152	dma-channels = <16>;
	153	interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
	154	<GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
	155	<GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
	156	<GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
	157	<GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
	158	<GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
	159	<GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
	160	<GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
	161	<GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>,
	162	<GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>,
	163	<GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>,
	164	<GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH>,
	165	<GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>,
	166	<GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>,
	167	<GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>,
	168	<GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>;
	169	power-domains = <&pd IMX_SC_R_DMA_2_CH0>,
	170	<&pd IMX_SC_R_DMA_2_CH1>,
	171	<&pd IMX_SC_R_DMA_2_CH2>,
	172	<&pd IMX_SC_R_DMA_2_CH3>,
	173	<&pd IMX_SC_R_DMA_2_CH4>,
	174	<&pd IMX_SC_R_DMA_2_CH5>,
	175	<&pd IMX_SC_R_DMA_2_CH6>,
	176	<&pd IMX_SC_R_DMA_2_CH7>,
	177	<&pd IMX_SC_R_DMA_2_CH8>,
	178	<&pd IMX_SC_R_DMA_2_CH9>,
	179	<&pd IMX_SC_R_DMA_2_CH10>,
	180	<&pd IMX_SC_R_DMA_2_CH11>,
	181	<&pd IMX_SC_R_DMA_2_CH12>,
	182	<&pd IMX_SC_R_DMA_2_CH13>,
	183	<&pd IMX_SC_R_DMA_2_CH14>,
	184	<&pd IMX_SC_R_DMA_2_CH15>;
	185	};
	186
	187	edma3: dma-controller@5a9f0000 {
	188	compatible = "fsl,imx8qm-edma";
	189	reg = <0x5a9f0000 0x90000>;
	190	#dma-cells = <3>;
	191	dma-channels = <8>;
	192	interrupts = <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
	193	<GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
	194	<GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,
	195	<GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>,
	196	<GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>,
	197	<GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>,
	198	<GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>,
	199	<GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>;
	200	power-domains = <&pd IMX_SC_R_DMA_3_CH0>,
	201	<&pd IMX_SC_R_DMA_3_CH1>,
	202	<&pd IMX_SC_R_DMA_3_CH2>,
	203	<&pd IMX_SC_R_DMA_3_CH3>,
	204	<&pd IMX_SC_R_DMA_3_CH4>,
	205	<&pd IMX_SC_R_DMA_3_CH5>,
	206	<&pd IMX_SC_R_DMA_3_CH6>,
	207	<&pd IMX_SC_R_DMA_3_CH7>;
	208	};
	209
c4098885 FL	210	spi0_lpcg: clock-controller@5a400000 {
	211	compatible = "fsl,imx8qxp-lpcg";
	212	reg = <0x5a400000 0x10000>;
	213	#clock-cells = <1>;
	214	clocks = <&clk IMX_SC_R_SPI_0 IMX_SC_PM_CLK_PER>,
	215	<&dma_ipg_clk>;
	216	clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
	217	clock-output-names = "spi0_lpcg_clk",
	218	"spi0_lpcg_ipg_clk";
	219	power-domains = <&pd IMX_SC_R_SPI_0>;
	220	};
	221
	222	spi1_lpcg: clock-controller@5a410000 {
	223	compatible = "fsl,imx8qxp-lpcg";
	224	reg = <0x5a410000 0x10000>;
	225	#clock-cells = <1>;
	226	clocks = <&clk IMX_SC_R_SPI_1 IMX_SC_PM_CLK_PER>,
	227	<&dma_ipg_clk>;
	228	clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
	229	clock-output-names = "spi1_lpcg_clk",
	230	"spi1_lpcg_ipg_clk";
	231	power-domains = <&pd IMX_SC_R_SPI_1>;
	232	};
	233
	234	spi2_lpcg: clock-controller@5a420000 {
	235	compatible = "fsl,imx8qxp-lpcg";
	236	reg = <0x5a420000 0x10000>;
	237	#clock-cells = <1>;
	238	clocks = <&clk IMX_SC_R_SPI_2 IMX_SC_PM_CLK_PER>,
	239	<&dma_ipg_clk>;
	240	clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
	241	clock-output-names = "spi2_lpcg_clk",
	242	"spi2_lpcg_ipg_clk";
	243	power-domains = <&pd IMX_SC_R_SPI_2>;
	244	};
	245
	246	spi3_lpcg: clock-controller@5a430000 {
	247	compatible = "fsl,imx8qxp-lpcg";
	248	reg = <0x5a430000 0x10000>;
	249	#clock-cells = <1>;
	250	clocks = <&clk IMX_SC_R_SPI_3 IMX_SC_PM_CLK_PER>,
	251	<&dma_ipg_clk>;
	252	clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
	253	clock-output-names = "spi3_lpcg_clk",
	254	"spi3_lpcg_ipg_clk";
	255	power-domains = <&pd IMX_SC_R_SPI_3>;
	256	};
	257
35f4e9d7 DA	258	uart0_lpcg: clock-controller@5a460000 {
	259	compatible = "fsl,imx8qxp-lpcg";
	260	reg = <0x5a460000 0x10000>;
	261	#clock-cells = <1>;
	262	clocks = <&clk IMX_SC_R_UART_0 IMX_SC_PM_CLK_PER>,
	263	<&dma_ipg_clk>;
	264	clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
	265	clock-output-names = "uart0_lpcg_baud_clk",
	266	"uart0_lpcg_ipg_clk";
	267	power-domains = <&pd IMX_SC_R_UART_0>;
	268	};
	269
	270	uart1_lpcg: clock-controller@5a470000 {
	271	compatible = "fsl,imx8qxp-lpcg";
	272	reg = <0x5a470000 0x10000>;
	273	#clock-cells = <1>;
	274	clocks = <&clk IMX_SC_R_UART_1 IMX_SC_PM_CLK_PER>,
	275	<&dma_ipg_clk>;
	276	clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
	277	clock-output-names = "uart1_lpcg_baud_clk",
	278	"uart1_lpcg_ipg_clk";
	279	power-domains = <&pd IMX_SC_R_UART_1>;
	280	};
	281
	282	uart2_lpcg: clock-controller@5a480000 {
	283	compatible = "fsl,imx8qxp-lpcg";
	284	reg = <0x5a480000 0x10000>;
	285	#clock-cells = <1>;
	286	clocks = <&clk IMX_SC_R_UART_2 IMX_SC_PM_CLK_PER>,
	287	<&dma_ipg_clk>;
	288	clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
	289	clock-output-names = "uart2_lpcg_baud_clk",
	290	"uart2_lpcg_ipg_clk";
	291	power-domains = <&pd IMX_SC_R_UART_2>;
	292	};
	293
	294	uart3_lpcg: clock-controller@5a490000 {
	295	compatible = "fsl,imx8qxp-lpcg";
	296	reg = <0x5a490000 0x10000>;
	297	#clock-cells = <1>;
	298	clocks = <&clk IMX_SC_R_UART_3 IMX_SC_PM_CLK_PER>,
	299	<&dma_ipg_clk>;
	300	clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
	301	clock-output-names = "uart3_lpcg_baud_clk",
	302	"uart3_lpcg_ipg_clk";
	303	power-domains = <&pd IMX_SC_R_UART_3>;
	304	};
	305
f1d6a6b9 AS	306	adma_pwm_lpcg: clock-controller@5a590000 {
	307	compatible = "fsl,imx8qxp-lpcg";
	308	reg = <0x5a590000 0x10000>;
	309	#clock-cells = <1>;
	310	clocks = <&clk IMX_SC_R_LCD_0_PWM_0 IMX_SC_PM_CLK_PER>,
	311	<&dma_ipg_clk>;
	312	clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
	313	clock-output-names = "adma_pwm_lpcg_clk",
	314	"adma_pwm_lpcg_ipg_clk";
	315	power-domains = <&pd IMX_SC_R_LCD_0_PWM_0>;
	316	};
	317
35f4e9d7 DA	318	i2c0: i2c@5a800000 {
	319	reg = <0x5a800000 0x4000>;
	320	interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
b57f7d21 PF	321	clocks = <&i2c0_lpcg IMX_LPCG_CLK_0>,
	322	<&i2c0_lpcg IMX_LPCG_CLK_4>;
	323	clock-names = "per", "ipg";
35f4e9d7 DA	324	assigned-clocks = <&clk IMX_SC_R_I2C_0 IMX_SC_PM_CLK_PER>;
	325	assigned-clock-rates = <24000000>;
	326	power-domains = <&pd IMX_SC_R_I2C_0>;
	327	status = "disabled";
	328	};
	329
	330	i2c1: i2c@5a810000 {
	331	reg = <0x5a810000 0x4000>;
	332	interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
b57f7d21 PF	333	clocks = <&i2c1_lpcg IMX_LPCG_CLK_0>,
	334	<&i2c1_lpcg IMX_LPCG_CLK_4>;
	335	clock-names = "per", "ipg";
35f4e9d7 DA	336	assigned-clocks = <&clk IMX_SC_R_I2C_1 IMX_SC_PM_CLK_PER>;
	337	assigned-clock-rates = <24000000>;
	338	power-domains = <&pd IMX_SC_R_I2C_1>;
	339	status = "disabled";
	340	};
	341
	342	i2c2: i2c@5a820000 {
	343	reg = <0x5a820000 0x4000>;
	344	interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
b57f7d21 PF	345	clocks = <&i2c2_lpcg IMX_LPCG_CLK_0>,
	346	<&i2c2_lpcg IMX_LPCG_CLK_4>;
	347	clock-names = "per", "ipg";
35f4e9d7 DA	348	assigned-clocks = <&clk IMX_SC_R_I2C_2 IMX_SC_PM_CLK_PER>;
	349	assigned-clock-rates = <24000000>;
	350	power-domains = <&pd IMX_SC_R_I2C_2>;
	351	status = "disabled";
	352	};
	353
	354	i2c3: i2c@5a830000 {
	355	reg = <0x5a830000 0x4000>;
	356	interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
b57f7d21 PF	357	clocks = <&i2c3_lpcg IMX_LPCG_CLK_0>,
	358	<&i2c3_lpcg IMX_LPCG_CLK_4>;
	359	clock-names = "per", "ipg";
35f4e9d7 DA	360	assigned-clocks = <&clk IMX_SC_R_I2C_3 IMX_SC_PM_CLK_PER>;
	361	assigned-clock-rates = <24000000>;
	362	power-domains = <&pd IMX_SC_R_I2C_3>;
	363	status = "disabled";
	364	};
	365
1db044b2 FL	366	adc0: adc@5a880000 {
1db044b2 FL	367	compatible = "nxp,imx8qxp-adc";
b503c3c0	368	#io-channel-cells = <1>;
1db044b2 FL	369	reg = <0x5a880000 0x10000>;
	370	interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
	371	interrupt-parent = <&gic>;
	372	clocks = <&adc0_lpcg 0>,
	373	<&adc0_lpcg 1>;
	374	clock-names = "per", "ipg";
	375	assigned-clocks = <&clk IMX_SC_R_ADC_0 IMX_SC_PM_CLK_PER>;
	376	assigned-clock-rates = <24000000>;
	377	power-domains = <&pd IMX_SC_R_ADC_0>;
	378	status = "disabled";
	379	};
	380
	381	adc1: adc@5a890000 {
	382	compatible = "nxp,imx8qxp-adc";
b503c3c0	383	#io-channel-cells = <1>;
1db044b2 FL	384	reg = <0x5a890000 0x10000>;
	385	interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
	386	interrupt-parent = <&gic>;
	387	clocks = <&adc1_lpcg 0>,
	388	<&adc1_lpcg 1>;
	389	clock-names = "per", "ipg";
	390	assigned-clocks = <&clk IMX_SC_R_ADC_1 IMX_SC_PM_CLK_PER>;
	391	assigned-clock-rates = <24000000>;
	392	power-domains = <&pd IMX_SC_R_ADC_1>;
	393	status = "disabled";
	394	};
	395
5e7d5b02 JZ	396	flexcan1: can@5a8d0000 {
	397	compatible = "fsl,imx8qm-flexcan";
	398	reg = <0x5a8d0000 0x10000>;
	399	interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>;
	400	interrupt-parent = <&gic>;
	401	clocks = <&can0_lpcg 1>,
	402	<&can0_lpcg 0>;
	403	clock-names = "ipg", "per";
	404	assigned-clocks = <&clk IMX_SC_R_CAN_0 IMX_SC_PM_CLK_PER>;
	405	assigned-clock-rates = <40000000>;
	406	power-domains = <&pd IMX_SC_R_CAN_0>;
	407	/* SLSlice[4] */
	408	fsl,clk-source = /bits/ 8 <0>;
	409	fsl,scu-index = /bits/ 8 <0>;
	410	status = "disabled";
	411	};
	412
	413	flexcan2: can@5a8e0000 {
	414	compatible = "fsl,imx8qm-flexcan";
	415	reg = <0x5a8e0000 0x10000>;
	416	interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>;
	417	interrupt-parent = <&gic>;
	418	/* CAN0 clock and PD is shared among all CAN instances as
	419	* CAN1 shares CAN0's clock and to enable CAN0's clock it
	420	* has to be powered on.
	421	*/
	422	clocks = <&can0_lpcg 1>,
	423	<&can0_lpcg 0>;
	424	clock-names = "ipg", "per";
	425	assigned-clocks = <&clk IMX_SC_R_CAN_0 IMX_SC_PM_CLK_PER>;
	426	assigned-clock-rates = <40000000>;
	427	power-domains = <&pd IMX_SC_R_CAN_1>;
	428	/* SLSlice[4] */
	429	fsl,clk-source = /bits/ 8 <0>;
	430	fsl,scu-index = /bits/ 8 <1>;
	431	status = "disabled";
	432	};
	433
	434	flexcan3: can@5a8f0000 {
	435	compatible = "fsl,imx8qm-flexcan";
	436	reg = <0x5a8f0000 0x10000>;
	437	interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>;
	438	interrupt-parent = <&gic>;
	439	/* CAN0 clock and PD is shared among all CAN instances as
	440	* CAN2 shares CAN0's clock and to enable CAN0's clock it
	441	* has to be powered on.
	442	*/
	443	clocks = <&can0_lpcg 1>,
	444	<&can0_lpcg 0>;
	445	clock-names = "ipg", "per";
	446	assigned-clocks = <&clk IMX_SC_R_CAN_0 IMX_SC_PM_CLK_PER>;
	447	assigned-clock-rates = <40000000>;
	448	power-domains = <&pd IMX_SC_R_CAN_2>;
	449	/* SLSlice[4] */
	450	fsl,clk-source = /bits/ 8 <0>;
	451	fsl,scu-index = /bits/ 8 <2>;
	452	status = "disabled";
	453	};
	454
35f4e9d7 DA	455	i2c0_lpcg: clock-controller@5ac00000 {
	456	compatible = "fsl,imx8qxp-lpcg";
	457	reg = <0x5ac00000 0x10000>;
	458	#clock-cells = <1>;
	459	clocks = <&clk IMX_SC_R_I2C_0 IMX_SC_PM_CLK_PER>,
	460	<&dma_ipg_clk>;
	461	clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
	462	clock-output-names = "i2c0_lpcg_clk",
	463	"i2c0_lpcg_ipg_clk";
	464	power-domains = <&pd IMX_SC_R_I2C_0>;
	465	};
	466
	467	i2c1_lpcg: clock-controller@5ac10000 {
	468	compatible = "fsl,imx8qxp-lpcg";
	469	reg = <0x5ac10000 0x10000>;
	470	#clock-cells = <1>;
	471	clocks = <&clk IMX_SC_R_I2C_1 IMX_SC_PM_CLK_PER>,
	472	<&dma_ipg_clk>;
	473	clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
	474	clock-output-names = "i2c1_lpcg_clk",
	475	"i2c1_lpcg_ipg_clk";
	476	power-domains = <&pd IMX_SC_R_I2C_1>;
	477	};
	478
	479	i2c2_lpcg: clock-controller@5ac20000 {
	480	compatible = "fsl,imx8qxp-lpcg";
	481	reg = <0x5ac20000 0x10000>;
	482	#clock-cells = <1>;
	483	clocks = <&clk IMX_SC_R_I2C_2 IMX_SC_PM_CLK_PER>,
	484	<&dma_ipg_clk>;
	485	clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
	486	clock-output-names = "i2c2_lpcg_clk",
	487	"i2c2_lpcg_ipg_clk";
	488	power-domains = <&pd IMX_SC_R_I2C_2>;
	489	};
	490
	491	i2c3_lpcg: clock-controller@5ac30000 {
	492	compatible = "fsl,imx8qxp-lpcg";
	493	reg = <0x5ac30000 0x10000>;
	494	#clock-cells = <1>;
	495	clocks = <&clk IMX_SC_R_I2C_3 IMX_SC_PM_CLK_PER>,
	496	<&dma_ipg_clk>;
	497	clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
	498	clock-output-names = "i2c3_lpcg_clk",
	499	"i2c3_lpcg_ipg_clk";
	500	power-domains = <&pd IMX_SC_R_I2C_3>;
	501	};
1db044b2 FL	502
	503	adc0_lpcg: clock-controller@5ac80000 {
	504	compatible = "fsl,imx8qxp-lpcg";
	505	reg = <0x5ac80000 0x10000>;
	506	#clock-cells = <1>;
	507	clocks = <&clk IMX_SC_R_ADC_0 IMX_SC_PM_CLK_PER>,
	508	<&dma_ipg_clk>;
	509	clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
	510	clock-output-names = "adc0_lpcg_clk",
	511	"adc0_lpcg_ipg_clk";
	512	power-domains = <&pd IMX_SC_R_ADC_0>;
	513	};
	514
	515	adc1_lpcg: clock-controller@5ac90000 {
	516	compatible = "fsl,imx8qxp-lpcg";
	517	reg = <0x5ac90000 0x10000>;
	518	#clock-cells = <1>;
	519	clocks = <&clk IMX_SC_R_ADC_1 IMX_SC_PM_CLK_PER>,
	520	<&dma_ipg_clk>;
	521	clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
	522	clock-output-names = "adc1_lpcg_clk",
	523	"adc1_lpcg_ipg_clk";
	524	power-domains = <&pd IMX_SC_R_ADC_1>;
	525	};
5e7d5b02 JZ	526
	527	can0_lpcg: clock-controller@5acd0000 {
	528	compatible = "fsl,imx8qxp-lpcg";
	529	reg = <0x5acd0000 0x10000>;
	530	#clock-cells = <1>;
	531	clocks = <&clk IMX_SC_R_CAN_0 IMX_SC_PM_CLK_PER>,
	532	<&dma_ipg_clk>, <&dma_ipg_clk>;
	533	clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>;
	534	clock-output-names = "can0_lpcg_pe_clk",
	535	"can0_lpcg_ipg_clk",
	536	"can0_lpcg_chi_clk";
	537	power-domains = <&pd IMX_SC_R_CAN_0>;
	538	};
35f4e9d7	539	};