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1 | /* |
2 | * Device Tree Include file for Freescale Layerscape-2085A family SoC. | |
3 | * | |
4 | * Copyright (C) 2014, Freescale Semiconductor | |
5 | * | |
6 | * Bhupesh Sharma <bhupesh.sharma@freescale.com> | |
7 | * | |
8 | * This file is dual-licensed: you can use it either under the terms | |
9 | * of the GPLv2 or the X11 license, at your option. Note that this dual | |
10 | * licensing only applies to this file, and not this project as a | |
11 | * whole. | |
12 | * | |
13 | * a) This library is free software; you can redistribute it and/or | |
14 | * modify it under the terms of the GNU General Public License as | |
15 | * published by the Free Software Foundation; either version 2 of the | |
16 | * License, or (at your option) any later version. | |
17 | * | |
18 | * This library is distributed in the hope that it will be useful, | |
19 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
20 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
21 | * GNU General Public License for more details. | |
22 | * | |
23 | * You should have received a copy of the GNU General Public | |
24 | * License along with this library; if not, write to the Free | |
25 | * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, | |
26 | * MA 02110-1301 USA | |
27 | * | |
28 | * Or, alternatively, | |
29 | * | |
30 | * b) Permission is hereby granted, free of charge, to any person | |
31 | * obtaining a copy of this software and associated documentation | |
32 | * files (the "Software"), to deal in the Software without | |
33 | * restriction, including without limitation the rights to use, | |
34 | * copy, modify, merge, publish, distribute, sublicense, and/or | |
35 | * sell copies of the Software, and to permit persons to whom the | |
36 | * Software is furnished to do so, subject to the following | |
37 | * conditions: | |
38 | * | |
39 | * The above copyright notice and this permission notice shall be | |
40 | * included in all copies or substantial portions of the Software. | |
41 | * | |
42 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
43 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES | |
44 | * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
45 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT | |
46 | * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, | |
47 | * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
48 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
49 | * OTHER DEALINGS IN THE SOFTWARE. | |
50 | */ | |
51 | ||
52 | / { | |
53 | compatible = "fsl,ls2085a"; | |
54 | interrupt-parent = <&gic>; | |
55 | #address-cells = <2>; | |
56 | #size-cells = <2>; | |
57 | ||
58 | cpus { | |
59 | #address-cells = <2>; | |
60 | #size-cells = <0>; | |
61 | ||
62 | /* | |
63 | * We expect the enable-method for cpu's to be "psci", but this | |
64 | * is dependent on the SoC FW, which will fill this in. | |
65 | * | |
66 | * Currently supported enable-method is psci v0.2 | |
67 | */ | |
68 | ||
69 | /* We have 4 clusters having 2 Cortex-A57 cores each */ | |
70 | cpu@0 { | |
71 | device_type = "cpu"; | |
72 | compatible = "arm,cortex-a57"; | |
73 | reg = <0x0 0x0>; | |
74 | }; | |
75 | ||
76 | cpu@1 { | |
77 | device_type = "cpu"; | |
78 | compatible = "arm,cortex-a57"; | |
79 | reg = <0x0 0x1>; | |
80 | }; | |
81 | ||
82 | cpu@100 { | |
83 | device_type = "cpu"; | |
84 | compatible = "arm,cortex-a57"; | |
85 | reg = <0x0 0x100>; | |
86 | }; | |
87 | ||
88 | cpu@101 { | |
89 | device_type = "cpu"; | |
90 | compatible = "arm,cortex-a57"; | |
91 | reg = <0x0 0x101>; | |
92 | }; | |
93 | ||
94 | cpu@200 { | |
95 | device_type = "cpu"; | |
96 | compatible = "arm,cortex-a57"; | |
97 | reg = <0x0 0x200>; | |
98 | }; | |
99 | ||
100 | cpu@201 { | |
101 | device_type = "cpu"; | |
102 | compatible = "arm,cortex-a57"; | |
103 | reg = <0x0 0x201>; | |
104 | }; | |
105 | ||
106 | cpu@300 { | |
107 | device_type = "cpu"; | |
108 | compatible = "arm,cortex-a57"; | |
109 | reg = <0x0 0x300>; | |
110 | }; | |
111 | ||
112 | cpu@301 { | |
113 | device_type = "cpu"; | |
114 | compatible = "arm,cortex-a57"; | |
115 | reg = <0x0 0x301>; | |
116 | }; | |
117 | }; | |
118 | ||
119 | memory@80000000 { | |
120 | device_type = "memory"; | |
121 | reg = <0x00000000 0x80000000 0 0x80000000>; | |
122 | /* DRAM space - 1, size : 2 GB DRAM */ | |
123 | }; | |
124 | ||
125 | gic: interrupt-controller@6000000 { | |
126 | compatible = "arm,gic-v3"; | |
127 | reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */ | |
128 | <0x0 0x06100000 0 0x100000>; /* GICR (RD_base + SGI_base) */ | |
129 | #interrupt-cells = <3>; | |
130 | interrupt-controller; | |
131 | interrupts = <1 9 0x4>; | |
132 | }; | |
133 | ||
134 | timer { | |
135 | compatible = "arm,armv8-timer"; | |
136 | interrupts = <1 13 0x8>, /* Physical Secure PPI, active-low */ | |
137 | <1 14 0x8>, /* Physical Non-Secure PPI, active-low */ | |
138 | <1 11 0x8>, /* Virtual PPI, active-low */ | |
139 | <1 10 0x8>; /* Hypervisor PPI, active-low */ | |
140 | }; | |
141 | ||
142 | serial0: serial@21c0500 { | |
143 | device_type = "serial"; | |
144 | compatible = "fsl,ns16550", "ns16550a"; | |
145 | reg = <0x0 0x21c0500 0x0 0x100>; | |
146 | clock-frequency = <0>; /* Updated by bootloader */ | |
147 | interrupts = <0 32 0x1>; /* edge triggered */ | |
148 | }; | |
149 | ||
150 | serial1: serial@21c0600 { | |
151 | device_type = "serial"; | |
152 | compatible = "fsl,ns16550", "ns16550a"; | |
153 | reg = <0x0 0x21c0600 0x0 0x100>; | |
154 | clock-frequency = <0>; /* Updated by bootloader */ | |
155 | interrupts = <0 32 0x1>; /* edge triggered */ | |
156 | }; | |
157 | ||
158 | fsl_mc: fsl-mc@80c000000 { | |
159 | compatible = "fsl,qoriq-mc"; | |
160 | reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */ | |
161 | <0x00000000 0x08340000 0 0x40000>; /* MC control reg */ | |
162 | }; | |
163 | }; |