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747c84d0 | 1 | /* |
f43a4b85 | 2 | * Device Tree Include file for Freescale Layerscape-2080A family SoC. |
747c84d0 | 3 | * |
f43a4b85 | 4 | * Copyright (C) 2014-2015, Freescale Semiconductor |
747c84d0 BS |
5 | * |
6 | * Bhupesh Sharma <bhupesh.sharma@freescale.com> | |
7 | * | |
8 | * This file is dual-licensed: you can use it either under the terms | |
9 | * of the GPLv2 or the X11 license, at your option. Note that this dual | |
10 | * licensing only applies to this file, and not this project as a | |
11 | * whole. | |
12 | * | |
13 | * a) This library is free software; you can redistribute it and/or | |
14 | * modify it under the terms of the GNU General Public License as | |
15 | * published by the Free Software Foundation; either version 2 of the | |
16 | * License, or (at your option) any later version. | |
17 | * | |
18 | * This library is distributed in the hope that it will be useful, | |
19 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
20 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
21 | * GNU General Public License for more details. | |
22 | * | |
747c84d0 BS |
23 | * Or, alternatively, |
24 | * | |
25 | * b) Permission is hereby granted, free of charge, to any person | |
26 | * obtaining a copy of this software and associated documentation | |
27 | * files (the "Software"), to deal in the Software without | |
28 | * restriction, including without limitation the rights to use, | |
29 | * copy, modify, merge, publish, distribute, sublicense, and/or | |
30 | * sell copies of the Software, and to permit persons to whom the | |
31 | * Software is furnished to do so, subject to the following | |
32 | * conditions: | |
33 | * | |
34 | * The above copyright notice and this permission notice shall be | |
35 | * included in all copies or substantial portions of the Software. | |
36 | * | |
37 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
38 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES | |
39 | * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
40 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT | |
41 | * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, | |
42 | * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
43 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
44 | * OTHER DEALINGS IN THE SOFTWARE. | |
45 | */ | |
46 | ||
47 | / { | |
f43a4b85 | 48 | compatible = "fsl,ls2080a"; |
747c84d0 BS |
49 | interrupt-parent = <&gic>; |
50 | #address-cells = <2>; | |
51 | #size-cells = <2>; | |
52 | ||
53 | cpus { | |
54 | #address-cells = <2>; | |
55 | #size-cells = <0>; | |
56 | ||
57 | /* | |
58 | * We expect the enable-method for cpu's to be "psci", but this | |
59 | * is dependent on the SoC FW, which will fill this in. | |
60 | * | |
61 | * Currently supported enable-method is psci v0.2 | |
62 | */ | |
63 | ||
64 | /* We have 4 clusters having 2 Cortex-A57 cores each */ | |
65 | cpu@0 { | |
66 | device_type = "cpu"; | |
67 | compatible = "arm,cortex-a57"; | |
68 | reg = <0x0 0x0>; | |
5461597f | 69 | clocks = <&clockgen 1 0>; |
747c84d0 BS |
70 | }; |
71 | ||
72 | cpu@1 { | |
73 | device_type = "cpu"; | |
74 | compatible = "arm,cortex-a57"; | |
75 | reg = <0x0 0x1>; | |
5461597f | 76 | clocks = <&clockgen 1 0>; |
747c84d0 BS |
77 | }; |
78 | ||
79 | cpu@100 { | |
80 | device_type = "cpu"; | |
81 | compatible = "arm,cortex-a57"; | |
82 | reg = <0x0 0x100>; | |
5461597f | 83 | clocks = <&clockgen 1 1>; |
747c84d0 BS |
84 | }; |
85 | ||
86 | cpu@101 { | |
87 | device_type = "cpu"; | |
88 | compatible = "arm,cortex-a57"; | |
89 | reg = <0x0 0x101>; | |
5461597f | 90 | clocks = <&clockgen 1 1>; |
747c84d0 BS |
91 | }; |
92 | ||
93 | cpu@200 { | |
94 | device_type = "cpu"; | |
95 | compatible = "arm,cortex-a57"; | |
96 | reg = <0x0 0x200>; | |
5461597f | 97 | clocks = <&clockgen 1 2>; |
747c84d0 BS |
98 | }; |
99 | ||
100 | cpu@201 { | |
101 | device_type = "cpu"; | |
102 | compatible = "arm,cortex-a57"; | |
103 | reg = <0x0 0x201>; | |
5461597f | 104 | clocks = <&clockgen 1 2>; |
747c84d0 BS |
105 | }; |
106 | ||
107 | cpu@300 { | |
108 | device_type = "cpu"; | |
109 | compatible = "arm,cortex-a57"; | |
110 | reg = <0x0 0x300>; | |
5461597f | 111 | clocks = <&clockgen 1 3>; |
747c84d0 BS |
112 | }; |
113 | ||
114 | cpu@301 { | |
115 | device_type = "cpu"; | |
116 | compatible = "arm,cortex-a57"; | |
117 | reg = <0x0 0x301>; | |
5461597f | 118 | clocks = <&clockgen 1 3>; |
747c84d0 BS |
119 | }; |
120 | }; | |
121 | ||
122 | memory@80000000 { | |
123 | device_type = "memory"; | |
124 | reg = <0x00000000 0x80000000 0 0x80000000>; | |
125 | /* DRAM space - 1, size : 2 GB DRAM */ | |
126 | }; | |
127 | ||
5461597f BS |
128 | sysclk: sysclk { |
129 | compatible = "fixed-clock"; | |
130 | #clock-cells = <0>; | |
131 | clock-frequency = <100000000>; | |
132 | clock-output-names = "sysclk"; | |
133 | }; | |
134 | ||
747c84d0 BS |
135 | gic: interrupt-controller@6000000 { |
136 | compatible = "arm,gic-v3"; | |
137 | reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */ | |
5461597f BS |
138 | <0x0 0x06100000 0 0x100000>, /* GICR (RD_base + SGI_base) */ |
139 | <0x0 0x0c0c0000 0 0x2000>, /* GICC */ | |
140 | <0x0 0x0c0d0000 0 0x1000>, /* GICH */ | |
141 | <0x0 0x0c0e0000 0 0x20000>; /* GICV */ | |
747c84d0 | 142 | #interrupt-cells = <3>; |
5461597f BS |
143 | #address-cells = <2>; |
144 | #size-cells = <2>; | |
145 | ranges; | |
747c84d0 BS |
146 | interrupt-controller; |
147 | interrupts = <1 9 0x4>; | |
5461597f BS |
148 | |
149 | its: gic-its@6020000 { | |
150 | compatible = "arm,gic-v3-its"; | |
151 | msi-controller; | |
152 | reg = <0x0 0x6020000 0 0x20000>; | |
153 | }; | |
747c84d0 BS |
154 | }; |
155 | ||
c7a5675f GR |
156 | rstcr: syscon@1e60000 { |
157 | compatible = "fsl,ls2080a-rstcr", "syscon"; | |
158 | reg = <0x0 0x1e60000 0x0 0x4>; | |
159 | }; | |
160 | ||
161 | reboot { | |
162 | compatible ="syscon-reboot"; | |
163 | regmap = <&rstcr>; | |
164 | offset = <0x0>; | |
165 | mask = <0x2>; | |
166 | }; | |
167 | ||
747c84d0 BS |
168 | timer { |
169 | compatible = "arm,armv8-timer"; | |
170 | interrupts = <1 13 0x8>, /* Physical Secure PPI, active-low */ | |
171 | <1 14 0x8>, /* Physical Non-Secure PPI, active-low */ | |
172 | <1 11 0x8>, /* Virtual PPI, active-low */ | |
173 | <1 10 0x8>; /* Hypervisor PPI, active-low */ | |
174 | }; | |
175 | ||
5461597f BS |
176 | pmu { |
177 | compatible = "arm,armv8-pmuv3"; | |
178 | interrupts = <1 7 0x8>; /* PMU PPI, Level low type */ | |
747c84d0 BS |
179 | }; |
180 | ||
5461597f BS |
181 | soc { |
182 | compatible = "simple-bus"; | |
183 | #address-cells = <2>; | |
184 | #size-cells = <2>; | |
185 | ranges; | |
186 | ||
187 | clockgen: clocking@1300000 { | |
188 | compatible = "fsl,ls2080a-clockgen"; | |
189 | reg = <0 0x1300000 0 0xa0000>; | |
190 | #clock-cells = <2>; | |
191 | clocks = <&sysclk>; | |
192 | }; | |
193 | ||
194 | serial0: serial@21c0500 { | |
195 | compatible = "fsl,ns16550", "ns16550a"; | |
196 | reg = <0x0 0x21c0500 0x0 0x100>; | |
197 | clocks = <&clockgen 4 3>; | |
198 | interrupts = <0 32 0x4>; /* Level high type */ | |
199 | }; | |
200 | ||
201 | serial1: serial@21c0600 { | |
202 | compatible = "fsl,ns16550", "ns16550a"; | |
203 | reg = <0x0 0x21c0600 0x0 0x100>; | |
204 | clocks = <&clockgen 4 3>; | |
205 | interrupts = <0 32 0x4>; /* Level high type */ | |
206 | }; | |
207 | ||
d50a8b48 BS |
208 | cluster1_core0_watchdog: wdt@c000000 { |
209 | compatible = "arm,sp805-wdt", "arm,primecell"; | |
210 | reg = <0x0 0xc000000 0x0 0x1000>; | |
211 | clocks = <&clockgen 4 3>, <&clockgen 4 3>; | |
212 | clock-names = "apb_pclk", "wdog_clk"; | |
213 | }; | |
214 | ||
215 | cluster1_core1_watchdog: wdt@c010000 { | |
216 | compatible = "arm,sp805-wdt", "arm,primecell"; | |
217 | reg = <0x0 0xc010000 0x0 0x1000>; | |
218 | clocks = <&clockgen 4 3>, <&clockgen 4 3>; | |
219 | clock-names = "apb_pclk", "wdog_clk"; | |
220 | }; | |
221 | ||
222 | cluster2_core0_watchdog: wdt@c100000 { | |
223 | compatible = "arm,sp805-wdt", "arm,primecell"; | |
224 | reg = <0x0 0xc100000 0x0 0x1000>; | |
225 | clocks = <&clockgen 4 3>, <&clockgen 4 3>; | |
226 | clock-names = "apb_pclk", "wdog_clk"; | |
227 | }; | |
228 | ||
229 | cluster2_core1_watchdog: wdt@c110000 { | |
230 | compatible = "arm,sp805-wdt", "arm,primecell"; | |
231 | reg = <0x0 0xc110000 0x0 0x1000>; | |
232 | clocks = <&clockgen 4 3>, <&clockgen 4 3>; | |
233 | clock-names = "apb_pclk", "wdog_clk"; | |
234 | }; | |
235 | ||
236 | cluster3_core0_watchdog: wdt@c200000 { | |
237 | compatible = "arm,sp805-wdt", "arm,primecell"; | |
238 | reg = <0x0 0xc200000 0x0 0x1000>; | |
239 | clocks = <&clockgen 4 3>, <&clockgen 4 3>; | |
240 | clock-names = "apb_pclk", "wdog_clk"; | |
241 | }; | |
242 | ||
243 | cluster3_core1_watchdog: wdt@c210000 { | |
244 | compatible = "arm,sp805-wdt", "arm,primecell"; | |
245 | reg = <0x0 0xc210000 0x0 0x1000>; | |
246 | clocks = <&clockgen 4 3>, <&clockgen 4 3>; | |
247 | clock-names = "apb_pclk", "wdog_clk"; | |
248 | }; | |
249 | ||
250 | cluster4_core0_watchdog: wdt@c300000 { | |
251 | compatible = "arm,sp805-wdt", "arm,primecell"; | |
252 | reg = <0x0 0xc300000 0x0 0x1000>; | |
253 | clocks = <&clockgen 4 3>, <&clockgen 4 3>; | |
254 | clock-names = "apb_pclk", "wdog_clk"; | |
255 | }; | |
256 | ||
257 | cluster4_core1_watchdog: wdt@c310000 { | |
258 | compatible = "arm,sp805-wdt", "arm,primecell"; | |
259 | reg = <0x0 0xc310000 0x0 0x1000>; | |
260 | clocks = <&clockgen 4 3>, <&clockgen 4 3>; | |
261 | clock-names = "apb_pclk", "wdog_clk"; | |
262 | }; | |
263 | ||
5461597f BS |
264 | fsl_mc: fsl-mc@80c000000 { |
265 | compatible = "fsl,qoriq-mc"; | |
266 | reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */ | |
267 | <0x00000000 0x08340000 0 0x40000>; /* MC control reg */ | |
268 | }; | |
747c84d0 | 269 | |
5461597f BS |
270 | smmu: iommu@5000000 { |
271 | compatible = "arm,mmu-500"; | |
272 | reg = <0 0x5000000 0 0x800000>; | |
273 | #global-interrupts = <12>; | |
274 | interrupts = <0 13 4>, /* global secure fault */ | |
275 | <0 14 4>, /* combined secure interrupt */ | |
276 | <0 15 4>, /* global non-secure fault */ | |
277 | <0 16 4>, /* combined non-secure interrupt */ | |
278 | /* performance counter interrupts 0-7 */ | |
279 | <0 211 4>, <0 212 4>, | |
280 | <0 213 4>, <0 214 4>, | |
281 | <0 215 4>, <0 216 4>, | |
282 | <0 217 4>, <0 218 4>, | |
283 | /* per context interrupt, 64 interrupts */ | |
284 | <0 146 4>, <0 147 4>, | |
285 | <0 148 4>, <0 149 4>, | |
286 | <0 150 4>, <0 151 4>, | |
287 | <0 152 4>, <0 153 4>, | |
288 | <0 154 4>, <0 155 4>, | |
289 | <0 156 4>, <0 157 4>, | |
290 | <0 158 4>, <0 159 4>, | |
291 | <0 160 4>, <0 161 4>, | |
292 | <0 162 4>, <0 163 4>, | |
293 | <0 164 4>, <0 165 4>, | |
294 | <0 166 4>, <0 167 4>, | |
295 | <0 168 4>, <0 169 4>, | |
296 | <0 170 4>, <0 171 4>, | |
297 | <0 172 4>, <0 173 4>, | |
298 | <0 174 4>, <0 175 4>, | |
299 | <0 176 4>, <0 177 4>, | |
300 | <0 178 4>, <0 179 4>, | |
301 | <0 180 4>, <0 181 4>, | |
302 | <0 182 4>, <0 183 4>, | |
303 | <0 184 4>, <0 185 4>, | |
304 | <0 186 4>, <0 187 4>, | |
305 | <0 188 4>, <0 189 4>, | |
306 | <0 190 4>, <0 191 4>, | |
307 | <0 192 4>, <0 193 4>, | |
308 | <0 194 4>, <0 195 4>, | |
309 | <0 196 4>, <0 197 4>, | |
310 | <0 198 4>, <0 199 4>, | |
311 | <0 200 4>, <0 201 4>, | |
312 | <0 202 4>, <0 203 4>, | |
313 | <0 204 4>, <0 205 4>, | |
314 | <0 206 4>, <0 207 4>, | |
315 | <0 208 4>, <0 209 4>; | |
316 | mmu-masters = <&fsl_mc 0x300 0>; | |
317 | }; | |
318 | ||
319 | dspi: dspi@2100000 { | |
320 | status = "disabled"; | |
b3f85aba | 321 | compatible = "fsl,ls2080a-dspi", "fsl,ls2085a-dspi"; |
5461597f BS |
322 | #address-cells = <1>; |
323 | #size-cells = <0>; | |
324 | reg = <0x0 0x2100000 0x0 0x10000>; | |
325 | interrupts = <0 26 0x4>; /* Level high type */ | |
326 | clocks = <&clockgen 4 3>; | |
327 | clock-names = "dspi"; | |
328 | spi-num-chipselects = <5>; | |
329 | bus-num = <0>; | |
330 | }; | |
331 | ||
332 | esdhc: esdhc@2140000 { | |
333 | status = "disabled"; | |
334 | compatible = "fsl,ls2080a-esdhc", "fsl,esdhc"; | |
335 | reg = <0x0 0x2140000 0x0 0x10000>; | |
336 | interrupts = <0 28 0x4>; /* Level high type */ | |
337 | clock-frequency = <0>; /* Updated by bootloader */ | |
338 | voltage-ranges = <1800 1800 3300 3300>; | |
339 | sdhci,auto-cmd12; | |
2dd2e4d1 | 340 | little-endian; |
5461597f BS |
341 | bus-width = <4>; |
342 | }; | |
343 | ||
344 | gpio0: gpio@2300000 { | |
345 | compatible = "fsl,qoriq-gpio"; | |
346 | reg = <0x0 0x2300000 0x0 0x10000>; | |
347 | interrupts = <0 36 0x4>; /* Level high type */ | |
348 | gpio-controller; | |
65347783 | 349 | little-endian; |
5461597f BS |
350 | #gpio-cells = <2>; |
351 | interrupt-controller; | |
352 | #interrupt-cells = <2>; | |
353 | }; | |
354 | ||
355 | gpio1: gpio@2310000 { | |
356 | compatible = "fsl,qoriq-gpio"; | |
357 | reg = <0x0 0x2310000 0x0 0x10000>; | |
358 | interrupts = <0 36 0x4>; /* Level high type */ | |
359 | gpio-controller; | |
65347783 | 360 | little-endian; |
5461597f BS |
361 | #gpio-cells = <2>; |
362 | interrupt-controller; | |
363 | #interrupt-cells = <2>; | |
364 | }; | |
365 | ||
366 | gpio2: gpio@2320000 { | |
367 | compatible = "fsl,qoriq-gpio"; | |
368 | reg = <0x0 0x2320000 0x0 0x10000>; | |
369 | interrupts = <0 37 0x4>; /* Level high type */ | |
370 | gpio-controller; | |
65347783 | 371 | little-endian; |
5461597f BS |
372 | #gpio-cells = <2>; |
373 | interrupt-controller; | |
374 | #interrupt-cells = <2>; | |
375 | }; | |
376 | ||
377 | gpio3: gpio@2330000 { | |
378 | compatible = "fsl,qoriq-gpio"; | |
379 | reg = <0x0 0x2330000 0x0 0x10000>; | |
380 | interrupts = <0 37 0x4>; /* Level high type */ | |
381 | gpio-controller; | |
65347783 | 382 | little-endian; |
5461597f BS |
383 | #gpio-cells = <2>; |
384 | interrupt-controller; | |
385 | #interrupt-cells = <2>; | |
386 | }; | |
387 | ||
388 | i2c0: i2c@2000000 { | |
389 | status = "disabled"; | |
390 | compatible = "fsl,vf610-i2c"; | |
391 | #address-cells = <1>; | |
392 | #size-cells = <0>; | |
393 | reg = <0x0 0x2000000 0x0 0x10000>; | |
394 | interrupts = <0 34 0x4>; /* Level high type */ | |
395 | clock-names = "i2c"; | |
396 | clocks = <&clockgen 4 3>; | |
397 | }; | |
398 | ||
399 | i2c1: i2c@2010000 { | |
400 | status = "disabled"; | |
401 | compatible = "fsl,vf610-i2c"; | |
402 | #address-cells = <1>; | |
403 | #size-cells = <0>; | |
404 | reg = <0x0 0x2010000 0x0 0x10000>; | |
405 | interrupts = <0 34 0x4>; /* Level high type */ | |
406 | clock-names = "i2c"; | |
407 | clocks = <&clockgen 4 3>; | |
408 | }; | |
409 | ||
410 | i2c2: i2c@2020000 { | |
411 | status = "disabled"; | |
412 | compatible = "fsl,vf610-i2c"; | |
413 | #address-cells = <1>; | |
414 | #size-cells = <0>; | |
415 | reg = <0x0 0x2020000 0x0 0x10000>; | |
416 | interrupts = <0 35 0x4>; /* Level high type */ | |
417 | clock-names = "i2c"; | |
418 | clocks = <&clockgen 4 3>; | |
419 | }; | |
420 | ||
421 | i2c3: i2c@2030000 { | |
422 | status = "disabled"; | |
423 | compatible = "fsl,vf610-i2c"; | |
424 | #address-cells = <1>; | |
425 | #size-cells = <0>; | |
426 | reg = <0x0 0x2030000 0x0 0x10000>; | |
427 | interrupts = <0 35 0x4>; /* Level high type */ | |
428 | clock-names = "i2c"; | |
429 | clocks = <&clockgen 4 3>; | |
430 | }; | |
431 | ||
432 | ifc: ifc@2240000 { | |
433 | compatible = "fsl,ifc", "simple-bus"; | |
434 | reg = <0x0 0x2240000 0x0 0x20000>; | |
435 | interrupts = <0 21 0x4>; /* Level high type */ | |
436 | little-endian; | |
437 | #address-cells = <2>; | |
438 | #size-cells = <1>; | |
439 | ||
440 | ranges = <0 0 0x5 0x80000000 0x08000000 | |
441 | 2 0 0x5 0x30000000 0x00010000 | |
442 | 3 0 0x5 0x20000000 0x00010000>; | |
443 | }; | |
444 | ||
445 | qspi: quadspi@20c0000 { | |
446 | status = "disabled"; | |
b3f85aba | 447 | compatible = "fsl,ls2080a-qspi", "fsl,ls1021a-qspi"; |
5461597f BS |
448 | #address-cells = <1>; |
449 | #size-cells = <0>; | |
450 | reg = <0x0 0x20c0000 0x0 0x10000>, | |
451 | <0x0 0x20000000 0x0 0x10000000>; | |
452 | reg-names = "QuadSPI", "QuadSPI-memory"; | |
453 | interrupts = <0 25 0x4>; /* Level high type */ | |
454 | clocks = <&clockgen 4 3>, <&clockgen 4 3>; | |
455 | clock-names = "qspi_en", "qspi"; | |
456 | }; | |
457 | ||
458 | pcie@3400000 { | |
f21a3c7d ML |
459 | compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie", |
460 | "snps,dw-pcie"; | |
5461597f BS |
461 | reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ |
462 | 0x10 0x00000000 0x0 0x00002000>; /* configuration space */ | |
463 | reg-names = "regs", "config"; | |
464 | interrupts = <0 108 0x4>; /* Level high type */ | |
465 | interrupt-names = "intr"; | |
466 | #address-cells = <3>; | |
467 | #size-cells = <2>; | |
468 | device_type = "pci"; | |
469 | num-lanes = <4>; | |
470 | bus-range = <0x0 0xff>; | |
471 | ranges = <0x81000000 0x0 0x00000000 0x10 0x00010000 0x0 0x00010000 /* downstream I/O */ | |
472 | 0x82000000 0x0 0x40000000 0x10 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ | |
473 | msi-parent = <&its>; | |
474 | #interrupt-cells = <1>; | |
475 | interrupt-map-mask = <0 0 0 7>; | |
476 | interrupt-map = <0000 0 0 1 &gic 0 0 0 109 4>, | |
477 | <0000 0 0 2 &gic 0 0 0 110 4>, | |
478 | <0000 0 0 3 &gic 0 0 0 111 4>, | |
479 | <0000 0 0 4 &gic 0 0 0 112 4>; | |
480 | }; | |
481 | ||
482 | pcie@3500000 { | |
f21a3c7d ML |
483 | compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie", |
484 | "snps,dw-pcie"; | |
5461597f BS |
485 | reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */ |
486 | 0x12 0x00000000 0x0 0x00002000>; /* configuration space */ | |
487 | reg-names = "regs", "config"; | |
488 | interrupts = <0 113 0x4>; /* Level high type */ | |
489 | interrupt-names = "intr"; | |
490 | #address-cells = <3>; | |
491 | #size-cells = <2>; | |
492 | device_type = "pci"; | |
493 | num-lanes = <4>; | |
494 | bus-range = <0x0 0xff>; | |
495 | ranges = <0x81000000 0x0 0x00000000 0x12 0x00010000 0x0 0x00010000 /* downstream I/O */ | |
496 | 0x82000000 0x0 0x40000000 0x12 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ | |
497 | msi-parent = <&its>; | |
498 | #interrupt-cells = <1>; | |
499 | interrupt-map-mask = <0 0 0 7>; | |
500 | interrupt-map = <0000 0 0 1 &gic 0 0 0 114 4>, | |
501 | <0000 0 0 2 &gic 0 0 0 115 4>, | |
502 | <0000 0 0 3 &gic 0 0 0 116 4>, | |
503 | <0000 0 0 4 &gic 0 0 0 117 4>; | |
504 | }; | |
505 | ||
506 | pcie@3600000 { | |
f21a3c7d ML |
507 | compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie", |
508 | "snps,dw-pcie"; | |
5461597f BS |
509 | reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */ |
510 | 0x14 0x00000000 0x0 0x00002000>; /* configuration space */ | |
511 | reg-names = "regs", "config"; | |
512 | interrupts = <0 118 0x4>; /* Level high type */ | |
513 | interrupt-names = "intr"; | |
514 | #address-cells = <3>; | |
515 | #size-cells = <2>; | |
516 | device_type = "pci"; | |
517 | num-lanes = <8>; | |
518 | bus-range = <0x0 0xff>; | |
519 | ranges = <0x81000000 0x0 0x00000000 0x14 0x00010000 0x0 0x00010000 /* downstream I/O */ | |
520 | 0x82000000 0x0 0x40000000 0x14 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ | |
521 | msi-parent = <&its>; | |
522 | #interrupt-cells = <1>; | |
523 | interrupt-map-mask = <0 0 0 7>; | |
524 | interrupt-map = <0000 0 0 1 &gic 0 0 0 119 4>, | |
525 | <0000 0 0 2 &gic 0 0 0 120 4>, | |
526 | <0000 0 0 3 &gic 0 0 0 121 4>, | |
527 | <0000 0 0 4 &gic 0 0 0 122 4>; | |
528 | }; | |
529 | ||
530 | pcie@3700000 { | |
f21a3c7d ML |
531 | compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie", |
532 | "snps,dw-pcie"; | |
5461597f BS |
533 | reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */ |
534 | 0x16 0x00000000 0x0 0x00002000>; /* configuration space */ | |
535 | reg-names = "regs", "config"; | |
536 | interrupts = <0 123 0x4>; /* Level high type */ | |
537 | interrupt-names = "intr"; | |
538 | #address-cells = <3>; | |
539 | #size-cells = <2>; | |
540 | device_type = "pci"; | |
541 | num-lanes = <4>; | |
542 | bus-range = <0x0 0xff>; | |
543 | ranges = <0x81000000 0x0 0x00000000 0x16 0x00010000 0x0 0x00010000 /* downstream I/O */ | |
544 | 0x82000000 0x0 0x40000000 0x16 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ | |
545 | msi-parent = <&its>; | |
546 | #interrupt-cells = <1>; | |
547 | interrupt-map-mask = <0 0 0 7>; | |
548 | interrupt-map = <0000 0 0 1 &gic 0 0 0 124 4>, | |
549 | <0000 0 0 2 &gic 0 0 0 125 4>, | |
550 | <0000 0 0 3 &gic 0 0 0 126 4>, | |
551 | <0000 0 0 4 &gic 0 0 0 127 4>; | |
552 | }; | |
553 | ||
554 | sata0: sata@3200000 { | |
555 | status = "disabled"; | |
556 | compatible = "fsl,ls2080a-ahci"; | |
557 | reg = <0x0 0x3200000 0x0 0x10000>; | |
558 | interrupts = <0 133 0x4>; /* Level high type */ | |
559 | clocks = <&clockgen 4 3>; | |
560 | }; | |
561 | ||
562 | sata1: sata@3210000 { | |
563 | status = "disabled"; | |
564 | compatible = "fsl,ls2080a-ahci"; | |
565 | reg = <0x0 0x3210000 0x0 0x10000>; | |
566 | interrupts = <0 136 0x4>; /* Level high type */ | |
567 | clocks = <&clockgen 4 3>; | |
568 | }; | |
569 | ||
570 | usb0: usb3@3100000 { | |
571 | status = "disabled"; | |
572 | compatible = "snps,dwc3"; | |
573 | reg = <0x0 0x3100000 0x0 0x10000>; | |
574 | interrupts = <0 80 0x4>; /* Level high type */ | |
575 | dr_mode = "host"; | |
a9cefa36 | 576 | snps,quirk-frame-length-adjustment = <0x20>; |
5461597f BS |
577 | }; |
578 | ||
579 | usb1: usb3@3110000 { | |
580 | status = "disabled"; | |
581 | compatible = "snps,dwc3"; | |
582 | reg = <0x0 0x3110000 0x0 0x10000>; | |
583 | interrupts = <0 81 0x4>; /* Level high type */ | |
584 | dr_mode = "host"; | |
a9cefa36 | 585 | snps,quirk-frame-length-adjustment = <0x20>; |
5461597f BS |
586 | }; |
587 | ||
588 | ccn@4000000 { | |
589 | compatible = "arm,ccn-504"; | |
590 | reg = <0x0 0x04000000 0x0 0x01000000>; | |
591 | interrupts = <0 12 4>; | |
592 | }; | |
747c84d0 BS |
593 | }; |
594 | }; |