projects / linux-2.6-block.git / blame
| Commit | Line | Data |
|---|---|---|
| 7a2aeb91 | 1 | // SPDX-License-Identifier: (GPL-2.0+ OR MIT) |
| 6d453cd2 | 2 | /* |
| f7d48ffc | 3 | * Device Tree Include file for NXP Layerscape-1043A family SoC. |
| 6d453cd2 | 4 | * |
| 8637f58b | 5 | * Copyright 2014-2015 Freescale Semiconductor, Inc. |
| f7d48ffc | 6 | * Copyright 2018, 2020 NXP |
| 6d453cd2 MH |
7 | * |
| 8 | * Mingkai Hu <Mingkai.hu@freescale.com> | |
| 6d453cd2 MH |
9 | */ |
| 10 | ||
| 7525022d | 11 | #include <dt-bindings/clock/fsl,qoriq-clockgen.h> |
| 18486552 | 12 | #include <dt-bindings/thermal/thermal.h> |
| 90945593 | 13 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 4b211ebb | 14 | #include <dt-bindings/gpio/gpio.h> |
| 18486552 | 15 | |
| 6d453cd2 MH |
16 | / { |
| 17 | compatible = "fsl,ls1043a"; | |
| 18 | interrupt-parent = <&gic>; | |
| 19 | #address-cells = <2>; | |
| 20 | #size-cells = <2>; | |
| 21 | ||
| bf02f2ff | 22 | aliases { |
| 00f1dac3 | 23 | crypto = &crypto; |
| bf02f2ff MB |
24 | fman0 = &fman0; |
| 25 | ethernet0 = &enet0; | |
| 26 | ethernet1 = &enet1; | |
| 27 | ethernet2 = &enet2; | |
| 28 | ethernet3 = &enet3; | |
| 29 | ethernet4 = &enet4; | |
| 30 | ethernet5 = &enet5; | |
| 31 | ethernet6 = &enet6; | |
| f4fe3a86 | 32 | rtc1 = &ftm_alarm0; |
| bf02f2ff MB |
33 | }; |
| 34 | ||
| 6d453cd2 | 35 | cpus { |
| e6d66c50 | 36 | #address-cells = <1>; |
| 6d453cd2 MH |
37 | #size-cells = <0>; |
| 38 | ||
| 39 | /* | |
| 40 | * We expect the enable-method for cpu's to be "psci", but this | |
| 41 | * is dependent on the SoC FW, which will fill this in. | |
| 42 | * | |
| 43 | * Currently supported enable-method is psci v0.2 | |
| 44 | */ | |
| 45 | cpu0: cpu@0 { | |
| 46 | device_type = "cpu"; | |
| 47 | compatible = "arm,cortex-a53"; | |
| e6d66c50 | 48 | reg = <0x0>; |
| 7525022d | 49 | clocks = <&clockgen QORIQ_CLK_CMUX 0>; |
| ec049f33 | 50 | next-level-cache = <&l2>; |
| 3fd366d8 | 51 | cpu-idle-states = <&CPU_PH20>; |
| 346f5976 | 52 | #cooling-cells = <2>; |
| 6d453cd2 MH |
53 | }; |
| 54 | ||
| 55 | cpu1: cpu@1 { | |
| 56 | device_type = "cpu"; | |
| 57 | compatible = "arm,cortex-a53"; | |
| e6d66c50 | 58 | reg = <0x1>; |
| 7525022d | 59 | clocks = <&clockgen QORIQ_CLK_CMUX 0>; |
| ec049f33 | 60 | next-level-cache = <&l2>; |
| 3fd366d8 | 61 | cpu-idle-states = <&CPU_PH20>; |
| 346f5976 | 62 | #cooling-cells = <2>; |
| 6d453cd2 MH |
63 | }; |
| 64 | ||
| 65 | cpu2: cpu@2 { | |
| 66 | device_type = "cpu"; | |
| 67 | compatible = "arm,cortex-a53"; | |
| e6d66c50 | 68 | reg = <0x2>; |
| 7525022d | 69 | clocks = <&clockgen QORIQ_CLK_CMUX 0>; |
| ec049f33 | 70 | next-level-cache = <&l2>; |
| 3fd366d8 | 71 | cpu-idle-states = <&CPU_PH20>; |
| 346f5976 | 72 | #cooling-cells = <2>; |
| 6d453cd2 MH |
73 | }; |
| 74 | ||
| 75 | cpu3: cpu@3 { | |
| 76 | device_type = "cpu"; | |
| 77 | compatible = "arm,cortex-a53"; | |
| e6d66c50 | 78 | reg = <0x3>; |
| 7525022d | 79 | clocks = <&clockgen QORIQ_CLK_CMUX 0>; |
| ec049f33 | 80 | next-level-cache = <&l2>; |
| 3fd366d8 | 81 | cpu-idle-states = <&CPU_PH20>; |
| 346f5976 | 82 | #cooling-cells = <2>; |
| ec049f33 LY |
83 | }; |
| 84 | ||
| 85 | l2: l2-cache { | |
| 86 | compatible = "cache"; | |
| 3b450831 | 87 | cache-level = <2>; |
| c290d09a | 88 | cache-unified; |
| 6d453cd2 MH |
89 | }; |
| 90 | }; | |
| 91 | ||
| 3fd366d8 YT |
92 | idle-states { |
| 93 | /* | |
| 94 | * PSCI node is not added default, U-boot will add missing | |
| 95 | * parts if it determines to use PSCI. | |
| 96 | */ | |
| e9880240 | 97 | entry-method = "psci"; |
| 3fd366d8 YT |
98 | |
| 99 | CPU_PH20: cpu-ph20 { | |
| 100 | compatible = "arm,idle-state"; | |
| 101 | idle-state-name = "PH20"; | |
| 69ea29b0 | 102 | arm,psci-suspend-param = <0x0>; |
| 3fd366d8 YT |
103 | entry-latency-us = <1000>; |
| 104 | exit-latency-us = <1000>; | |
| 105 | min-residency-us = <3000>; | |
| 106 | }; | |
| 107 | }; | |
| 108 | ||
| 6d453cd2 MH |
109 | memory@80000000 { |
| 110 | device_type = "memory"; | |
| 111 | reg = <0x0 0x80000000 0 0x80000000>; | |
| 112 | /* DRAM space 1, size: 2GiB DRAM */ | |
| 113 | }; | |
| 114 | ||
| 90945593 MB |
115 | reserved-memory { |
| 116 | #address-cells = <2>; | |
| 117 | #size-cells = <2>; | |
| 118 | ranges; | |
| 119 | ||
| 120 | bman_fbpr: bman-fbpr { | |
| 121 | compatible = "shared-dma-pool"; | |
| 122 | size = <0 0x1000000>; | |
| 123 | alignment = <0 0x1000000>; | |
| 124 | no-map; | |
| 125 | }; | |
| 126 | ||
| 127 | qman_fqd: qman-fqd { | |
| 128 | compatible = "shared-dma-pool"; | |
| 129 | size = <0 0x400000>; | |
| 130 | alignment = <0 0x400000>; | |
| 131 | no-map; | |
| 132 | }; | |
| 133 | ||
| 134 | qman_pfdr: qman-pfdr { | |
| 135 | compatible = "shared-dma-pool"; | |
| 136 | size = <0 0x2000000>; | |
| 137 | alignment = <0 0x2000000>; | |
| 138 | no-map; | |
| 139 | }; | |
| 140 | }; | |
| 141 | ||
| 6d453cd2 MH |
142 | sysclk: sysclk { |
| 143 | compatible = "fixed-clock"; | |
| 144 | #clock-cells = <0>; | |
| 145 | clock-frequency = <100000000>; | |
| 146 | clock-output-names = "sysclk"; | |
| 147 | }; | |
| 148 | ||
| 149 | reboot { | |
| 33597c62 | 150 | compatible = "syscon-reboot"; |
| 6d453cd2 MH |
151 | regmap = <&dcfg>; |
| 152 | offset = <0xb0>; | |
| 153 | mask = <0x02>; | |
| 154 | }; | |
| 155 | ||
| 0abe2a16 | 156 | thermal-zones { |
| c147caa6 | 157 | ddr-controller { |
| 0abe2a16 FE |
158 | polling-delay-passive = <1000>; |
| 159 | polling-delay = <5000>; | |
| c147caa6 | 160 | thermal-sensors = <&tmu 0>; |
| 0abe2a16 | 161 | |
| c147caa6 YT |
162 | trips { |
| 163 | ddr-ctrler-alert { | |
| 164 | temperature = <85000>; | |
| 165 | hysteresis = <2000>; | |
| 166 | type = "passive"; | |
| 167 | }; | |
| 168 | ||
| 169 | ddr-ctrler-crit { | |
| 170 | temperature = <95000>; | |
| 171 | hysteresis = <2000>; | |
| 172 | type = "critical"; | |
| 173 | }; | |
| 174 | }; | |
| 175 | }; | |
| 176 | ||
| 177 | serdes { | |
| 178 | polling-delay-passive = <1000>; | |
| 179 | polling-delay = <5000>; | |
| 180 | thermal-sensors = <&tmu 1>; | |
| 181 | ||
| 182 | trips { | |
| 183 | serdes-alert { | |
| 184 | temperature = <85000>; | |
| 185 | hysteresis = <2000>; | |
| 186 | type = "passive"; | |
| 187 | }; | |
| 188 | ||
| 189 | serdes-crit { | |
| 190 | temperature = <95000>; | |
| 191 | hysteresis = <2000>; | |
| 192 | type = "critical"; | |
| 193 | }; | |
| 194 | }; | |
| 195 | }; | |
| 196 | ||
| 197 | fman { | |
| 198 | polling-delay-passive = <1000>; | |
| 199 | polling-delay = <5000>; | |
| 200 | thermal-sensors = <&tmu 2>; | |
| 201 | ||
| 202 | trips { | |
| 203 | fman-alert { | |
| 204 | temperature = <85000>; | |
| 205 | hysteresis = <2000>; | |
| 206 | type = "passive"; | |
| 207 | }; | |
| 208 | ||
| 209 | fman-crit { | |
| 210 | temperature = <95000>; | |
| 211 | hysteresis = <2000>; | |
| 212 | type = "critical"; | |
| 213 | }; | |
| 214 | }; | |
| 215 | }; | |
| 216 | ||
| 217 | core-cluster { | |
| 218 | polling-delay-passive = <1000>; | |
| 219 | polling-delay = <5000>; | |
| 0abe2a16 FE |
220 | thermal-sensors = <&tmu 3>; |
| 221 | ||
| 222 | trips { | |
| c147caa6 | 223 | core_cluster_alert: core-cluster-alert { |
| 0abe2a16 FE |
224 | temperature = <85000>; |
| 225 | hysteresis = <2000>; | |
| 226 | type = "passive"; | |
| 227 | }; | |
| c147caa6 YT |
228 | |
| 229 | core_cluster_crit: core-cluster-crit { | |
| 0abe2a16 FE |
230 | temperature = <95000>; |
| 231 | hysteresis = <2000>; | |
| 232 | type = "critical"; | |
| 233 | }; | |
| 234 | }; | |
| 235 | ||
| 236 | cooling-maps { | |
| 237 | map0 { | |
| c147caa6 | 238 | trip = <&core_cluster_alert>; |
| 0abe2a16 | 239 | cooling-device = |
| c9a1f243 VK |
240 | <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| 241 | <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 242 | <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 243 | <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
| 0abe2a16 FE |
244 | }; |
| 245 | }; | |
| 246 | }; | |
| c147caa6 YT |
247 | |
| 248 | sec { | |
| 249 | polling-delay-passive = <1000>; | |
| 250 | polling-delay = <5000>; | |
| 251 | thermal-sensors = <&tmu 4>; | |
| 252 | ||
| 253 | trips { | |
| 254 | sec-alert { | |
| 255 | temperature = <85000>; | |
| 256 | hysteresis = <2000>; | |
| 257 | type = "passive"; | |
| 258 | }; | |
| 259 | ||
| 260 | sec-crit { | |
| 261 | temperature = <95000>; | |
| 262 | hysteresis = <2000>; | |
| 263 | type = "critical"; | |
| 264 | }; | |
| 265 | }; | |
| 266 | }; | |
| 0abe2a16 FE |
267 | }; |
| 268 | ||
| 6d453cd2 MH |
269 | timer { |
| 270 | compatible = "arm,armv8-timer"; | |
| f2a89d3b MZ |
271 | interrupts = <1 13 0xf08>, /* Physical Secure PPI */ |
| 272 | <1 14 0xf08>, /* Physical Non-Secure PPI */ | |
| 273 | <1 11 0xf08>, /* Virtual PPI */ | |
| 274 | <1 10 0xf08>; /* Hypervisor PPI */ | |
| 6a34e0e6 | 275 | fsl,erratum-a008585; |
| 6d453cd2 MH |
276 | }; |
| 277 | ||
| 278 | pmu { | |
| 8b40a469 | 279 | compatible = "arm,cortex-a53-pmu"; |
| 6d453cd2 MH |
280 | interrupts = <0 106 0x4>, |
| 281 | <0 107 0x4>, | |
| 282 | <0 95 0x4>, | |
| 283 | <0 97 0x4>; | |
| 284 | interrupt-affinity = <&cpu0>, | |
| 285 | <&cpu1>, | |
| 286 | <&cpu2>, | |
| 287 | <&cpu3>; | |
| 288 | }; | |
| 289 | ||
| 290 | gic: interrupt-controller@1400000 { | |
| 291 | compatible = "arm,gic-400"; | |
| 292 | #interrupt-cells = <3>; | |
| 293 | interrupt-controller; | |
| 294 | reg = <0x0 0x1401000 0 0x1000>, /* GICD */ | |
| 295 | <0x0 0x1402000 0 0x2000>, /* GICC */ | |
| 296 | <0x0 0x1404000 0 0x2000>, /* GICH */ | |
| 297 | <0x0 0x1406000 0 0x2000>; /* GICV */ | |
| 298 | interrupts = <1 9 0xf08>; | |
| 299 | }; | |
| 300 | ||
| bf02f2ff | 301 | soc: soc { |
| 6d453cd2 MH |
302 | compatible = "simple-bus"; |
| 303 | #address-cells = <2>; | |
| 304 | #size-cells = <2>; | |
| 305 | ranges; | |
| 21d5096f | 306 | dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>; |
| f0560158 | 307 | dma-coherent; |
| 6d453cd2 MH |
308 | |
| 309 | clockgen: clocking@1ee1000 { | |
| 310 | compatible = "fsl,ls1043a-clockgen"; | |
| 311 | reg = <0x0 0x1ee1000 0x0 0x1000>; | |
| 312 | #clock-cells = <2>; | |
| 313 | clocks = <&sysclk>; | |
| 314 | }; | |
| 315 | ||
| 316 | scfg: scfg@1570000 { | |
| 317 | compatible = "fsl,ls1043a-scfg", "syscon"; | |
| 318 | reg = <0x0 0x1570000 0x0 0x10000>; | |
| 319 | big-endian; | |
| 3f8c61a5 BL |
320 | #address-cells = <1>; |
| 321 | #size-cells = <1>; | |
| 322 | ranges = <0x0 0x0 0x1570000 0x10000>; | |
| 323 | ||
| 324 | extirq: interrupt-controller@1ac { | |
| 325 | compatible = "fsl,ls1043a-extirq"; | |
| 326 | #interrupt-cells = <2>; | |
| 327 | #address-cells = <0>; | |
| 328 | interrupt-controller; | |
| 329 | reg = <0x1ac 4>; | |
| 330 | interrupt-map = | |
| 331 | <0 0 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, | |
| 332 | <1 0 &gic GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, | |
| 333 | <2 0 &gic GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, | |
| 334 | <3 0 &gic GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, | |
| 335 | <4 0 &gic GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, | |
| 336 | <5 0 &gic GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, | |
| 337 | <6 0 &gic GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, | |
| 338 | <7 0 &gic GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, | |
| 339 | <8 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, | |
| 340 | <9 0 &gic GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, | |
| 341 | <10 0 &gic GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, | |
| 342 | <11 0 &gic GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; | |
| 339c8bea | 343 | interrupt-map-mask = <0xf 0x0>; |
| 3f8c61a5 | 344 | }; |
| 6d453cd2 MH |
345 | }; |
| 346 | ||
| 63dac35b HG |
347 | crypto: crypto@1700000 { |
| 348 | compatible = "fsl,sec-v5.4", "fsl,sec-v5.0", | |
| 349 | "fsl,sec-v4.0"; | |
| 350 | fsl,sec-era = <3>; | |
| 351 | #address-cells = <1>; | |
| 352 | #size-cells = <1>; | |
| 353 | ranges = <0x0 0x00 0x1700000 0x100000>; | |
| 354 | reg = <0x00 0x1700000 0x0 0x100000>; | |
| 355 | interrupts = <0 75 0x4>; | |
| 4fb3a074 | 356 | dma-coherent; |
| 63dac35b HG |
357 | |
| 358 | sec_jr0: jr@10000 { | |
| 359 | compatible = "fsl,sec-v5.4-job-ring", | |
| 360 | "fsl,sec-v5.0-job-ring", | |
| 361 | "fsl,sec-v4.0-job-ring"; | |
| 33597c62 | 362 | reg = <0x10000 0x10000>; |
| 63dac35b HG |
363 | interrupts = <0 71 0x4>; |
| 364 | }; | |
| 365 | ||
| 366 | sec_jr1: jr@20000 { | |
| 367 | compatible = "fsl,sec-v5.4-job-ring", | |
| 368 | "fsl,sec-v5.0-job-ring", | |
| 369 | "fsl,sec-v4.0-job-ring"; | |
| 33597c62 | 370 | reg = <0x20000 0x10000>; |
| 63dac35b HG |
371 | interrupts = <0 72 0x4>; |
| 372 | }; | |
| 373 | ||
| 374 | sec_jr2: jr@30000 { | |
| 375 | compatible = "fsl,sec-v5.4-job-ring", | |
| 376 | "fsl,sec-v5.0-job-ring", | |
| 377 | "fsl,sec-v4.0-job-ring"; | |
| 33597c62 | 378 | reg = <0x30000 0x10000>; |
| 63dac35b HG |
379 | interrupts = <0 73 0x4>; |
| 380 | }; | |
| 381 | ||
| 382 | sec_jr3: jr@40000 { | |
| 383 | compatible = "fsl,sec-v5.4-job-ring", | |
| 384 | "fsl,sec-v5.0-job-ring", | |
| 385 | "fsl,sec-v4.0-job-ring"; | |
| 33597c62 | 386 | reg = <0x40000 0x10000>; |
| 63dac35b HG |
387 | interrupts = <0 74 0x4>; |
| 388 | }; | |
| 389 | }; | |
| 390 | ||
| 043dce4e SA |
391 | sfp: efuse@1e80000 { |
| 392 | compatible = "fsl,ls1021a-sfp"; | |
| 393 | reg = <0x0 0x1e80000 0x0 0x10000>; | |
| 394 | clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL | |
| 395 | QORIQ_CLK_PLL_DIV(4)>; | |
| 396 | clock-names = "sfp"; | |
| 397 | }; | |
| 398 | ||
| 6d453cd2 MH |
399 | dcfg: dcfg@1ee0000 { |
| 400 | compatible = "fsl,ls1043a-dcfg", "syscon"; | |
| 9b6408f0 | 401 | reg = <0x0 0x1ee0000 0x0 0x1000>; |
| 6d453cd2 MH |
402 | big-endian; |
| 403 | }; | |
| 404 | ||
| e55264f3 | 405 | ifc: memory-controller@1530000 { |
| fefbc002 | 406 | compatible = "fsl,ifc"; |
| 6d453cd2 MH |
407 | reg = <0x0 0x1530000 0x0 0x10000>; |
| 408 | interrupts = <0 43 0x4>; | |
| 409 | }; | |
| 410 | ||
| b739c177 | 411 | qspi: spi@1550000 { |
| e26e054b YY |
412 | compatible = "fsl,ls1043a-qspi", "fsl,ls1021a-qspi"; |
| 413 | #address-cells = <1>; | |
| 414 | #size-cells = <0>; | |
| 415 | reg = <0x0 0x1550000 0x0 0x10000>, | |
| 416 | <0x0 0x40000000 0x0 0x4000000>; | |
| 417 | reg-names = "QuadSPI", "QuadSPI-memory"; | |
| 418 | interrupts = <0 99 0x4>; | |
| 419 | clock-names = "qspi_en", "qspi"; | |
| 7525022d MW |
420 | clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL |
| 421 | QORIQ_CLK_PLL_DIV(1)>, | |
| 422 | <&clockgen QORIQ_CLK_PLATFORM_PLL | |
| 423 | QORIQ_CLK_PLL_DIV(1)>; | |
| e26e054b YY |
424 | status = "disabled"; |
| 425 | }; | |
| 426 | ||
| 6d453cd2 MH |
427 | esdhc: esdhc@1560000 { |
| 428 | compatible = "fsl,ls1043a-esdhc", "fsl,esdhc"; | |
| 429 | reg = <0x0 0x1560000 0x0 0x10000>; | |
| 430 | interrupts = <0 62 0x4>; | |
| 431 | clock-frequency = <0>; | |
| 432 | voltage-ranges = <1800 1800 3300 3300>; | |
| 433 | sdhci,auto-cmd12; | |
| 434 | big-endian; | |
| 435 | bus-width = <4>; | |
| 436 | }; | |
| 437 | ||
| 30062fb0 YS |
438 | ddr: memory-controller@1080000 { |
| 439 | compatible = "fsl,qoriq-memory-controller"; | |
| 440 | reg = <0x0 0x1080000 0x0 0x1000>; | |
| 441 | interrupts = <0 144 0x4>; | |
| 442 | big-endian; | |
| 443 | }; | |
| 444 | ||
| 18486552 HJ |
445 | tmu: tmu@1f00000 { |
| 446 | compatible = "fsl,qoriq-tmu"; | |
| 447 | reg = <0x0 0x1f00000 0x0 0x10000>; | |
| 448 | interrupts = <0 33 0x4>; | |
| 64d81113 | 449 | fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x70062>; |
| f43c3a62 DH |
450 | fsl,tmu-calibration = |
| 451 | <0x00000000 0x00000023>, | |
| 452 | <0x00000001 0x0000002a>, | |
| 453 | <0x00000002 0x00000031>, | |
| 454 | <0x00000003 0x00000037>, | |
| 455 | <0x00000004 0x0000003e>, | |
| 456 | <0x00000005 0x00000044>, | |
| 457 | <0x00000006 0x0000004b>, | |
| 458 | <0x00000007 0x00000051>, | |
| 459 | <0x00000008 0x00000058>, | |
| 460 | <0x00000009 0x0000005e>, | |
| 461 | <0x0000000a 0x00000065>, | |
| 462 | <0x0000000b 0x0000006b>, | |
| 463 | ||
| 464 | <0x00010000 0x00000023>, | |
| 465 | <0x00010001 0x0000002b>, | |
| 466 | <0x00010002 0x00000033>, | |
| 467 | <0x00010003 0x0000003b>, | |
| 468 | <0x00010004 0x00000043>, | |
| 469 | <0x00010005 0x0000004b>, | |
| 470 | <0x00010006 0x00000054>, | |
| 471 | <0x00010007 0x0000005c>, | |
| 472 | <0x00010008 0x00000064>, | |
| 473 | <0x00010009 0x0000006c>, | |
| 474 | ||
| 475 | <0x00020000 0x00000021>, | |
| 476 | <0x00020001 0x0000002c>, | |
| 477 | <0x00020002 0x00000036>, | |
| 478 | <0x00020003 0x00000040>, | |
| 479 | <0x00020004 0x0000004b>, | |
| 480 | <0x00020005 0x00000055>, | |
| 481 | <0x00020006 0x0000005f>, | |
| 482 | ||
| 483 | <0x00030000 0x00000013>, | |
| 484 | <0x00030001 0x0000001d>, | |
| 485 | <0x00030002 0x00000028>, | |
| 486 | <0x00030003 0x00000032>, | |
| 487 | <0x00030004 0x0000003d>, | |
| 488 | <0x00030005 0x00000047>, | |
| 489 | <0x00030006 0x00000052>, | |
| 490 | <0x00030007 0x0000005c>; | |
| 18486552 HJ |
491 | #thermal-sensor-cells = <1>; |
| 492 | }; | |
| 493 | ||
| 90945593 MB |
494 | qman: qman@1880000 { |
| 495 | compatible = "fsl,qman"; | |
| 496 | reg = <0x0 0x1880000 0x0 0x10000>; | |
| e54b911f | 497 | interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; |
| 90945593 MB |
498 | memory-region = <&qman_fqd &qman_pfdr>; |
| 499 | }; | |
| 500 | ||
| 501 | bman: bman@1890000 { | |
| 502 | compatible = "fsl,bman"; | |
| 503 | reg = <0x0 0x1890000 0x0 0x10000>; | |
| e54b911f | 504 | interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; |
| 90945593 MB |
505 | memory-region = <&bman_fbpr>; |
| 506 | }; | |
| 507 | ||
| 508 | bportals: bman-portals@508000000 { | |
| 509 | ranges = <0x0 0x5 0x08000000 0x8000000>; | |
| 510 | }; | |
| 511 | ||
| 512 | qportals: qman-portals@500000000 { | |
| 513 | ranges = <0x0 0x5 0x00000000 0x8000000>; | |
| 514 | }; | |
| 515 | ||
| b739c177 | 516 | dspi0: spi@2100000 { |
| 6d453cd2 MH |
517 | compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi"; |
| 518 | #address-cells = <1>; | |
| 519 | #size-cells = <0>; | |
| 520 | reg = <0x0 0x2100000 0x0 0x10000>; | |
| 521 | interrupts = <0 64 0x4>; | |
| 522 | clock-names = "dspi"; | |
| 7525022d MW |
523 | clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL |
| 524 | QORIQ_CLK_PLL_DIV(1)>; | |
| 6d453cd2 MH |
525 | spi-num-chipselects = <5>; |
| 526 | big-endian; | |
| 527 | status = "disabled"; | |
| 528 | }; | |
| 529 | ||
| 6d453cd2 | 530 | i2c0: i2c@2180000 { |
| 4b211ebb | 531 | compatible = "fsl,ls1043a-i2c", "fsl,vf610-i2c"; |
| 6d453cd2 MH |
532 | #address-cells = <1>; |
| 533 | #size-cells = <0>; | |
| 534 | reg = <0x0 0x2180000 0x0 0x10000>; | |
| 535 | interrupts = <0 56 0x4>; | |
| 536 | clock-names = "i2c"; | |
| 7525022d MW |
537 | clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL |
| 538 | QORIQ_CLK_PLL_DIV(1)>; | |
| aa4df840 KS |
539 | dmas = <&edma0 1 38>, |
| 540 | <&edma0 1 39>; | |
| 541 | dma-names = "rx", "tx"; | |
| 6d453cd2 MH |
542 | status = "disabled"; |
| 543 | }; | |
| 544 | ||
| 545 | i2c1: i2c@2190000 { | |
| 4b211ebb | 546 | compatible = "fsl,ls1043a-i2c", "fsl,vf610-i2c"; |
| 6d453cd2 MH |
547 | #address-cells = <1>; |
| 548 | #size-cells = <0>; | |
| 549 | reg = <0x0 0x2190000 0x0 0x10000>; | |
| 550 | interrupts = <0 57 0x4>; | |
| 551 | clock-names = "i2c"; | |
| 7525022d MW |
552 | clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL |
| 553 | QORIQ_CLK_PLL_DIV(1)>; | |
| 4b211ebb | 554 | scl-gpios = <&gpio4 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; |
| 6d453cd2 MH |
555 | status = "disabled"; |
| 556 | }; | |
| 557 | ||
| 558 | i2c2: i2c@21a0000 { | |
| 4b211ebb | 559 | compatible = "fsl,ls1043a-i2c", "fsl,vf610-i2c"; |
| 6d453cd2 MH |
560 | #address-cells = <1>; |
| 561 | #size-cells = <0>; | |
| 562 | reg = <0x0 0x21a0000 0x0 0x10000>; | |
| 563 | interrupts = <0 58 0x4>; | |
| 564 | clock-names = "i2c"; | |
| 7525022d MW |
565 | clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL |
| 566 | QORIQ_CLK_PLL_DIV(1)>; | |
| 4b211ebb | 567 | scl-gpios = <&gpio4 10 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; |
| 6d453cd2 MH |
568 | status = "disabled"; |
| 569 | }; | |
| 570 | ||
| 571 | i2c3: i2c@21b0000 { | |
| 4b211ebb | 572 | compatible = "fsl,ls1043a-i2c", "fsl,vf610-i2c"; |
| 6d453cd2 MH |
573 | #address-cells = <1>; |
| 574 | #size-cells = <0>; | |
| 575 | reg = <0x0 0x21b0000 0x0 0x10000>; | |
| 576 | interrupts = <0 59 0x4>; | |
| 577 | clock-names = "i2c"; | |
| 7525022d MW |
578 | clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL |
| 579 | QORIQ_CLK_PLL_DIV(1)>; | |
| 4b211ebb | 580 | scl-gpios = <&gpio4 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; |
| 6d453cd2 MH |
581 | status = "disabled"; |
| 582 | }; | |
| 583 | ||
| 584 | duart0: serial@21c0500 { | |
| 585 | compatible = "fsl,ns16550", "ns16550a"; | |
| 586 | reg = <0x00 0x21c0500 0x0 0x100>; | |
| 587 | interrupts = <0 54 0x4>; | |
| 7525022d MW |
588 | clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL |
| 589 | QORIQ_CLK_PLL_DIV(1)>; | |
| 6d453cd2 MH |
590 | }; |
| 591 | ||
| 592 | duart1: serial@21c0600 { | |
| 593 | compatible = "fsl,ns16550", "ns16550a"; | |
| 594 | reg = <0x00 0x21c0600 0x0 0x100>; | |
| 595 | interrupts = <0 54 0x4>; | |
| 7525022d MW |
596 | clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL |
| 597 | QORIQ_CLK_PLL_DIV(1)>; | |
| 6d453cd2 MH |
598 | }; |
| 599 | ||
| 600 | duart2: serial@21d0500 { | |
| 601 | compatible = "fsl,ns16550", "ns16550a"; | |
| 602 | reg = <0x0 0x21d0500 0x0 0x100>; | |
| 603 | interrupts = <0 55 0x4>; | |
| 7525022d MW |
604 | clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL |
| 605 | QORIQ_CLK_PLL_DIV(1)>; | |
| 6d453cd2 MH |
606 | }; |
| 607 | ||
| 608 | duart3: serial@21d0600 { | |
| 609 | compatible = "fsl,ns16550", "ns16550a"; | |
| 610 | reg = <0x0 0x21d0600 0x0 0x100>; | |
| 611 | interrupts = <0 55 0x4>; | |
| 7525022d MW |
612 | clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL |
| 613 | QORIQ_CLK_PLL_DIV(1)>; | |
| 6d453cd2 MH |
614 | }; |
| 615 | ||
| 616 | gpio1: gpio@2300000 { | |
| c21de87d | 617 | compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio"; |
| 6d453cd2 MH |
618 | reg = <0x0 0x2300000 0x0 0x10000>; |
| 619 | interrupts = <0 66 0x4>; | |
| 620 | gpio-controller; | |
| 621 | #gpio-cells = <2>; | |
| 622 | interrupt-controller; | |
| 623 | #interrupt-cells = <2>; | |
| 624 | }; | |
| 625 | ||
| 626 | gpio2: gpio@2310000 { | |
| c21de87d | 627 | compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio"; |
| 6d453cd2 MH |
628 | reg = <0x0 0x2310000 0x0 0x10000>; |
| 629 | interrupts = <0 67 0x4>; | |
| 630 | gpio-controller; | |
| 631 | #gpio-cells = <2>; | |
| 632 | interrupt-controller; | |
| 633 | #interrupt-cells = <2>; | |
| 634 | }; | |
| 635 | ||
| 636 | gpio3: gpio@2320000 { | |
| c21de87d | 637 | compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio"; |
| 6d453cd2 MH |
638 | reg = <0x0 0x2320000 0x0 0x10000>; |
| 639 | interrupts = <0 68 0x4>; | |
| 640 | gpio-controller; | |
| 641 | #gpio-cells = <2>; | |
| 642 | interrupt-controller; | |
| 643 | #interrupt-cells = <2>; | |
| 644 | }; | |
| 645 | ||
| 646 | gpio4: gpio@2330000 { | |
| c21de87d | 647 | compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio"; |
| 6d453cd2 MH |
648 | reg = <0x0 0x2330000 0x0 0x10000>; |
| 649 | interrupts = <0 134 0x4>; | |
| 650 | gpio-controller; | |
| 651 | #gpio-cells = <2>; | |
| 652 | interrupt-controller; | |
| 653 | #interrupt-cells = <2>; | |
| 654 | }; | |
| 655 | ||
| 76afd7db ZQ |
656 | uqe: uqe@2400000 { |
| 657 | #address-cells = <1>; | |
| 658 | #size-cells = <1>; | |
| 659 | compatible = "fsl,qe", "simple-bus"; | |
| 660 | ranges = <0x0 0x0 0x2400000 0x40000>; | |
| 661 | reg = <0x0 0x2400000 0x0 0x480>; | |
| 662 | brg-frequency = <100000000>; | |
| 663 | bus-frequency = <200000000>; | |
| 664 | fsl,qe-num-riscs = <1>; | |
| 665 | fsl,qe-num-snums = <28>; | |
| 666 | ||
| 667 | qeic: qeic@80 { | |
| 668 | compatible = "fsl,qe-ic"; | |
| 669 | reg = <0x80 0x80>; | |
| 670 | #address-cells = <0>; | |
| 671 | interrupt-controller; | |
| 672 | #interrupt-cells = <1>; | |
| 673 | interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, | |
| 674 | <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; | |
| 675 | }; | |
| 676 | ||
| 677 | si1: si@700 { | |
| 678 | #address-cells = <1>; | |
| 679 | #size-cells = <0>; | |
| 680 | compatible = "fsl,ls1043-qe-si", | |
| 681 | "fsl,t1040-qe-si"; | |
| 682 | reg = <0x700 0x80>; | |
| 683 | }; | |
| 684 | ||
| 685 | siram1: siram@1000 { | |
| 686 | #address-cells = <1>; | |
| 687 | #size-cells = <1>; | |
| 688 | compatible = "fsl,ls1043-qe-siram", | |
| 689 | "fsl,t1040-qe-siram"; | |
| 690 | reg = <0x1000 0x800>; | |
| 691 | }; | |
| 692 | ||
| 693 | ucc@2000 { | |
| 694 | cell-index = <1>; | |
| 695 | reg = <0x2000 0x200>; | |
| 696 | interrupts = <32>; | |
| 697 | interrupt-parent = <&qeic>; | |
| 698 | }; | |
| 699 | ||
| 700 | ucc@2200 { | |
| 701 | cell-index = <3>; | |
| 702 | reg = <0x2200 0x200>; | |
| 703 | interrupts = <34>; | |
| 704 | interrupt-parent = <&qeic>; | |
| 705 | }; | |
| 706 | ||
| 707 | muram@10000 { | |
| 708 | #address-cells = <1>; | |
| 709 | #size-cells = <1>; | |
| 710 | compatible = "fsl,qe-muram", "fsl,cpm-muram"; | |
| 711 | ranges = <0x0 0x10000 0x6000>; | |
| 712 | ||
| 713 | data-only@0 { | |
| 714 | compatible = "fsl,qe-muram-data", | |
| 715 | "fsl,cpm-muram-data"; | |
| 716 | reg = <0x0 0x6000>; | |
| 717 | }; | |
| 718 | }; | |
| 719 | }; | |
| 720 | ||
| 6d453cd2 MH |
721 | lpuart0: serial@2950000 { |
| 722 | compatible = "fsl,ls1021a-lpuart"; | |
| 723 | reg = <0x0 0x2950000 0x0 0x1000>; | |
| 724 | interrupts = <0 48 0x4>; | |
| 7525022d | 725 | clocks = <&clockgen QORIQ_CLK_SYSCLK 0>; |
| 6d453cd2 MH |
726 | clock-names = "ipg"; |
| 727 | status = "disabled"; | |
| 728 | }; | |
| 729 | ||
| 730 | lpuart1: serial@2960000 { | |
| 731 | compatible = "fsl,ls1021a-lpuart"; | |
| 732 | reg = <0x0 0x2960000 0x0 0x1000>; | |
| 733 | interrupts = <0 49 0x4>; | |
| 7525022d MW |
734 | clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL |
| 735 | QORIQ_CLK_PLL_DIV(1)>; | |
| 6d453cd2 MH |
736 | clock-names = "ipg"; |
| 737 | status = "disabled"; | |
| 738 | }; | |
| 739 | ||
| 740 | lpuart2: serial@2970000 { | |
| 741 | compatible = "fsl,ls1021a-lpuart"; | |
| 742 | reg = <0x0 0x2970000 0x0 0x1000>; | |
| 743 | interrupts = <0 50 0x4>; | |
| 7525022d MW |
744 | clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL |
| 745 | QORIQ_CLK_PLL_DIV(1)>; | |
| 6d453cd2 MH |
746 | clock-names = "ipg"; |
| 747 | status = "disabled"; | |
| 748 | }; | |
| 749 | ||
| 750 | lpuart3: serial@2980000 { | |
| 751 | compatible = "fsl,ls1021a-lpuart"; | |
| 752 | reg = <0x0 0x2980000 0x0 0x1000>; | |
| 753 | interrupts = <0 51 0x4>; | |
| 7525022d MW |
754 | clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL |
| 755 | QORIQ_CLK_PLL_DIV(1)>; | |
| 6d453cd2 MH |
756 | clock-names = "ipg"; |
| 757 | status = "disabled"; | |
| 758 | }; | |
| 759 | ||
| 760 | lpuart4: serial@2990000 { | |
| 761 | compatible = "fsl,ls1021a-lpuart"; | |
| 762 | reg = <0x0 0x2990000 0x0 0x1000>; | |
| 763 | interrupts = <0 52 0x4>; | |
| 7525022d MW |
764 | clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL |
| 765 | QORIQ_CLK_PLL_DIV(1)>; | |
| 6d453cd2 MH |
766 | clock-names = "ipg"; |
| 767 | status = "disabled"; | |
| 768 | }; | |
| 769 | ||
| 770 | lpuart5: serial@29a0000 { | |
| 771 | compatible = "fsl,ls1021a-lpuart"; | |
| 772 | reg = <0x0 0x29a0000 0x0 0x1000>; | |
| 773 | interrupts = <0 53 0x4>; | |
| 7525022d MW |
774 | clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL |
| 775 | QORIQ_CLK_PLL_DIV(1)>; | |
| 6d453cd2 MH |
776 | clock-names = "ipg"; |
| 777 | status = "disabled"; | |
| 778 | }; | |
| 779 | ||
| 71011f55 | 780 | wdog0: watchdog@2ad0000 { |
| 6d453cd2 MH |
781 | compatible = "fsl,ls1043a-wdt", "fsl,imx21-wdt"; |
| 782 | reg = <0x0 0x2ad0000 0x0 0x10000>; | |
| 783 | interrupts = <0 83 0x4>; | |
| 7525022d MW |
784 | clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL |
| 785 | QORIQ_CLK_PLL_DIV(1)>; | |
| 6d453cd2 MH |
786 | clock-names = "wdog"; |
| 787 | big-endian; | |
| 788 | }; | |
| 789 | ||
| 4a154e5a | 790 | edma0: dma-controller@2c00000 { |
| 6d453cd2 MH |
791 | #dma-cells = <2>; |
| 792 | compatible = "fsl,vf610-edma"; | |
| 793 | reg = <0x0 0x2c00000 0x0 0x10000>, | |
| 794 | <0x0 0x2c10000 0x0 0x10000>, | |
| 795 | <0x0 0x2c20000 0x0 0x10000>; | |
| 796 | interrupts = <0 103 0x4>, | |
| 797 | <0 103 0x4>; | |
| 798 | interrupt-names = "edma-tx", "edma-err"; | |
| 799 | dma-channels = <32>; | |
| 800 | big-endian; | |
| 801 | clock-names = "dmamux0", "dmamux1"; | |
| 7525022d MW |
802 | clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL |
| 803 | QORIQ_CLK_PLL_DIV(1)>, | |
| 804 | <&clockgen QORIQ_CLK_PLATFORM_PLL | |
| 805 | QORIQ_CLK_PLL_DIV(1)>; | |
| 6d453cd2 MH |
806 | }; |
| 807 | ||
| 2a2ab4d5 LT |
808 | aux_bus: aux_bus { |
| 809 | #address-cells = <2>; | |
| 810 | #size-cells = <2>; | |
| 811 | compatible = "simple-bus"; | |
| 812 | ranges; | |
| 813 | dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x00000000>; | |
| 814 | ||
| 815 | usb0: usb@2f00000 { | |
| 816 | compatible = "snps,dwc3"; | |
| 817 | reg = <0x0 0x2f00000 0x0 0x10000>; | |
| 818 | interrupts = <0 60 IRQ_TYPE_LEVEL_HIGH>; | |
| 819 | dr_mode = "host"; | |
| 820 | snps,quirk-frame-length-adjustment = <0x20>; | |
| 821 | snps,dis_rxdet_inp3_quirk; | |
| 822 | usb3-lpm-capable; | |
| 823 | snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; | |
| 824 | status = "disabled"; | |
| 825 | }; | |
| 6d453cd2 | 826 | |
| 2a2ab4d5 LT |
827 | usb1: usb@3000000 { |
| 828 | compatible = "snps,dwc3"; | |
| 829 | reg = <0x0 0x3000000 0x0 0x10000>; | |
| 830 | interrupts = <0 61 IRQ_TYPE_LEVEL_HIGH>; | |
| 831 | dr_mode = "host"; | |
| 832 | snps,quirk-frame-length-adjustment = <0x20>; | |
| 833 | snps,dis_rxdet_inp3_quirk; | |
| 834 | usb3-lpm-capable; | |
| 835 | snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; | |
| 836 | status = "disabled"; | |
| 837 | }; | |
| 6d453cd2 | 838 | |
| 2a2ab4d5 LT |
839 | usb2: usb@3100000 { |
| 840 | compatible = "snps,dwc3"; | |
| 841 | reg = <0x0 0x3100000 0x0 0x10000>; | |
| 842 | interrupts = <0 63 IRQ_TYPE_LEVEL_HIGH>; | |
| 843 | dr_mode = "host"; | |
| 844 | snps,quirk-frame-length-adjustment = <0x20>; | |
| 845 | snps,dis_rxdet_inp3_quirk; | |
| 846 | usb3-lpm-capable; | |
| 847 | snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; | |
| 848 | status = "disabled"; | |
| 849 | }; | |
| 6d453cd2 | 850 | |
| 2a2ab4d5 LT |
851 | sata: sata@3200000 { |
| 852 | compatible = "fsl,ls1043a-ahci"; | |
| 853 | reg = <0x0 0x3200000 0x0 0x10000>, | |
| 854 | <0x0 0x20140520 0x0 0x4>; | |
| 855 | reg-names = "ahci", "sata-ecc"; | |
| 856 | interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>; | |
| 857 | clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL | |
| 858 | QORIQ_CLK_PLL_DIV(1)>; | |
| 859 | dma-coherent; | |
| 860 | }; | |
| 6d453cd2 MH |
861 | }; |
| 862 | ||
| 863 | msi1: msi-controller1@1571000 { | |
| f93aff62 | 864 | compatible = "fsl,ls1043a-msi"; |
| 6d453cd2 MH |
865 | reg = <0x0 0x1571000 0x0 0x8>; |
| 866 | msi-controller; | |
| 867 | interrupts = <0 116 0x4>; | |
| 868 | }; | |
| 869 | ||
| 870 | msi2: msi-controller2@1572000 { | |
| f93aff62 | 871 | compatible = "fsl,ls1043a-msi"; |
| 6d453cd2 MH |
872 | reg = <0x0 0x1572000 0x0 0x8>; |
| 873 | msi-controller; | |
| 874 | interrupts = <0 126 0x4>; | |
| 875 | }; | |
| 876 | ||
| 877 | msi3: msi-controller3@1573000 { | |
| f93aff62 | 878 | compatible = "fsl,ls1043a-msi"; |
| 6d453cd2 MH |
879 | reg = <0x0 0x1573000 0x0 0x8>; |
| 880 | msi-controller; | |
| 881 | interrupts = <0 160 0x4>; | |
| 882 | }; | |
| 883 | ||
| f7d48ffc | 884 | pcie1: pcie@3400000 { |
| 1fa35bc0 | 885 | compatible = "fsl,ls1043a-pcie"; |
| ce87d936 ZL |
886 | reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */ |
| 887 | <0x40 0x00000000 0x0 0x00002000>; /* configuration space */ | |
| 6d453cd2 | 888 | reg-names = "regs", "config"; |
| ee00c1a6 LY |
889 | interrupts = <0 117 IRQ_TYPE_LEVEL_HIGH>, |
| 890 | <0 118 IRQ_TYPE_LEVEL_HIGH>; | |
| 891 | interrupt-names = "pme", "aer"; | |
| 6d453cd2 MH |
892 | #address-cells = <3>; |
| 893 | #size-cells = <2>; | |
| 894 | device_type = "pci"; | |
| 881e90d2 | 895 | num-viewport = <6>; |
| 6d453cd2 MH |
896 | bus-range = <0x0 0xff>; |
| 897 | ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */ | |
| 898 | 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ | |
| 0b09331a | 899 | msi-parent = <&msi1>, <&msi2>, <&msi3>; |
| 6d453cd2 MH |
900 | #interrupt-cells = <1>; |
| 901 | interrupt-map-mask = <0 0 0 7>; | |
| 902 | interrupt-map = <0000 0 0 1 &gic 0 110 0x4>, | |
| 903 | <0000 0 0 2 &gic 0 111 0x4>, | |
| 904 | <0000 0 0 3 &gic 0 112 0x4>, | |
| 905 | <0000 0 0 4 &gic 0 113 0x4>; | |
| 8580b6aa | 906 | fsl,pcie-scfg = <&scfg 0>; |
| 5c4820af | 907 | big-endian; |
| aa2aa888 | 908 | status = "disabled"; |
| 6d453cd2 MH |
909 | }; |
| 910 | ||
| f7d48ffc | 911 | pcie2: pcie@3500000 { |
| 1fa35bc0 | 912 | compatible = "fsl,ls1043a-pcie"; |
| ce87d936 ZL |
913 | reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */ |
| 914 | <0x48 0x00000000 0x0 0x00002000>; /* configuration space */ | |
| 6d453cd2 | 915 | reg-names = "regs", "config"; |
| ee00c1a6 LY |
916 | interrupts = <0 127 IRQ_TYPE_LEVEL_HIGH>, |
| 917 | <0 128 IRQ_TYPE_LEVEL_HIGH>; | |
| 918 | interrupt-names = "pme", "aer"; | |
| 6d453cd2 MH |
919 | #address-cells = <3>; |
| 920 | #size-cells = <2>; | |
| 921 | device_type = "pci"; | |
| 881e90d2 | 922 | num-viewport = <6>; |
| 6d453cd2 MH |
923 | bus-range = <0x0 0xff>; |
| 924 | ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */ | |
| 925 | 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ | |
| 0b09331a | 926 | msi-parent = <&msi1>, <&msi2>, <&msi3>; |
| 6d453cd2 MH |
927 | #interrupt-cells = <1>; |
| 928 | interrupt-map-mask = <0 0 0 7>; | |
| 929 | interrupt-map = <0000 0 0 1 &gic 0 120 0x4>, | |
| 930 | <0000 0 0 2 &gic 0 121 0x4>, | |
| 931 | <0000 0 0 3 &gic 0 122 0x4>, | |
| 932 | <0000 0 0 4 &gic 0 123 0x4>; | |
| 8580b6aa | 933 | fsl,pcie-scfg = <&scfg 1>; |
| 5c4820af | 934 | big-endian; |
| aa2aa888 | 935 | status = "disabled"; |
| 6d453cd2 MH |
936 | }; |
| 937 | ||
| f7d48ffc | 938 | pcie3: pcie@3600000 { |
| 1fa35bc0 | 939 | compatible = "fsl,ls1043a-pcie"; |
| ce87d936 ZL |
940 | reg = <0x00 0x03600000 0x0 0x00100000>, /* controller registers */ |
| 941 | <0x50 0x00000000 0x0 0x00002000>; /* configuration space */ | |
| 6d453cd2 | 942 | reg-names = "regs", "config"; |
| ee00c1a6 LY |
943 | interrupts = <0 161 IRQ_TYPE_LEVEL_HIGH>, |
| 944 | <0 162 IRQ_TYPE_LEVEL_HIGH>; | |
| 945 | interrupt-names = "pme", "aer"; | |
| 6d453cd2 MH |
946 | #address-cells = <3>; |
| 947 | #size-cells = <2>; | |
| 948 | device_type = "pci"; | |
| 881e90d2 | 949 | num-viewport = <6>; |
| 6d453cd2 MH |
950 | bus-range = <0x0 0xff>; |
| 951 | ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */ | |
| 952 | 0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ | |
| 0b09331a | 953 | msi-parent = <&msi1>, <&msi2>, <&msi3>; |
| 6d453cd2 MH |
954 | #interrupt-cells = <1>; |
| 955 | interrupt-map-mask = <0 0 0 7>; | |
| 956 | interrupt-map = <0000 0 0 1 &gic 0 154 0x4>, | |
| 957 | <0000 0 0 2 &gic 0 155 0x4>, | |
| 958 | <0000 0 0 3 &gic 0 156 0x4>, | |
| 959 | <0000 0 0 4 &gic 0 157 0x4>; | |
| 8580b6aa | 960 | fsl,pcie-scfg = <&scfg 2>; |
| 5c4820af | 961 | big-endian; |
| aa2aa888 | 962 | status = "disabled"; |
| 6d453cd2 | 963 | }; |
| 29813f66 PM |
964 | |
| 965 | qdma: dma-controller@8380000 { | |
| 966 | compatible = "fsl,ls1021a-qdma", "fsl,ls1043a-qdma"; | |
| 967 | reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */ | |
| 968 | <0x0 0x8390000 0x0 0x10000>, /* Status regs */ | |
| 969 | <0x0 0x83a0000 0x0 0x40000>; /* Block regs */ | |
| 970 | interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, | |
| 971 | <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, | |
| 972 | <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, | |
| 973 | <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, | |
| 974 | <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; | |
| 975 | interrupt-names = "qdma-error", "qdma-queue0", | |
| 976 | "qdma-queue1", "qdma-queue2", "qdma-queue3"; | |
| 977 | dma-channels = <8>; | |
| 978 | block-number = <1>; | |
| 979 | block-offset = <0x10000>; | |
| 980 | fsl,dma-queues = <2>; | |
| 981 | status-sizes = <64>; | |
| 982 | queue-sizes = <64 64>; | |
| 983 | big-endian; | |
| 984 | }; | |
| 985 | ||
| f4fe3a86 BL |
986 | rcpm: power-controller@1ee2140 { |
| 987 | compatible = "fsl,ls1043a-rcpm", "fsl,qoriq-rcpm-2.1+"; | |
| 988 | reg = <0x0 0x1ee2140 0x0 0x4>; | |
| 989 | #fsl,rcpm-wakeup-cells = <1>; | |
| 990 | }; | |
| 991 | ||
| 992 | ftm_alarm0: timer@29d0000 { | |
| 993 | compatible = "fsl,ls1043a-ftm-alarm"; | |
| 994 | reg = <0x0 0x29d0000 0x0 0x10000>; | |
| 995 | fsl,rcpm-wakeup = <&rcpm 0x20000>; | |
| 996 | interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; | |
| 997 | big-endian; | |
| 998 | }; | |
| 6d453cd2 MH |
999 | }; |
| 1000 | ||
| 51b29445 SG |
1001 | firmware { |
| 1002 | optee { | |
| 1003 | compatible = "linaro,optee-tz"; | |
| 1004 | method = "smc"; | |
| 1005 | }; | |
| 1006 | }; | |
| 1007 | ||
| 6d453cd2 | 1008 | }; |
| 90945593 MB |
1009 | |
| 1010 | #include "qoriq-qman-portals.dtsi" | |
| 1011 | #include "qoriq-bman-portals.dtsi" |