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6d453cd2 MH |
1 | /* |
2 | * Device Tree Include file for Freescale Layerscape-1043A family SoC. | |
3 | * | |
4 | * Copyright 2014-2015, Freescale Semiconductor | |
5 | * | |
6 | * Mingkai Hu <Mingkai.hu@freescale.com> | |
7 | * | |
8 | * This file is dual-licensed: you can use it either under the terms | |
9 | * of the GPLv2 or the X11 license, at your option. Note that this dual | |
10 | * licensing only applies to this file, and not this project as a | |
11 | * whole. | |
12 | * | |
13 | * a) This library is free software; you can redistribute it and/or | |
14 | * modify it under the terms of the GNU General Public License as | |
15 | * published by the Free Software Foundation; either version 2 of the | |
16 | * License, or (at your option) any later version. | |
17 | * | |
18 | * This library is distributed in the hope that it will be useful, | |
19 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
20 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
21 | * GNU General Public License for more details. | |
22 | * | |
23 | * Or, alternatively, | |
24 | * | |
25 | * b) Permission is hereby granted, free of charge, to any person | |
26 | * obtaining a copy of this software and associated documentation | |
27 | * files (the "Software"), to deal in the Software without | |
28 | * restriction, including without limitation the rights to use, | |
29 | * copy, modify, merge, publish, distribute, sublicense, and/or | |
30 | * sell copies of the Software, and to permit persons to whom the | |
31 | * Software is furnished to do so, subject to the following | |
32 | * conditions: | |
33 | * | |
34 | * The above copyright notice and this permission notice shall be | |
35 | * included in all copies or substantial portions of the Software. | |
36 | * | |
37 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
38 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES | |
39 | * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
40 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT | |
41 | * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, | |
42 | * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
43 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
44 | * OTHER DEALINGS IN THE SOFTWARE. | |
45 | */ | |
46 | ||
47 | / { | |
48 | compatible = "fsl,ls1043a"; | |
49 | interrupt-parent = <&gic>; | |
50 | #address-cells = <2>; | |
51 | #size-cells = <2>; | |
52 | ||
53 | cpus { | |
e6d66c50 | 54 | #address-cells = <1>; |
6d453cd2 MH |
55 | #size-cells = <0>; |
56 | ||
57 | /* | |
58 | * We expect the enable-method for cpu's to be "psci", but this | |
59 | * is dependent on the SoC FW, which will fill this in. | |
60 | * | |
61 | * Currently supported enable-method is psci v0.2 | |
62 | */ | |
63 | cpu0: cpu@0 { | |
64 | device_type = "cpu"; | |
65 | compatible = "arm,cortex-a53"; | |
e6d66c50 | 66 | reg = <0x0>; |
6d453cd2 MH |
67 | clocks = <&clockgen 1 0>; |
68 | }; | |
69 | ||
70 | cpu1: cpu@1 { | |
71 | device_type = "cpu"; | |
72 | compatible = "arm,cortex-a53"; | |
e6d66c50 | 73 | reg = <0x1>; |
6d453cd2 MH |
74 | clocks = <&clockgen 1 0>; |
75 | }; | |
76 | ||
77 | cpu2: cpu@2 { | |
78 | device_type = "cpu"; | |
79 | compatible = "arm,cortex-a53"; | |
e6d66c50 | 80 | reg = <0x2>; |
6d453cd2 MH |
81 | clocks = <&clockgen 1 0>; |
82 | }; | |
83 | ||
84 | cpu3: cpu@3 { | |
85 | device_type = "cpu"; | |
86 | compatible = "arm,cortex-a53"; | |
e6d66c50 | 87 | reg = <0x3>; |
6d453cd2 MH |
88 | clocks = <&clockgen 1 0>; |
89 | }; | |
90 | }; | |
91 | ||
92 | memory@80000000 { | |
93 | device_type = "memory"; | |
94 | reg = <0x0 0x80000000 0 0x80000000>; | |
95 | /* DRAM space 1, size: 2GiB DRAM */ | |
96 | }; | |
97 | ||
98 | sysclk: sysclk { | |
99 | compatible = "fixed-clock"; | |
100 | #clock-cells = <0>; | |
101 | clock-frequency = <100000000>; | |
102 | clock-output-names = "sysclk"; | |
103 | }; | |
104 | ||
105 | reboot { | |
106 | compatible ="syscon-reboot"; | |
107 | regmap = <&dcfg>; | |
108 | offset = <0xb0>; | |
109 | mask = <0x02>; | |
110 | }; | |
111 | ||
112 | timer { | |
113 | compatible = "arm,armv8-timer"; | |
114 | interrupts = <1 13 0x1>, /* Physical Secure PPI */ | |
115 | <1 14 0x1>, /* Physical Non-Secure PPI */ | |
116 | <1 11 0x1>, /* Virtual PPI */ | |
117 | <1 10 0x1>; /* Hypervisor PPI */ | |
118 | }; | |
119 | ||
120 | pmu { | |
121 | compatible = "arm,armv8-pmuv3"; | |
122 | interrupts = <0 106 0x4>, | |
123 | <0 107 0x4>, | |
124 | <0 95 0x4>, | |
125 | <0 97 0x4>; | |
126 | interrupt-affinity = <&cpu0>, | |
127 | <&cpu1>, | |
128 | <&cpu2>, | |
129 | <&cpu3>; | |
130 | }; | |
131 | ||
132 | gic: interrupt-controller@1400000 { | |
133 | compatible = "arm,gic-400"; | |
134 | #interrupt-cells = <3>; | |
135 | interrupt-controller; | |
136 | reg = <0x0 0x1401000 0 0x1000>, /* GICD */ | |
137 | <0x0 0x1402000 0 0x2000>, /* GICC */ | |
138 | <0x0 0x1404000 0 0x2000>, /* GICH */ | |
139 | <0x0 0x1406000 0 0x2000>; /* GICV */ | |
140 | interrupts = <1 9 0xf08>; | |
141 | }; | |
142 | ||
143 | soc { | |
144 | compatible = "simple-bus"; | |
145 | #address-cells = <2>; | |
146 | #size-cells = <2>; | |
147 | ranges; | |
148 | ||
149 | clockgen: clocking@1ee1000 { | |
150 | compatible = "fsl,ls1043a-clockgen"; | |
151 | reg = <0x0 0x1ee1000 0x0 0x1000>; | |
152 | #clock-cells = <2>; | |
153 | clocks = <&sysclk>; | |
154 | }; | |
155 | ||
156 | scfg: scfg@1570000 { | |
157 | compatible = "fsl,ls1043a-scfg", "syscon"; | |
158 | reg = <0x0 0x1570000 0x0 0x10000>; | |
159 | big-endian; | |
160 | }; | |
161 | ||
162 | dcfg: dcfg@1ee0000 { | |
163 | compatible = "fsl,ls1043a-dcfg", "syscon"; | |
164 | reg = <0x0 0x1ee0000 0x0 0x10000>; | |
165 | big-endian; | |
166 | }; | |
167 | ||
168 | ifc: ifc@1530000 { | |
169 | compatible = "fsl,ifc", "simple-bus"; | |
170 | reg = <0x0 0x1530000 0x0 0x10000>; | |
171 | interrupts = <0 43 0x4>; | |
172 | }; | |
173 | ||
e26e054b YY |
174 | qspi: quadspi@1550000 { |
175 | compatible = "fsl,ls1043a-qspi", "fsl,ls1021a-qspi"; | |
176 | #address-cells = <1>; | |
177 | #size-cells = <0>; | |
178 | reg = <0x0 0x1550000 0x0 0x10000>, | |
179 | <0x0 0x40000000 0x0 0x4000000>; | |
180 | reg-names = "QuadSPI", "QuadSPI-memory"; | |
181 | interrupts = <0 99 0x4>; | |
182 | clock-names = "qspi_en", "qspi"; | |
183 | clocks = <&clockgen 4 0>, <&clockgen 4 0>; | |
184 | big-endian; | |
185 | status = "disabled"; | |
186 | }; | |
187 | ||
6d453cd2 MH |
188 | esdhc: esdhc@1560000 { |
189 | compatible = "fsl,ls1043a-esdhc", "fsl,esdhc"; | |
190 | reg = <0x0 0x1560000 0x0 0x10000>; | |
191 | interrupts = <0 62 0x4>; | |
192 | clock-frequency = <0>; | |
193 | voltage-ranges = <1800 1800 3300 3300>; | |
194 | sdhci,auto-cmd12; | |
195 | big-endian; | |
196 | bus-width = <4>; | |
197 | }; | |
198 | ||
199 | dspi0: dspi@2100000 { | |
200 | compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi"; | |
201 | #address-cells = <1>; | |
202 | #size-cells = <0>; | |
203 | reg = <0x0 0x2100000 0x0 0x10000>; | |
204 | interrupts = <0 64 0x4>; | |
205 | clock-names = "dspi"; | |
206 | clocks = <&clockgen 4 0>; | |
207 | spi-num-chipselects = <5>; | |
208 | big-endian; | |
209 | status = "disabled"; | |
210 | }; | |
211 | ||
212 | dspi1: dspi@2110000 { | |
213 | compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi"; | |
214 | #address-cells = <1>; | |
215 | #size-cells = <0>; | |
216 | reg = <0x0 0x2110000 0x0 0x10000>; | |
217 | interrupts = <0 65 0x4>; | |
218 | clock-names = "dspi"; | |
219 | clocks = <&clockgen 4 0>; | |
220 | spi-num-chipselects = <5>; | |
221 | big-endian; | |
222 | status = "disabled"; | |
223 | }; | |
224 | ||
225 | i2c0: i2c@2180000 { | |
226 | compatible = "fsl,vf610-i2c"; | |
227 | #address-cells = <1>; | |
228 | #size-cells = <0>; | |
229 | reg = <0x0 0x2180000 0x0 0x10000>; | |
230 | interrupts = <0 56 0x4>; | |
231 | clock-names = "i2c"; | |
232 | clocks = <&clockgen 4 0>; | |
233 | dmas = <&edma0 1 39>, | |
234 | <&edma0 1 38>; | |
235 | dma-names = "tx", "rx"; | |
236 | status = "disabled"; | |
237 | }; | |
238 | ||
239 | i2c1: i2c@2190000 { | |
240 | compatible = "fsl,vf610-i2c"; | |
241 | #address-cells = <1>; | |
242 | #size-cells = <0>; | |
243 | reg = <0x0 0x2190000 0x0 0x10000>; | |
244 | interrupts = <0 57 0x4>; | |
245 | clock-names = "i2c"; | |
246 | clocks = <&clockgen 4 0>; | |
247 | status = "disabled"; | |
248 | }; | |
249 | ||
250 | i2c2: i2c@21a0000 { | |
251 | compatible = "fsl,vf610-i2c"; | |
252 | #address-cells = <1>; | |
253 | #size-cells = <0>; | |
254 | reg = <0x0 0x21a0000 0x0 0x10000>; | |
255 | interrupts = <0 58 0x4>; | |
256 | clock-names = "i2c"; | |
257 | clocks = <&clockgen 4 0>; | |
258 | status = "disabled"; | |
259 | }; | |
260 | ||
261 | i2c3: i2c@21b0000 { | |
262 | compatible = "fsl,vf610-i2c"; | |
263 | #address-cells = <1>; | |
264 | #size-cells = <0>; | |
265 | reg = <0x0 0x21b0000 0x0 0x10000>; | |
266 | interrupts = <0 59 0x4>; | |
267 | clock-names = "i2c"; | |
268 | clocks = <&clockgen 4 0>; | |
269 | status = "disabled"; | |
270 | }; | |
271 | ||
272 | duart0: serial@21c0500 { | |
273 | compatible = "fsl,ns16550", "ns16550a"; | |
274 | reg = <0x00 0x21c0500 0x0 0x100>; | |
275 | interrupts = <0 54 0x4>; | |
276 | clocks = <&clockgen 4 0>; | |
277 | }; | |
278 | ||
279 | duart1: serial@21c0600 { | |
280 | compatible = "fsl,ns16550", "ns16550a"; | |
281 | reg = <0x00 0x21c0600 0x0 0x100>; | |
282 | interrupts = <0 54 0x4>; | |
283 | clocks = <&clockgen 4 0>; | |
284 | }; | |
285 | ||
286 | duart2: serial@21d0500 { | |
287 | compatible = "fsl,ns16550", "ns16550a"; | |
288 | reg = <0x0 0x21d0500 0x0 0x100>; | |
289 | interrupts = <0 55 0x4>; | |
290 | clocks = <&clockgen 4 0>; | |
291 | }; | |
292 | ||
293 | duart3: serial@21d0600 { | |
294 | compatible = "fsl,ns16550", "ns16550a"; | |
295 | reg = <0x0 0x21d0600 0x0 0x100>; | |
296 | interrupts = <0 55 0x4>; | |
297 | clocks = <&clockgen 4 0>; | |
298 | }; | |
299 | ||
300 | gpio1: gpio@2300000 { | |
c21de87d | 301 | compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio"; |
6d453cd2 MH |
302 | reg = <0x0 0x2300000 0x0 0x10000>; |
303 | interrupts = <0 66 0x4>; | |
304 | gpio-controller; | |
305 | #gpio-cells = <2>; | |
306 | interrupt-controller; | |
307 | #interrupt-cells = <2>; | |
308 | }; | |
309 | ||
310 | gpio2: gpio@2310000 { | |
c21de87d | 311 | compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio"; |
6d453cd2 MH |
312 | reg = <0x0 0x2310000 0x0 0x10000>; |
313 | interrupts = <0 67 0x4>; | |
314 | gpio-controller; | |
315 | #gpio-cells = <2>; | |
316 | interrupt-controller; | |
317 | #interrupt-cells = <2>; | |
318 | }; | |
319 | ||
320 | gpio3: gpio@2320000 { | |
c21de87d | 321 | compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio"; |
6d453cd2 MH |
322 | reg = <0x0 0x2320000 0x0 0x10000>; |
323 | interrupts = <0 68 0x4>; | |
324 | gpio-controller; | |
325 | #gpio-cells = <2>; | |
326 | interrupt-controller; | |
327 | #interrupt-cells = <2>; | |
328 | }; | |
329 | ||
330 | gpio4: gpio@2330000 { | |
c21de87d | 331 | compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio"; |
6d453cd2 MH |
332 | reg = <0x0 0x2330000 0x0 0x10000>; |
333 | interrupts = <0 134 0x4>; | |
334 | gpio-controller; | |
335 | #gpio-cells = <2>; | |
336 | interrupt-controller; | |
337 | #interrupt-cells = <2>; | |
338 | }; | |
339 | ||
340 | lpuart0: serial@2950000 { | |
341 | compatible = "fsl,ls1021a-lpuart"; | |
342 | reg = <0x0 0x2950000 0x0 0x1000>; | |
343 | interrupts = <0 48 0x4>; | |
344 | clocks = <&clockgen 0 0>; | |
345 | clock-names = "ipg"; | |
346 | status = "disabled"; | |
347 | }; | |
348 | ||
349 | lpuart1: serial@2960000 { | |
350 | compatible = "fsl,ls1021a-lpuart"; | |
351 | reg = <0x0 0x2960000 0x0 0x1000>; | |
352 | interrupts = <0 49 0x4>; | |
353 | clocks = <&clockgen 4 0>; | |
354 | clock-names = "ipg"; | |
355 | status = "disabled"; | |
356 | }; | |
357 | ||
358 | lpuart2: serial@2970000 { | |
359 | compatible = "fsl,ls1021a-lpuart"; | |
360 | reg = <0x0 0x2970000 0x0 0x1000>; | |
361 | interrupts = <0 50 0x4>; | |
362 | clocks = <&clockgen 4 0>; | |
363 | clock-names = "ipg"; | |
364 | status = "disabled"; | |
365 | }; | |
366 | ||
367 | lpuart3: serial@2980000 { | |
368 | compatible = "fsl,ls1021a-lpuart"; | |
369 | reg = <0x0 0x2980000 0x0 0x1000>; | |
370 | interrupts = <0 51 0x4>; | |
371 | clocks = <&clockgen 4 0>; | |
372 | clock-names = "ipg"; | |
373 | status = "disabled"; | |
374 | }; | |
375 | ||
376 | lpuart4: serial@2990000 { | |
377 | compatible = "fsl,ls1021a-lpuart"; | |
378 | reg = <0x0 0x2990000 0x0 0x1000>; | |
379 | interrupts = <0 52 0x4>; | |
380 | clocks = <&clockgen 4 0>; | |
381 | clock-names = "ipg"; | |
382 | status = "disabled"; | |
383 | }; | |
384 | ||
385 | lpuart5: serial@29a0000 { | |
386 | compatible = "fsl,ls1021a-lpuart"; | |
387 | reg = <0x0 0x29a0000 0x0 0x1000>; | |
388 | interrupts = <0 53 0x4>; | |
389 | clocks = <&clockgen 4 0>; | |
390 | clock-names = "ipg"; | |
391 | status = "disabled"; | |
392 | }; | |
393 | ||
394 | wdog0: wdog@2ad0000 { | |
395 | compatible = "fsl,ls1043a-wdt", "fsl,imx21-wdt"; | |
396 | reg = <0x0 0x2ad0000 0x0 0x10000>; | |
397 | interrupts = <0 83 0x4>; | |
398 | clocks = <&clockgen 4 0>; | |
399 | clock-names = "wdog"; | |
400 | big-endian; | |
401 | }; | |
402 | ||
403 | edma0: edma@2c00000 { | |
404 | #dma-cells = <2>; | |
405 | compatible = "fsl,vf610-edma"; | |
406 | reg = <0x0 0x2c00000 0x0 0x10000>, | |
407 | <0x0 0x2c10000 0x0 0x10000>, | |
408 | <0x0 0x2c20000 0x0 0x10000>; | |
409 | interrupts = <0 103 0x4>, | |
410 | <0 103 0x4>; | |
411 | interrupt-names = "edma-tx", "edma-err"; | |
412 | dma-channels = <32>; | |
413 | big-endian; | |
414 | clock-names = "dmamux0", "dmamux1"; | |
415 | clocks = <&clockgen 4 0>, | |
416 | <&clockgen 4 0>; | |
417 | }; | |
418 | ||
419 | usb0: usb3@2f00000 { | |
420 | compatible = "snps,dwc3"; | |
421 | reg = <0x0 0x2f00000 0x0 0x10000>; | |
422 | interrupts = <0 60 0x4>; | |
423 | dr_mode = "host"; | |
4c1d9ea7 | 424 | snps,quirk-frame-length-adjustment = <0x20>; |
bf26225f | 425 | snps,dis_rxdet_inp3_quirk; |
6d453cd2 MH |
426 | }; |
427 | ||
428 | usb1: usb3@3000000 { | |
429 | compatible = "snps,dwc3"; | |
430 | reg = <0x0 0x3000000 0x0 0x10000>; | |
431 | interrupts = <0 61 0x4>; | |
432 | dr_mode = "host"; | |
4c1d9ea7 | 433 | snps,quirk-frame-length-adjustment = <0x20>; |
bf26225f | 434 | snps,dis_rxdet_inp3_quirk; |
6d453cd2 MH |
435 | }; |
436 | ||
437 | usb2: usb3@3100000 { | |
438 | compatible = "snps,dwc3"; | |
439 | reg = <0x0 0x3100000 0x0 0x10000>; | |
440 | interrupts = <0 63 0x4>; | |
441 | dr_mode = "host"; | |
4c1d9ea7 | 442 | snps,quirk-frame-length-adjustment = <0x20>; |
bf26225f | 443 | snps,dis_rxdet_inp3_quirk; |
6d453cd2 MH |
444 | }; |
445 | ||
446 | sata: sata@3200000 { | |
447 | compatible = "fsl,ls1043a-ahci", "fsl,ls1021a-ahci"; | |
448 | reg = <0x0 0x3200000 0x0 0x10000>; | |
449 | interrupts = <0 69 0x4>; | |
450 | clocks = <&clockgen 4 0>; | |
451 | }; | |
452 | ||
453 | msi1: msi-controller1@1571000 { | |
454 | compatible = "fsl,1s1043a-msi"; | |
455 | reg = <0x0 0x1571000 0x0 0x8>; | |
456 | msi-controller; | |
457 | interrupts = <0 116 0x4>; | |
458 | }; | |
459 | ||
460 | msi2: msi-controller2@1572000 { | |
461 | compatible = "fsl,1s1043a-msi"; | |
462 | reg = <0x0 0x1572000 0x0 0x8>; | |
463 | msi-controller; | |
464 | interrupts = <0 126 0x4>; | |
465 | }; | |
466 | ||
467 | msi3: msi-controller3@1573000 { | |
468 | compatible = "fsl,1s1043a-msi"; | |
469 | reg = <0x0 0x1573000 0x0 0x8>; | |
470 | msi-controller; | |
471 | interrupts = <0 160 0x4>; | |
472 | }; | |
473 | ||
474 | pcie@3400000 { | |
475 | compatible = "fsl,ls1043a-pcie", "snps,dw-pcie"; | |
476 | reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ | |
477 | 0x40 0x00000000 0x0 0x00002000>; /* configuration space */ | |
478 | reg-names = "regs", "config"; | |
479 | interrupts = <0 118 0x4>, /* controller interrupt */ | |
480 | <0 117 0x4>; /* PME interrupt */ | |
481 | interrupt-names = "intr", "pme"; | |
482 | #address-cells = <3>; | |
483 | #size-cells = <2>; | |
484 | device_type = "pci"; | |
485 | num-lanes = <4>; | |
486 | bus-range = <0x0 0xff>; | |
487 | ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */ | |
488 | 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ | |
489 | msi-parent = <&msi1>; | |
490 | #interrupt-cells = <1>; | |
491 | interrupt-map-mask = <0 0 0 7>; | |
492 | interrupt-map = <0000 0 0 1 &gic 0 110 0x4>, | |
493 | <0000 0 0 2 &gic 0 111 0x4>, | |
494 | <0000 0 0 3 &gic 0 112 0x4>, | |
495 | <0000 0 0 4 &gic 0 113 0x4>; | |
496 | }; | |
497 | ||
498 | pcie@3500000 { | |
499 | compatible = "fsl,ls1043a-pcie", "snps,dw-pcie"; | |
500 | reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */ | |
501 | 0x48 0x00000000 0x0 0x00002000>; /* configuration space */ | |
502 | reg-names = "regs", "config"; | |
503 | interrupts = <0 128 0x4>, | |
504 | <0 127 0x4>; | |
505 | interrupt-names = "intr", "pme"; | |
506 | #address-cells = <3>; | |
507 | #size-cells = <2>; | |
508 | device_type = "pci"; | |
509 | num-lanes = <2>; | |
510 | bus-range = <0x0 0xff>; | |
511 | ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */ | |
512 | 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ | |
513 | msi-parent = <&msi2>; | |
514 | #interrupt-cells = <1>; | |
515 | interrupt-map-mask = <0 0 0 7>; | |
516 | interrupt-map = <0000 0 0 1 &gic 0 120 0x4>, | |
517 | <0000 0 0 2 &gic 0 121 0x4>, | |
518 | <0000 0 0 3 &gic 0 122 0x4>, | |
519 | <0000 0 0 4 &gic 0 123 0x4>; | |
520 | }; | |
521 | ||
522 | pcie@3600000 { | |
523 | compatible = "fsl,ls1043a-pcie", "snps,dw-pcie"; | |
524 | reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */ | |
525 | 0x50 0x00000000 0x0 0x00002000>; /* configuration space */ | |
526 | reg-names = "regs", "config"; | |
527 | interrupts = <0 162 0x4>, | |
528 | <0 161 0x4>; | |
529 | interrupt-names = "intr", "pme"; | |
530 | #address-cells = <3>; | |
531 | #size-cells = <2>; | |
532 | device_type = "pci"; | |
533 | num-lanes = <2>; | |
534 | bus-range = <0x0 0xff>; | |
535 | ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */ | |
536 | 0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ | |
537 | msi-parent = <&msi3>; | |
538 | #interrupt-cells = <1>; | |
539 | interrupt-map-mask = <0 0 0 7>; | |
540 | interrupt-map = <0000 0 0 1 &gic 0 154 0x4>, | |
541 | <0000 0 0 2 &gic 0 155 0x4>, | |
542 | <0000 0 0 3 &gic 0 156 0x4>, | |
543 | <0000 0 0 4 &gic 0 157 0x4>; | |
544 | }; | |
545 | }; | |
546 | ||
547 | }; |