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7a2aeb91 | 1 | // SPDX-License-Identifier: (GPL-2.0+ OR MIT) |
6d453cd2 MH |
2 | /* |
3 | * Device Tree Include file for Freescale Layerscape-1043A family SoC. | |
4 | * | |
8637f58b | 5 | * Copyright 2014-2015 Freescale Semiconductor, Inc. |
5b39601c | 6 | * Copyright 2018 NXP |
6d453cd2 MH |
7 | * |
8 | * Mingkai Hu <Mingkai.hu@freescale.com> | |
6d453cd2 MH |
9 | */ |
10 | ||
18486552 | 11 | #include <dt-bindings/thermal/thermal.h> |
90945593 | 12 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
18486552 | 13 | |
6d453cd2 MH |
14 | / { |
15 | compatible = "fsl,ls1043a"; | |
16 | interrupt-parent = <&gic>; | |
17 | #address-cells = <2>; | |
18 | #size-cells = <2>; | |
19 | ||
bf02f2ff MB |
20 | aliases { |
21 | fman0 = &fman0; | |
22 | ethernet0 = &enet0; | |
23 | ethernet1 = &enet1; | |
24 | ethernet2 = &enet2; | |
25 | ethernet3 = &enet3; | |
26 | ethernet4 = &enet4; | |
27 | ethernet5 = &enet5; | |
28 | ethernet6 = &enet6; | |
29 | }; | |
30 | ||
6d453cd2 | 31 | cpus { |
e6d66c50 | 32 | #address-cells = <1>; |
6d453cd2 MH |
33 | #size-cells = <0>; |
34 | ||
35 | /* | |
36 | * We expect the enable-method for cpu's to be "psci", but this | |
37 | * is dependent on the SoC FW, which will fill this in. | |
38 | * | |
39 | * Currently supported enable-method is psci v0.2 | |
40 | */ | |
41 | cpu0: cpu@0 { | |
42 | device_type = "cpu"; | |
43 | compatible = "arm,cortex-a53"; | |
e6d66c50 | 44 | reg = <0x0>; |
6d453cd2 | 45 | clocks = <&clockgen 1 0>; |
ec049f33 | 46 | next-level-cache = <&l2>; |
3fd366d8 | 47 | cpu-idle-states = <&CPU_PH20>; |
346f5976 | 48 | #cooling-cells = <2>; |
6d453cd2 MH |
49 | }; |
50 | ||
51 | cpu1: cpu@1 { | |
52 | device_type = "cpu"; | |
53 | compatible = "arm,cortex-a53"; | |
e6d66c50 | 54 | reg = <0x1>; |
6d453cd2 | 55 | clocks = <&clockgen 1 0>; |
ec049f33 | 56 | next-level-cache = <&l2>; |
3fd366d8 | 57 | cpu-idle-states = <&CPU_PH20>; |
346f5976 | 58 | #cooling-cells = <2>; |
6d453cd2 MH |
59 | }; |
60 | ||
61 | cpu2: cpu@2 { | |
62 | device_type = "cpu"; | |
63 | compatible = "arm,cortex-a53"; | |
e6d66c50 | 64 | reg = <0x2>; |
6d453cd2 | 65 | clocks = <&clockgen 1 0>; |
ec049f33 | 66 | next-level-cache = <&l2>; |
3fd366d8 | 67 | cpu-idle-states = <&CPU_PH20>; |
346f5976 | 68 | #cooling-cells = <2>; |
6d453cd2 MH |
69 | }; |
70 | ||
71 | cpu3: cpu@3 { | |
72 | device_type = "cpu"; | |
73 | compatible = "arm,cortex-a53"; | |
e6d66c50 | 74 | reg = <0x3>; |
6d453cd2 | 75 | clocks = <&clockgen 1 0>; |
ec049f33 | 76 | next-level-cache = <&l2>; |
3fd366d8 | 77 | cpu-idle-states = <&CPU_PH20>; |
346f5976 | 78 | #cooling-cells = <2>; |
ec049f33 LY |
79 | }; |
80 | ||
81 | l2: l2-cache { | |
82 | compatible = "cache"; | |
6d453cd2 MH |
83 | }; |
84 | }; | |
85 | ||
3fd366d8 YT |
86 | idle-states { |
87 | /* | |
88 | * PSCI node is not added default, U-boot will add missing | |
89 | * parts if it determines to use PSCI. | |
90 | */ | |
e9880240 | 91 | entry-method = "psci"; |
3fd366d8 YT |
92 | |
93 | CPU_PH20: cpu-ph20 { | |
94 | compatible = "arm,idle-state"; | |
95 | idle-state-name = "PH20"; | |
69ea29b0 | 96 | arm,psci-suspend-param = <0x0>; |
3fd366d8 YT |
97 | entry-latency-us = <1000>; |
98 | exit-latency-us = <1000>; | |
99 | min-residency-us = <3000>; | |
100 | }; | |
101 | }; | |
102 | ||
6d453cd2 MH |
103 | memory@80000000 { |
104 | device_type = "memory"; | |
105 | reg = <0x0 0x80000000 0 0x80000000>; | |
106 | /* DRAM space 1, size: 2GiB DRAM */ | |
107 | }; | |
108 | ||
90945593 MB |
109 | reserved-memory { |
110 | #address-cells = <2>; | |
111 | #size-cells = <2>; | |
112 | ranges; | |
113 | ||
114 | bman_fbpr: bman-fbpr { | |
115 | compatible = "shared-dma-pool"; | |
116 | size = <0 0x1000000>; | |
117 | alignment = <0 0x1000000>; | |
118 | no-map; | |
119 | }; | |
120 | ||
121 | qman_fqd: qman-fqd { | |
122 | compatible = "shared-dma-pool"; | |
123 | size = <0 0x400000>; | |
124 | alignment = <0 0x400000>; | |
125 | no-map; | |
126 | }; | |
127 | ||
128 | qman_pfdr: qman-pfdr { | |
129 | compatible = "shared-dma-pool"; | |
130 | size = <0 0x2000000>; | |
131 | alignment = <0 0x2000000>; | |
132 | no-map; | |
133 | }; | |
134 | }; | |
135 | ||
6d453cd2 MH |
136 | sysclk: sysclk { |
137 | compatible = "fixed-clock"; | |
138 | #clock-cells = <0>; | |
139 | clock-frequency = <100000000>; | |
140 | clock-output-names = "sysclk"; | |
141 | }; | |
142 | ||
143 | reboot { | |
144 | compatible ="syscon-reboot"; | |
145 | regmap = <&dcfg>; | |
146 | offset = <0xb0>; | |
147 | mask = <0x02>; | |
148 | }; | |
149 | ||
0abe2a16 FE |
150 | thermal-zones { |
151 | cpu_thermal: cpu-thermal { | |
152 | polling-delay-passive = <1000>; | |
153 | polling-delay = <5000>; | |
154 | ||
155 | thermal-sensors = <&tmu 3>; | |
156 | ||
157 | trips { | |
158 | cpu_alert: cpu-alert { | |
159 | temperature = <85000>; | |
160 | hysteresis = <2000>; | |
161 | type = "passive"; | |
162 | }; | |
163 | cpu_crit: cpu-crit { | |
164 | temperature = <95000>; | |
165 | hysteresis = <2000>; | |
166 | type = "critical"; | |
167 | }; | |
168 | }; | |
169 | ||
170 | cooling-maps { | |
171 | map0 { | |
172 | trip = <&cpu_alert>; | |
173 | cooling-device = | |
174 | <&cpu0 THERMAL_NO_LIMIT | |
175 | THERMAL_NO_LIMIT>; | |
176 | }; | |
177 | }; | |
178 | }; | |
179 | }; | |
180 | ||
6d453cd2 MH |
181 | timer { |
182 | compatible = "arm,armv8-timer"; | |
f2a89d3b MZ |
183 | interrupts = <1 13 0xf08>, /* Physical Secure PPI */ |
184 | <1 14 0xf08>, /* Physical Non-Secure PPI */ | |
185 | <1 11 0xf08>, /* Virtual PPI */ | |
186 | <1 10 0xf08>; /* Hypervisor PPI */ | |
6a34e0e6 | 187 | fsl,erratum-a008585; |
6d453cd2 MH |
188 | }; |
189 | ||
190 | pmu { | |
191 | compatible = "arm,armv8-pmuv3"; | |
192 | interrupts = <0 106 0x4>, | |
193 | <0 107 0x4>, | |
194 | <0 95 0x4>, | |
195 | <0 97 0x4>; | |
196 | interrupt-affinity = <&cpu0>, | |
197 | <&cpu1>, | |
198 | <&cpu2>, | |
199 | <&cpu3>; | |
200 | }; | |
201 | ||
202 | gic: interrupt-controller@1400000 { | |
203 | compatible = "arm,gic-400"; | |
204 | #interrupt-cells = <3>; | |
205 | interrupt-controller; | |
206 | reg = <0x0 0x1401000 0 0x1000>, /* GICD */ | |
207 | <0x0 0x1402000 0 0x2000>, /* GICC */ | |
208 | <0x0 0x1404000 0 0x2000>, /* GICH */ | |
209 | <0x0 0x1406000 0 0x2000>; /* GICV */ | |
210 | interrupts = <1 9 0xf08>; | |
211 | }; | |
212 | ||
bf02f2ff | 213 | soc: soc { |
6d453cd2 MH |
214 | compatible = "simple-bus"; |
215 | #address-cells = <2>; | |
216 | #size-cells = <2>; | |
217 | ranges; | |
218 | ||
219 | clockgen: clocking@1ee1000 { | |
220 | compatible = "fsl,ls1043a-clockgen"; | |
221 | reg = <0x0 0x1ee1000 0x0 0x1000>; | |
222 | #clock-cells = <2>; | |
223 | clocks = <&sysclk>; | |
224 | }; | |
225 | ||
226 | scfg: scfg@1570000 { | |
227 | compatible = "fsl,ls1043a-scfg", "syscon"; | |
228 | reg = <0x0 0x1570000 0x0 0x10000>; | |
229 | big-endian; | |
230 | }; | |
231 | ||
63dac35b HG |
232 | crypto: crypto@1700000 { |
233 | compatible = "fsl,sec-v5.4", "fsl,sec-v5.0", | |
234 | "fsl,sec-v4.0"; | |
235 | fsl,sec-era = <3>; | |
236 | #address-cells = <1>; | |
237 | #size-cells = <1>; | |
238 | ranges = <0x0 0x00 0x1700000 0x100000>; | |
239 | reg = <0x00 0x1700000 0x0 0x100000>; | |
240 | interrupts = <0 75 0x4>; | |
241 | ||
242 | sec_jr0: jr@10000 { | |
243 | compatible = "fsl,sec-v5.4-job-ring", | |
244 | "fsl,sec-v5.0-job-ring", | |
245 | "fsl,sec-v4.0-job-ring"; | |
246 | reg = <0x10000 0x10000>; | |
247 | interrupts = <0 71 0x4>; | |
248 | }; | |
249 | ||
250 | sec_jr1: jr@20000 { | |
251 | compatible = "fsl,sec-v5.4-job-ring", | |
252 | "fsl,sec-v5.0-job-ring", | |
253 | "fsl,sec-v4.0-job-ring"; | |
254 | reg = <0x20000 0x10000>; | |
255 | interrupts = <0 72 0x4>; | |
256 | }; | |
257 | ||
258 | sec_jr2: jr@30000 { | |
259 | compatible = "fsl,sec-v5.4-job-ring", | |
260 | "fsl,sec-v5.0-job-ring", | |
261 | "fsl,sec-v4.0-job-ring"; | |
262 | reg = <0x30000 0x10000>; | |
263 | interrupts = <0 73 0x4>; | |
264 | }; | |
265 | ||
266 | sec_jr3: jr@40000 { | |
267 | compatible = "fsl,sec-v5.4-job-ring", | |
268 | "fsl,sec-v5.0-job-ring", | |
269 | "fsl,sec-v4.0-job-ring"; | |
270 | reg = <0x40000 0x10000>; | |
271 | interrupts = <0 74 0x4>; | |
272 | }; | |
273 | }; | |
274 | ||
6d453cd2 MH |
275 | dcfg: dcfg@1ee0000 { |
276 | compatible = "fsl,ls1043a-dcfg", "syscon"; | |
277 | reg = <0x0 0x1ee0000 0x0 0x10000>; | |
278 | big-endian; | |
279 | }; | |
280 | ||
281 | ifc: ifc@1530000 { | |
282 | compatible = "fsl,ifc", "simple-bus"; | |
283 | reg = <0x0 0x1530000 0x0 0x10000>; | |
284 | interrupts = <0 43 0x4>; | |
285 | }; | |
286 | ||
b739c177 | 287 | qspi: spi@1550000 { |
e26e054b YY |
288 | compatible = "fsl,ls1043a-qspi", "fsl,ls1021a-qspi"; |
289 | #address-cells = <1>; | |
290 | #size-cells = <0>; | |
291 | reg = <0x0 0x1550000 0x0 0x10000>, | |
292 | <0x0 0x40000000 0x0 0x4000000>; | |
293 | reg-names = "QuadSPI", "QuadSPI-memory"; | |
294 | interrupts = <0 99 0x4>; | |
295 | clock-names = "qspi_en", "qspi"; | |
296 | clocks = <&clockgen 4 0>, <&clockgen 4 0>; | |
297 | big-endian; | |
298 | status = "disabled"; | |
299 | }; | |
300 | ||
6d453cd2 MH |
301 | esdhc: esdhc@1560000 { |
302 | compatible = "fsl,ls1043a-esdhc", "fsl,esdhc"; | |
303 | reg = <0x0 0x1560000 0x0 0x10000>; | |
304 | interrupts = <0 62 0x4>; | |
305 | clock-frequency = <0>; | |
306 | voltage-ranges = <1800 1800 3300 3300>; | |
307 | sdhci,auto-cmd12; | |
308 | big-endian; | |
309 | bus-width = <4>; | |
310 | }; | |
311 | ||
30062fb0 YS |
312 | ddr: memory-controller@1080000 { |
313 | compatible = "fsl,qoriq-memory-controller"; | |
314 | reg = <0x0 0x1080000 0x0 0x1000>; | |
315 | interrupts = <0 144 0x4>; | |
316 | big-endian; | |
317 | }; | |
318 | ||
18486552 HJ |
319 | tmu: tmu@1f00000 { |
320 | compatible = "fsl,qoriq-tmu"; | |
321 | reg = <0x0 0x1f00000 0x0 0x10000>; | |
322 | interrupts = <0 33 0x4>; | |
323 | fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>; | |
324 | fsl,tmu-calibration = <0x00000000 0x00000026 | |
325 | 0x00000001 0x0000002d | |
326 | 0x00000002 0x00000032 | |
327 | 0x00000003 0x00000039 | |
328 | 0x00000004 0x0000003f | |
329 | 0x00000005 0x00000046 | |
330 | 0x00000006 0x0000004d | |
331 | 0x00000007 0x00000054 | |
332 | 0x00000008 0x0000005a | |
333 | 0x00000009 0x00000061 | |
334 | 0x0000000a 0x0000006a | |
335 | 0x0000000b 0x00000071 | |
336 | ||
337 | 0x00010000 0x00000025 | |
338 | 0x00010001 0x0000002c | |
339 | 0x00010002 0x00000035 | |
340 | 0x00010003 0x0000003d | |
341 | 0x00010004 0x00000045 | |
342 | 0x00010005 0x0000004e | |
343 | 0x00010006 0x00000057 | |
344 | 0x00010007 0x00000061 | |
345 | 0x00010008 0x0000006b | |
346 | 0x00010009 0x00000076 | |
347 | ||
348 | 0x00020000 0x00000029 | |
349 | 0x00020001 0x00000033 | |
350 | 0x00020002 0x0000003d | |
351 | 0x00020003 0x00000049 | |
352 | 0x00020004 0x00000056 | |
353 | 0x00020005 0x00000061 | |
354 | 0x00020006 0x0000006d | |
355 | ||
356 | 0x00030000 0x00000021 | |
357 | 0x00030001 0x0000002a | |
358 | 0x00030002 0x0000003c | |
359 | 0x00030003 0x0000004e>; | |
360 | #thermal-sensor-cells = <1>; | |
361 | }; | |
362 | ||
90945593 MB |
363 | qman: qman@1880000 { |
364 | compatible = "fsl,qman"; | |
365 | reg = <0x0 0x1880000 0x0 0x10000>; | |
e54b911f | 366 | interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; |
90945593 MB |
367 | memory-region = <&qman_fqd &qman_pfdr>; |
368 | }; | |
369 | ||
370 | bman: bman@1890000 { | |
371 | compatible = "fsl,bman"; | |
372 | reg = <0x0 0x1890000 0x0 0x10000>; | |
e54b911f | 373 | interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; |
90945593 MB |
374 | memory-region = <&bman_fbpr>; |
375 | }; | |
376 | ||
377 | bportals: bman-portals@508000000 { | |
378 | ranges = <0x0 0x5 0x08000000 0x8000000>; | |
379 | }; | |
380 | ||
381 | qportals: qman-portals@500000000 { | |
382 | ranges = <0x0 0x5 0x00000000 0x8000000>; | |
383 | }; | |
384 | ||
b739c177 | 385 | dspi0: spi@2100000 { |
6d453cd2 MH |
386 | compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi"; |
387 | #address-cells = <1>; | |
388 | #size-cells = <0>; | |
389 | reg = <0x0 0x2100000 0x0 0x10000>; | |
390 | interrupts = <0 64 0x4>; | |
391 | clock-names = "dspi"; | |
392 | clocks = <&clockgen 4 0>; | |
393 | spi-num-chipselects = <5>; | |
394 | big-endian; | |
395 | status = "disabled"; | |
396 | }; | |
397 | ||
b739c177 | 398 | dspi1: spi@2110000 { |
6d453cd2 MH |
399 | compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi"; |
400 | #address-cells = <1>; | |
401 | #size-cells = <0>; | |
402 | reg = <0x0 0x2110000 0x0 0x10000>; | |
403 | interrupts = <0 65 0x4>; | |
404 | clock-names = "dspi"; | |
405 | clocks = <&clockgen 4 0>; | |
406 | spi-num-chipselects = <5>; | |
407 | big-endian; | |
408 | status = "disabled"; | |
409 | }; | |
410 | ||
411 | i2c0: i2c@2180000 { | |
412 | compatible = "fsl,vf610-i2c"; | |
413 | #address-cells = <1>; | |
414 | #size-cells = <0>; | |
415 | reg = <0x0 0x2180000 0x0 0x10000>; | |
416 | interrupts = <0 56 0x4>; | |
417 | clock-names = "i2c"; | |
418 | clocks = <&clockgen 4 0>; | |
419 | dmas = <&edma0 1 39>, | |
420 | <&edma0 1 38>; | |
421 | dma-names = "tx", "rx"; | |
422 | status = "disabled"; | |
423 | }; | |
424 | ||
425 | i2c1: i2c@2190000 { | |
426 | compatible = "fsl,vf610-i2c"; | |
427 | #address-cells = <1>; | |
428 | #size-cells = <0>; | |
429 | reg = <0x0 0x2190000 0x0 0x10000>; | |
430 | interrupts = <0 57 0x4>; | |
431 | clock-names = "i2c"; | |
432 | clocks = <&clockgen 4 0>; | |
433 | status = "disabled"; | |
434 | }; | |
435 | ||
436 | i2c2: i2c@21a0000 { | |
437 | compatible = "fsl,vf610-i2c"; | |
438 | #address-cells = <1>; | |
439 | #size-cells = <0>; | |
440 | reg = <0x0 0x21a0000 0x0 0x10000>; | |
441 | interrupts = <0 58 0x4>; | |
442 | clock-names = "i2c"; | |
443 | clocks = <&clockgen 4 0>; | |
444 | status = "disabled"; | |
445 | }; | |
446 | ||
447 | i2c3: i2c@21b0000 { | |
448 | compatible = "fsl,vf610-i2c"; | |
449 | #address-cells = <1>; | |
450 | #size-cells = <0>; | |
451 | reg = <0x0 0x21b0000 0x0 0x10000>; | |
452 | interrupts = <0 59 0x4>; | |
453 | clock-names = "i2c"; | |
454 | clocks = <&clockgen 4 0>; | |
455 | status = "disabled"; | |
456 | }; | |
457 | ||
458 | duart0: serial@21c0500 { | |
459 | compatible = "fsl,ns16550", "ns16550a"; | |
460 | reg = <0x00 0x21c0500 0x0 0x100>; | |
461 | interrupts = <0 54 0x4>; | |
462 | clocks = <&clockgen 4 0>; | |
463 | }; | |
464 | ||
465 | duart1: serial@21c0600 { | |
466 | compatible = "fsl,ns16550", "ns16550a"; | |
467 | reg = <0x00 0x21c0600 0x0 0x100>; | |
468 | interrupts = <0 54 0x4>; | |
469 | clocks = <&clockgen 4 0>; | |
470 | }; | |
471 | ||
472 | duart2: serial@21d0500 { | |
473 | compatible = "fsl,ns16550", "ns16550a"; | |
474 | reg = <0x0 0x21d0500 0x0 0x100>; | |
475 | interrupts = <0 55 0x4>; | |
476 | clocks = <&clockgen 4 0>; | |
477 | }; | |
478 | ||
479 | duart3: serial@21d0600 { | |
480 | compatible = "fsl,ns16550", "ns16550a"; | |
481 | reg = <0x0 0x21d0600 0x0 0x100>; | |
482 | interrupts = <0 55 0x4>; | |
483 | clocks = <&clockgen 4 0>; | |
484 | }; | |
485 | ||
486 | gpio1: gpio@2300000 { | |
c21de87d | 487 | compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio"; |
6d453cd2 MH |
488 | reg = <0x0 0x2300000 0x0 0x10000>; |
489 | interrupts = <0 66 0x4>; | |
490 | gpio-controller; | |
491 | #gpio-cells = <2>; | |
492 | interrupt-controller; | |
493 | #interrupt-cells = <2>; | |
494 | }; | |
495 | ||
496 | gpio2: gpio@2310000 { | |
c21de87d | 497 | compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio"; |
6d453cd2 MH |
498 | reg = <0x0 0x2310000 0x0 0x10000>; |
499 | interrupts = <0 67 0x4>; | |
500 | gpio-controller; | |
501 | #gpio-cells = <2>; | |
502 | interrupt-controller; | |
503 | #interrupt-cells = <2>; | |
504 | }; | |
505 | ||
506 | gpio3: gpio@2320000 { | |
c21de87d | 507 | compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio"; |
6d453cd2 MH |
508 | reg = <0x0 0x2320000 0x0 0x10000>; |
509 | interrupts = <0 68 0x4>; | |
510 | gpio-controller; | |
511 | #gpio-cells = <2>; | |
512 | interrupt-controller; | |
513 | #interrupt-cells = <2>; | |
514 | }; | |
515 | ||
516 | gpio4: gpio@2330000 { | |
c21de87d | 517 | compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio"; |
6d453cd2 MH |
518 | reg = <0x0 0x2330000 0x0 0x10000>; |
519 | interrupts = <0 134 0x4>; | |
520 | gpio-controller; | |
521 | #gpio-cells = <2>; | |
522 | interrupt-controller; | |
523 | #interrupt-cells = <2>; | |
524 | }; | |
525 | ||
526 | lpuart0: serial@2950000 { | |
527 | compatible = "fsl,ls1021a-lpuart"; | |
528 | reg = <0x0 0x2950000 0x0 0x1000>; | |
529 | interrupts = <0 48 0x4>; | |
530 | clocks = <&clockgen 0 0>; | |
531 | clock-names = "ipg"; | |
532 | status = "disabled"; | |
533 | }; | |
534 | ||
535 | lpuart1: serial@2960000 { | |
536 | compatible = "fsl,ls1021a-lpuart"; | |
537 | reg = <0x0 0x2960000 0x0 0x1000>; | |
538 | interrupts = <0 49 0x4>; | |
539 | clocks = <&clockgen 4 0>; | |
540 | clock-names = "ipg"; | |
541 | status = "disabled"; | |
542 | }; | |
543 | ||
544 | lpuart2: serial@2970000 { | |
545 | compatible = "fsl,ls1021a-lpuart"; | |
546 | reg = <0x0 0x2970000 0x0 0x1000>; | |
547 | interrupts = <0 50 0x4>; | |
548 | clocks = <&clockgen 4 0>; | |
549 | clock-names = "ipg"; | |
550 | status = "disabled"; | |
551 | }; | |
552 | ||
553 | lpuart3: serial@2980000 { | |
554 | compatible = "fsl,ls1021a-lpuart"; | |
555 | reg = <0x0 0x2980000 0x0 0x1000>; | |
556 | interrupts = <0 51 0x4>; | |
557 | clocks = <&clockgen 4 0>; | |
558 | clock-names = "ipg"; | |
559 | status = "disabled"; | |
560 | }; | |
561 | ||
562 | lpuart4: serial@2990000 { | |
563 | compatible = "fsl,ls1021a-lpuart"; | |
564 | reg = <0x0 0x2990000 0x0 0x1000>; | |
565 | interrupts = <0 52 0x4>; | |
566 | clocks = <&clockgen 4 0>; | |
567 | clock-names = "ipg"; | |
568 | status = "disabled"; | |
569 | }; | |
570 | ||
571 | lpuart5: serial@29a0000 { | |
572 | compatible = "fsl,ls1021a-lpuart"; | |
573 | reg = <0x0 0x29a0000 0x0 0x1000>; | |
574 | interrupts = <0 53 0x4>; | |
575 | clocks = <&clockgen 4 0>; | |
576 | clock-names = "ipg"; | |
577 | status = "disabled"; | |
578 | }; | |
579 | ||
580 | wdog0: wdog@2ad0000 { | |
581 | compatible = "fsl,ls1043a-wdt", "fsl,imx21-wdt"; | |
582 | reg = <0x0 0x2ad0000 0x0 0x10000>; | |
583 | interrupts = <0 83 0x4>; | |
584 | clocks = <&clockgen 4 0>; | |
585 | clock-names = "wdog"; | |
586 | big-endian; | |
587 | }; | |
588 | ||
589 | edma0: edma@2c00000 { | |
590 | #dma-cells = <2>; | |
591 | compatible = "fsl,vf610-edma"; | |
592 | reg = <0x0 0x2c00000 0x0 0x10000>, | |
593 | <0x0 0x2c10000 0x0 0x10000>, | |
594 | <0x0 0x2c20000 0x0 0x10000>; | |
595 | interrupts = <0 103 0x4>, | |
596 | <0 103 0x4>; | |
597 | interrupt-names = "edma-tx", "edma-err"; | |
598 | dma-channels = <32>; | |
599 | big-endian; | |
600 | clock-names = "dmamux0", "dmamux1"; | |
601 | clocks = <&clockgen 4 0>, | |
602 | <&clockgen 4 0>; | |
603 | }; | |
604 | ||
605 | usb0: usb3@2f00000 { | |
606 | compatible = "snps,dwc3"; | |
607 | reg = <0x0 0x2f00000 0x0 0x10000>; | |
608 | interrupts = <0 60 0x4>; | |
609 | dr_mode = "host"; | |
4c1d9ea7 | 610 | snps,quirk-frame-length-adjustment = <0x20>; |
bf26225f | 611 | snps,dis_rxdet_inp3_quirk; |
6d453cd2 MH |
612 | }; |
613 | ||
614 | usb1: usb3@3000000 { | |
615 | compatible = "snps,dwc3"; | |
616 | reg = <0x0 0x3000000 0x0 0x10000>; | |
617 | interrupts = <0 61 0x4>; | |
618 | dr_mode = "host"; | |
4c1d9ea7 | 619 | snps,quirk-frame-length-adjustment = <0x20>; |
bf26225f | 620 | snps,dis_rxdet_inp3_quirk; |
6d453cd2 MH |
621 | }; |
622 | ||
623 | usb2: usb3@3100000 { | |
624 | compatible = "snps,dwc3"; | |
625 | reg = <0x0 0x3100000 0x0 0x10000>; | |
626 | interrupts = <0 63 0x4>; | |
627 | dr_mode = "host"; | |
4c1d9ea7 | 628 | snps,quirk-frame-length-adjustment = <0x20>; |
bf26225f | 629 | snps,dis_rxdet_inp3_quirk; |
6d453cd2 MH |
630 | }; |
631 | ||
632 | sata: sata@3200000 { | |
16af080e | 633 | compatible = "fsl,ls1043a-ahci"; |
85f1dfae TY |
634 | reg = <0x0 0x3200000 0x0 0x10000>, |
635 | <0x0 0x20140520 0x0 0x4>; | |
636 | reg-names = "ahci", "sata-ecc"; | |
6d453cd2 MH |
637 | interrupts = <0 69 0x4>; |
638 | clocks = <&clockgen 4 0>; | |
16af080e | 639 | dma-coherent; |
6d453cd2 MH |
640 | }; |
641 | ||
642 | msi1: msi-controller1@1571000 { | |
f93aff62 | 643 | compatible = "fsl,ls1043a-msi"; |
6d453cd2 MH |
644 | reg = <0x0 0x1571000 0x0 0x8>; |
645 | msi-controller; | |
646 | interrupts = <0 116 0x4>; | |
647 | }; | |
648 | ||
649 | msi2: msi-controller2@1572000 { | |
f93aff62 | 650 | compatible = "fsl,ls1043a-msi"; |
6d453cd2 MH |
651 | reg = <0x0 0x1572000 0x0 0x8>; |
652 | msi-controller; | |
653 | interrupts = <0 126 0x4>; | |
654 | }; | |
655 | ||
656 | msi3: msi-controller3@1573000 { | |
f93aff62 | 657 | compatible = "fsl,ls1043a-msi"; |
6d453cd2 MH |
658 | reg = <0x0 0x1573000 0x0 0x8>; |
659 | msi-controller; | |
660 | interrupts = <0 160 0x4>; | |
661 | }; | |
662 | ||
663 | pcie@3400000 { | |
664 | compatible = "fsl,ls1043a-pcie", "snps,dw-pcie"; | |
665 | reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ | |
666 | 0x40 0x00000000 0x0 0x00002000>; /* configuration space */ | |
667 | reg-names = "regs", "config"; | |
668 | interrupts = <0 118 0x4>, /* controller interrupt */ | |
669 | <0 117 0x4>; /* PME interrupt */ | |
670 | interrupt-names = "intr", "pme"; | |
671 | #address-cells = <3>; | |
672 | #size-cells = <2>; | |
673 | device_type = "pci"; | |
f8ed1d9b | 674 | dma-coherent; |
6d453cd2 MH |
675 | num-lanes = <4>; |
676 | bus-range = <0x0 0xff>; | |
677 | ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */ | |
678 | 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ | |
0b09331a | 679 | msi-parent = <&msi1>, <&msi2>, <&msi3>; |
6d453cd2 MH |
680 | #interrupt-cells = <1>; |
681 | interrupt-map-mask = <0 0 0 7>; | |
682 | interrupt-map = <0000 0 0 1 &gic 0 110 0x4>, | |
683 | <0000 0 0 2 &gic 0 111 0x4>, | |
684 | <0000 0 0 3 &gic 0 112 0x4>, | |
685 | <0000 0 0 4 &gic 0 113 0x4>; | |
686 | }; | |
687 | ||
688 | pcie@3500000 { | |
689 | compatible = "fsl,ls1043a-pcie", "snps,dw-pcie"; | |
690 | reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */ | |
691 | 0x48 0x00000000 0x0 0x00002000>; /* configuration space */ | |
692 | reg-names = "regs", "config"; | |
693 | interrupts = <0 128 0x4>, | |
694 | <0 127 0x4>; | |
695 | interrupt-names = "intr", "pme"; | |
696 | #address-cells = <3>; | |
697 | #size-cells = <2>; | |
698 | device_type = "pci"; | |
f8ed1d9b | 699 | dma-coherent; |
6d453cd2 MH |
700 | num-lanes = <2>; |
701 | bus-range = <0x0 0xff>; | |
702 | ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */ | |
703 | 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ | |
0b09331a | 704 | msi-parent = <&msi1>, <&msi2>, <&msi3>; |
6d453cd2 MH |
705 | #interrupt-cells = <1>; |
706 | interrupt-map-mask = <0 0 0 7>; | |
707 | interrupt-map = <0000 0 0 1 &gic 0 120 0x4>, | |
708 | <0000 0 0 2 &gic 0 121 0x4>, | |
709 | <0000 0 0 3 &gic 0 122 0x4>, | |
710 | <0000 0 0 4 &gic 0 123 0x4>; | |
711 | }; | |
712 | ||
713 | pcie@3600000 { | |
714 | compatible = "fsl,ls1043a-pcie", "snps,dw-pcie"; | |
715 | reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */ | |
716 | 0x50 0x00000000 0x0 0x00002000>; /* configuration space */ | |
717 | reg-names = "regs", "config"; | |
718 | interrupts = <0 162 0x4>, | |
719 | <0 161 0x4>; | |
720 | interrupt-names = "intr", "pme"; | |
721 | #address-cells = <3>; | |
722 | #size-cells = <2>; | |
723 | device_type = "pci"; | |
f8ed1d9b | 724 | dma-coherent; |
6d453cd2 MH |
725 | num-lanes = <2>; |
726 | bus-range = <0x0 0xff>; | |
727 | ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */ | |
728 | 0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ | |
0b09331a | 729 | msi-parent = <&msi1>, <&msi2>, <&msi3>; |
6d453cd2 MH |
730 | #interrupt-cells = <1>; |
731 | interrupt-map-mask = <0 0 0 7>; | |
732 | interrupt-map = <0000 0 0 1 &gic 0 154 0x4>, | |
733 | <0000 0 0 2 &gic 0 155 0x4>, | |
734 | <0000 0 0 3 &gic 0 156 0x4>, | |
735 | <0000 0 0 4 &gic 0 157 0x4>; | |
736 | }; | |
737 | }; | |
738 | ||
51b29445 SG |
739 | firmware { |
740 | optee { | |
741 | compatible = "linaro,optee-tz"; | |
742 | method = "smc"; | |
743 | }; | |
744 | }; | |
745 | ||
6d453cd2 | 746 | }; |
90945593 MB |
747 | |
748 | #include "qoriq-qman-portals.dtsi" | |
749 | #include "qoriq-bman-portals.dtsi" |