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arm64: dts: Add ARM PMU node for exynos7
[linux-2.6-block.git] / arch / arm64 / boot / dts / exynos / exynos5433.dtsi
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5f04c4cf
CC		 1/*
2 * Samsung's Exynos5433 SoC device tree source
3 *
4 * Copyright (c) 2016 Samsung Electronics Co., Ltd.
5 *
6 * Samsung's Exynos5433 SoC device nodes are listed in this file.
7 * Exynos5433 based board files can include this file and provide
8 * values for board specific bindings.
9 *
10 * Note: This file does not include device nodes for all the controllers in
11 * Exynos5433 SoC. As device tree coverage for Exynos5433 increases,
12 * additional nodes can be added to this file.
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
17 */
18
19#include <dt-bindings/clock/exynos5433.h>
20#include <dt-bindings/interrupt-controller/arm-gic.h>
21
22/ {
23 compatible = "samsung,exynos5433";
24 #address-cells = <2>;
25 #size-cells = <2>;
26
27 interrupt-parent = <&gic>;
28
29 cpus {
30 #address-cells = <1>;
31 #size-cells = <0>;
32
33 cpu0: cpu@100 {
34 device_type = "cpu";
35 compatible = "arm,cortex-a53", "arm,armv8";
36 enable-method = "psci";
37 reg = <0x100>;
38 clock-frequency = <1300000000>;
39 clocks = <&cmu_apollo CLK_SCLK_APOLLO>;
40 clock-names = "apolloclk";
41 operating-points-v2 = <&cluster_a53_opp_table>;
42 #cooling-cells = <2>;
43 };
44
45 cpu1: cpu@101 {
46 device_type = "cpu";
47 compatible = "arm,cortex-a53", "arm,armv8";
48 enable-method = "psci";
49 reg = <0x101>;
50 clock-frequency = <1300000000>;
51 operating-points-v2 = <&cluster_a53_opp_table>;
52 #cooling-cells = <2>;
53 };
54
55 cpu2: cpu@102 {
56 device_type = "cpu";
57 compatible = "arm,cortex-a53", "arm,armv8";
58 enable-method = "psci";
59 reg = <0x102>;
60 clock-frequency = <1300000000>;
61 operating-points-v2 = <&cluster_a53_opp_table>;
62 #cooling-cells = <2>;
63 };
64
65 cpu3: cpu@103 {
66 device_type = "cpu";
67 compatible = "arm,cortex-a53", "arm,armv8";
68 enable-method = "psci";
69 reg = <0x103>;
70 clock-frequency = <1300000000>;
71 operating-points-v2 = <&cluster_a53_opp_table>;
72 #cooling-cells = <2>;
73 };
74
75 cpu4: cpu@0 {
76 device_type = "cpu";
77 compatible = "arm,cortex-a57", "arm,armv8";
78 enable-method = "psci";
79 reg = <0x0>;
80 clock-frequency = <1900000000>;
81 clocks = <&cmu_atlas CLK_SCLK_ATLAS>;
82 clock-names = "atlasclk";
83 operating-points-v2 = <&cluster_a57_opp_table>;
84 #cooling-cells = <2>;
85 };
86
87 cpu5: cpu@1 {
88 device_type = "cpu";
89 compatible = "arm,cortex-a57", "arm,armv8";
90 enable-method = "psci";
91 reg = <0x1>;
92 clock-frequency = <1900000000>;
93 operating-points-v2 = <&cluster_a57_opp_table>;
94 #cooling-cells = <2>;
95 };
96
97 cpu6: cpu@2 {
98 device_type = "cpu";
99 compatible = "arm,cortex-a57", "arm,armv8";
100 enable-method = "psci";
101 reg = <0x2>;
102 clock-frequency = <1900000000>;
103 operating-points-v2 = <&cluster_a57_opp_table>;
104 #cooling-cells = <2>;
105 };
106
107 cpu7: cpu@3 {
108 device_type = "cpu";
109 compatible = "arm,cortex-a57", "arm,armv8";
110 enable-method = "psci";
111 reg = <0x3>;
112 clock-frequency = <1900000000>;
113 operating-points-v2 = <&cluster_a57_opp_table>;
114 #cooling-cells = <2>;
115 };
116 };
117
118 cluster_a53_opp_table: opp_table0 {
119 compatible = "operating-points-v2";
120 opp-shared;
121
122 opp@400000000 {
123 opp-hz = /bits/ 64 <400000000>;
124 opp-microvolt = <900000>;
125 };
126 opp@500000000 {
127 opp-hz = /bits/ 64 <500000000>;
128 opp-microvolt = <925000>;
129 };
130 opp@600000000 {
131 opp-hz = /bits/ 64 <600000000>;
132 opp-microvolt = <950000>;
133 };
134 opp@700000000 {
135 opp-hz = /bits/ 64 <700000000>;
136 opp-microvolt = <975000>;
137 };
138 opp@800000000 {
139 opp-hz = /bits/ 64 <800000000>;
140 opp-microvolt = <1000000>;
141 };
142 opp@900000000 {
143 opp-hz = /bits/ 64 <900000000>;
144 opp-microvolt = <1050000>;
145 };
146 opp@1000000000 {
147 opp-hz = /bits/ 64 <1000000000>;
148 opp-microvolt = <1075000>;
149 };
150 opp@1100000000 {
151 opp-hz = /bits/ 64 <1100000000>;
152 opp-microvolt = <1112500>;
153 };
154 opp@1200000000 {
155 opp-hz = /bits/ 64 <1200000000>;
156 opp-microvolt = <1112500>;
157 };
158 opp@1300000000 {
159 opp-hz = /bits/ 64 <1300000000>;
160 opp-microvolt = <1150000>;
161 };
162 };
163
164 cluster_a57_opp_table: opp_table1 {
165 compatible = "operating-points-v2";
166 opp-shared;
167
168 opp@500000000 {
169 opp-hz = /bits/ 64 <500000000>;
170 opp-microvolt = <900000>;
171 };
172 opp@600000000 {
173 opp-hz = /bits/ 64 <600000000>;
174 opp-microvolt = <900000>;
175 };
176 opp@700000000 {
177 opp-hz = /bits/ 64 <700000000>;
178 opp-microvolt = <912500>;
179 };
180 opp@800000000 {
181 opp-hz = /bits/ 64 <800000000>;
182 opp-microvolt = <912500>;
183 };
184 opp@900000000 {
185 opp-hz = /bits/ 64 <900000000>;
186 opp-microvolt = <937500>;
187 };
188 opp@1000000000 {
189 opp-hz = /bits/ 64 <1000000000>;
190 opp-microvolt = <975000>;
191 };
192 opp@1100000000 {
193 opp-hz = /bits/ 64 <1100000000>;
194 opp-microvolt = <1012500>;
195 };
196 opp@1200000000 {
197 opp-hz = /bits/ 64 <1200000000>;
198 opp-microvolt = <1037500>;
199 };
200 opp@1300000000 {
201 opp-hz = /bits/ 64 <1300000000>;
202 opp-microvolt = <1062500>;
203 };
204 opp@1400000000 {
205 opp-hz = /bits/ 64 <1400000000>;
206 opp-microvolt = <1087500>;
207 };
208 opp@1500000000 {
209 opp-hz = /bits/ 64 <1500000000>;
210 opp-microvolt = <1125000>;
211 };
212 opp@1600000000 {
213 opp-hz = /bits/ 64 <1600000000>;
214 opp-microvolt = <1137500>;
215 };
216 opp@1700000000 {
217 opp-hz = /bits/ 64 <1700000000>;
218 opp-microvolt = <1175000>;
219 };
220 opp@1800000000 {
221 opp-hz = /bits/ 64 <1800000000>;
222 opp-microvolt = <1212500>;
223 };
224 opp@1900000000 {
225 opp-hz = /bits/ 64 <1900000000>;
226 opp-microvolt = <1262500>;
227 };
228 };
229
230 psci {
231 compatible = "arm,psci";
232 method = "smc";
233 cpu_off = <0x84000002>;
234 cpu_on = <0xC4000003>;
235 };
236
237 reboot: syscon-reboot {
238 compatible = "syscon-reboot";
239 regmap = <&pmu_system_controller>;
240 offset = <0x400>; /* SWRESET */
241 mask = <0x1>;
242 };
243
244 soc: soc {
245 compatible = "simple-bus";
246 #address-cells = <1>;
247 #size-cells = <1>;
248 ranges = <0x0 0x0 0x0 0x18000000>;
249
250 chipid@10000000 {
251 compatible = "samsung,exynos4210-chipid";
252 reg = <0x10000000 0x100>;
253 };
254
255 xxti: xxti {
256 compatible = "fixed-clock";
257 clock-output-names = "oscclk";
258 #clock-cells = <0>;
259 };
260
261 cmu_top: clock-controller@10030000 {
262 compatible = "samsung,exynos5433-cmu-top";
263 reg = <0x10030000 0x1000>;
264 #clock-cells = <1>;
265
266 clock-names = "oscclk",
267 "sclk_mphy_pll",
268 "sclk_mfc_pll",
269 "sclk_bus_pll";
270 clocks = <&xxti>,
271 <&cmu_cpif CLK_SCLK_MPHY_PLL>,
272 <&cmu_mif CLK_SCLK_MFC_PLL>,
273 <&cmu_mif CLK_SCLK_BUS_PLL>;
274 };
275
276 cmu_cpif: clock-controller@10fc0000 {
277 compatible = "samsung,exynos5433-cmu-cpif";
278 reg = <0x10fc0000 0x1000>;
279 #clock-cells = <1>;
280
281 clock-names = "oscclk";
282 clocks = <&xxti>;
283 };
284
285 cmu_mif: clock-controller@105b0000 {
286 compatible = "samsung,exynos5433-cmu-mif";
287 reg = <0x105b0000 0x2000>;
288 #clock-cells = <1>;
289
290 clock-names = "oscclk",
291 "sclk_mphy_pll";
292 clocks = <&xxti>,
293 <&cmu_cpif CLK_SCLK_MPHY_PLL>;
294 };
295
296 cmu_peric: clock-controller@14c80000 {
297 compatible = "samsung,exynos5433-cmu-peric";
298 reg = <0x14c80000 0x1000>;
299 #clock-cells = <1>;
300 };
301
302 cmu_peris: clock-controller@0x10040000 {
303 compatible = "samsung,exynos5433-cmu-peris";
304 reg = <0x10040000 0x1000>;
305 #clock-cells = <1>;
306 };
307
308 cmu_fsys: clock-controller@156e0000 {
309 compatible = "samsung,exynos5433-cmu-fsys";
310 reg = <0x156e0000 0x1000>;
311 #clock-cells = <1>;
312
313 clock-names = "oscclk",
314 "sclk_ufs_mphy",
315 "div_aclk_fsys_200",
316 "sclk_pcie_100_fsys",
317 "sclk_ufsunipro_fsys",
318 "sclk_mmc2_fsys",
319 "sclk_mmc1_fsys",
320 "sclk_mmc0_fsys",
321 "sclk_usbhost30_fsys",
322 "sclk_usbdrd30_fsys";
323 clocks = <&xxti>,
324 <&cmu_cpif CLK_SCLK_UFS_MPHY>,
325 <&cmu_top CLK_DIV_ACLK_FSYS_200>,
326 <&cmu_top CLK_SCLK_PCIE_100_FSYS>,
327 <&cmu_top CLK_SCLK_UFSUNIPRO_FSYS>,
328 <&cmu_top CLK_SCLK_MMC2_FSYS>,
329 <&cmu_top CLK_SCLK_MMC1_FSYS>,
330 <&cmu_top CLK_SCLK_MMC0_FSYS>,
331 <&cmu_top CLK_SCLK_USBHOST30_FSYS>,
332 <&cmu_top CLK_SCLK_USBDRD30_FSYS>;
333 };
334
335 cmu_g2d: clock-controller@12460000 {
336 compatible = "samsung,exynos5433-cmu-g2d";
337 reg = <0x12460000 0x1000>;
338 #clock-cells = <1>;
339
340 clock-names = "oscclk",
341 "aclk_g2d_266",
342 "aclk_g2d_400";
343 clocks = <&xxti>,
344 <&cmu_top CLK_ACLK_G2D_266>,
345 <&cmu_top CLK_ACLK_G2D_400>;
346 };
347
348 cmu_disp: clock-controller@13b90000 {
349 compatible = "samsung,exynos5433-cmu-disp";
350 reg = <0x13b90000 0x1000>;
351 #clock-cells = <1>;
352
353 clock-names = "oscclk",
354 "sclk_dsim1_disp",
355 "sclk_dsim0_disp",
356 "sclk_dsd_disp",
357 "sclk_decon_tv_eclk_disp",
358 "sclk_decon_vclk_disp",
359 "sclk_decon_eclk_disp",
360 "sclk_decon_tv_vclk_disp",
361 "aclk_disp_333";
362 clocks = <&xxti>,
363 <&cmu_mif CLK_SCLK_DSIM1_DISP>,
364 <&cmu_mif CLK_SCLK_DSIM0_DISP>,
365 <&cmu_mif CLK_SCLK_DSD_DISP>,
366 <&cmu_mif CLK_SCLK_DECON_TV_ECLK_DISP>,
367 <&cmu_mif CLK_SCLK_DECON_VCLK_DISP>,
368 <&cmu_mif CLK_SCLK_DECON_ECLK_DISP>,
369 <&cmu_mif CLK_SCLK_DECON_TV_VCLK_DISP>,
370 <&cmu_mif CLK_ACLK_DISP_333>;
371 };
372
373 cmu_aud: clock-controller@114c0000 {
374 compatible = "samsung,exynos5433-cmu-aud";
375 reg = <0x114c0000 0x1000>;
376 #clock-cells = <1>;
377 };
378
379 cmu_bus0: clock-controller@13600000 {
380 compatible = "samsung,exynos5433-cmu-bus0";
381 reg = <0x13600000 0x1000>;
382 #clock-cells = <1>;
383
384 clock-names = "aclk_bus0_400";
385 clocks = <&cmu_top CLK_ACLK_BUS0_400>;
386 };
387
388 cmu_bus1: clock-controller@14800000 {
389 compatible = "samsung,exynos5433-cmu-bus1";
390 reg = <0x14800000 0x1000>;
391 #clock-cells = <1>;
392
393 clock-names = "aclk_bus1_400";
394 clocks = <&cmu_top CLK_ACLK_BUS1_400>;
395 };
396
397 cmu_bus2: clock-controller@13400000 {
398 compatible = "samsung,exynos5433-cmu-bus2";
399 reg = <0x13400000 0x1000>;
400 #clock-cells = <1>;
401
402 clock-names = "oscclk", "aclk_bus2_400";
403 clocks = <&xxti>, <&cmu_mif CLK_ACLK_BUS2_400>;
404 };
405
406 cmu_g3d: clock-controller@14aa0000 {
407 compatible = "samsung,exynos5433-cmu-g3d";
408 reg = <0x14aa0000 0x2000>;
409 #clock-cells = <1>;
410
411 clock-names = "oscclk", "aclk_g3d_400";
412 clocks = <&xxti>, <&cmu_top CLK_ACLK_G3D_400>;
413 };
414
415 cmu_gscl: clock-controller@13cf0000 {
416 compatible = "samsung,exynos5433-cmu-gscl";
417 reg = <0x13cf0000 0x1000>;
418 #clock-cells = <1>;
419
420 clock-names = "oscclk",
421 "aclk_gscl_111",
422 "aclk_gscl_333";
423 clocks = <&xxti>,
424 <&cmu_top CLK_ACLK_GSCL_111>,
425 <&cmu_top CLK_ACLK_GSCL_333>;
426 };
427
428 cmu_apollo: clock-controller@11900000 {
429 compatible = "samsung,exynos5433-cmu-apollo";
430 reg = <0x11900000 0x2000>;
431 #clock-cells = <1>;
432
433 clock-names = "oscclk", "sclk_bus_pll_apollo";
434 clocks = <&xxti>, <&cmu_mif CLK_SCLK_BUS_PLL_APOLLO>;
435 };
436
437 cmu_atlas: clock-controller@11800000 {
438 compatible = "samsung,exynos5433-cmu-atlas";
439 reg = <0x11800000 0x2000>;
440 #clock-cells = <1>;
441
442 clock-names = "oscclk", "sclk_bus_pll_atlas";
443 clocks = <&xxti>, <&cmu_mif CLK_SCLK_BUS_PLL_ATLAS>;
444 };
445
446 cmu_mscl: clock-controller@105d0000 {
447 compatible = "samsung,exynos5433-cmu-mscl";
448 reg = <0x150d0000 0x1000>;
449 #clock-cells = <1>;
450
451 clock-names = "oscclk",
452 "sclk_jpeg_mscl",
453 "aclk_mscl_400";
454 clocks = <&xxti>,
455 <&cmu_top CLK_SCLK_JPEG_MSCL>,
456 <&cmu_top CLK_ACLK_MSCL_400>;
457 };
458
459 cmu_mfc: clock-controller@15280000 {
460 compatible = "samsung,exynos5433-cmu-mfc";
461 reg = <0x15280000 0x1000>;
462 #clock-cells = <1>;
463
464 clock-names = "oscclk", "aclk_mfc_400";
465 clocks = <&xxti>, <&cmu_top CLK_ACLK_MFC_400>;
466 };
467
468 cmu_hevc: clock-controller@14f80000 {
469 compatible = "samsung,exynos5433-cmu-hevc";
470 reg = <0x14f80000 0x1000>;
471 #clock-cells = <1>;
472
473 clock-names = "oscclk", "aclk_hevc_400";
474 clocks = <&xxti>, <&cmu_top CLK_ACLK_HEVC_400>;
475 };
476
477 cmu_isp: clock-controller@146d0000 {
478 compatible = "samsung,exynos5433-cmu-isp";
479 reg = <0x146d0000 0x1000>;
480 #clock-cells = <1>;
481
482 clock-names = "oscclk",
483 "aclk_isp_dis_400",
484 "aclk_isp_400";
485 clocks = <&xxti>,
486 <&cmu_top CLK_ACLK_ISP_DIS_400>,
487 <&cmu_top CLK_ACLK_ISP_400>;
488 };
489
490 cmu_cam0: clock-controller@120d0000 {
491 compatible = "samsung,exynos5433-cmu-cam0";
492 reg = <0x120d0000 0x1000>;
493 #clock-cells = <1>;
494
495 clock-names = "oscclk",
496 "aclk_cam0_333",
497 "aclk_cam0_400",
498 "aclk_cam0_552";
499 clocks = <&xxti>,
500 <&cmu_top CLK_ACLK_CAM0_333>,
501 <&cmu_top CLK_ACLK_CAM0_400>,
502 <&cmu_top CLK_ACLK_CAM0_552>;
503 };
504
505 cmu_cam1: clock-controller@145d0000 {
506 compatible = "samsung,exynos5433-cmu-cam1";
507 reg = <0x145d0000 0x1000>;
508 #clock-cells = <1>;
509
510 clock-names = "oscclk",
511 "sclk_isp_uart_cam1",
512 "sclk_isp_spi1_cam1",
513 "sclk_isp_spi0_cam1",
514 "aclk_cam1_333",
515 "aclk_cam1_400",
516 "aclk_cam1_552";
517 clocks = <&xxti>,
518 <&cmu_top CLK_SCLK_ISP_UART_CAM1>,
519 <&cmu_top CLK_SCLK_ISP_SPI1_CAM1>,
520 <&cmu_top CLK_SCLK_ISP_SPI0_CAM1>,
521 <&cmu_top CLK_ACLK_CAM1_333>,
522 <&cmu_top CLK_ACLK_CAM1_400>,
523 <&cmu_top CLK_ACLK_CAM1_552>;
524 };
525
526 tmu_atlas0: tmu@10060000 {
527 compatible = "samsung,exynos5433-tmu";
528 reg = <0x10060000 0x200>;
529 interrupts = <GIC_SPI 95 0>;
530 clocks = <&cmu_peris CLK_PCLK_TMU0_APBIF>,
531 <&cmu_peris CLK_SCLK_TMU0>;
532 clock-names = "tmu_apbif", "tmu_sclk";
533 #include "exynos5433-tmu-sensor-conf.dtsi"
534 status = "disabled";
535 };
536
537 tmu_atlas1: tmu@10068000 {
538 compatible = "samsung,exynos5433-tmu";
539 reg = <0x10068000 0x200>;
540 interrupts = <GIC_SPI 96 0>;
541 clocks = <&cmu_peris CLK_PCLK_TMU0_APBIF>,
542 <&cmu_peris CLK_SCLK_TMU0>;
543 clock-names = "tmu_apbif", "tmu_sclk";
544 #include "exynos5433-tmu-sensor-conf.dtsi"
545 status = "disabled";
546 };
547
548 tmu_g3d: tmu@10070000 {
549 compatible = "samsung,exynos5433-tmu";
550 reg = <0x10070000 0x200>;
551 interrupts = <GIC_SPI 99 0>;
552 clocks = <&cmu_peris CLK_PCLK_TMU1_APBIF>,
553 <&cmu_peris CLK_SCLK_TMU1>;
554 clock-names = "tmu_apbif", "tmu_sclk";
555 #include "exynos5433-tmu-g3d-sensor-conf.dtsi"
556 status = "disabled";
557 };
558
559 tmu_apollo: tmu@10078000 {
560 compatible = "samsung,exynos5433-tmu";
561 reg = <0x10078000 0x200>;
562 interrupts = <GIC_SPI 115 0>;
563 clocks = <&cmu_peris CLK_PCLK_TMU1_APBIF>,
564 <&cmu_peris CLK_SCLK_TMU1>;
565 clock-names = "tmu_apbif", "tmu_sclk";
566 #include "exynos5433-tmu-sensor-conf.dtsi"
567 status = "disabled";
568 };
569
570 tmu_isp: tmu@1007c000 {
571 compatible = "samsung,exynos5433-tmu";
572 reg = <0x1007c000 0x200>;
573 interrupts = <GIC_SPI 94 0>;
574 clocks = <&cmu_peris CLK_PCLK_TMU1_APBIF>,
575 <&cmu_peris CLK_SCLK_TMU1>;
576 clock-names = "tmu_apbif", "tmu_sclk";
577 #include "exynos5433-tmu-sensor-conf.dtsi"
578 status = "disabled";
579 };
580
581 mct@101c0000 {
582 compatible = "samsung,exynos4210-mct";
583 reg = <0x101c0000 0x800>;
584 interrupts = <GIC_SPI 102 0>, <GIC_SPI 103 0>,
585 <GIC_SPI 104 0>, <GIC_SPI 105 0>,
586 <GIC_SPI 106 0>, <GIC_SPI 107 0>,
587 <GIC_SPI 108 0>, <GIC_SPI 109 0>,
588 <GIC_SPI 110 0>, <GIC_SPI 111 0>,
589 <GIC_SPI 112 0>, <GIC_SPI 113 0>;
590 clocks = <&xxti>, <&cmu_peris CLK_PCLK_MCT>;
591 clock-names = "fin_pll", "mct";
592 };
593
594 pinctrl_alive: pinctrl@10580000 {
595 compatible = "samsung,exynos5433-pinctrl";
596 reg = <0x10580000 0x1a20>, <0x11090000 0x100>;
597
598 wakeup-interrupt-controller {
599 compatible = "samsung,exynos7-wakeup-eint";
600 interrupts = <GIC_SPI 16 0>;
601 };
602 };
603
604 pinctrl_aud: pinctrl@114b0000 {
605 compatible = "samsung,exynos5433-pinctrl";
606 reg = <0x114b0000 0x1000>;
607 interrupts = <GIC_SPI 68 0>;
608 };
609
610 pinctrl_cpif: pinctrl@10fe0000 {
611 compatible = "samsung,exynos5433-pinctrl";
612 reg = <0x10fe0000 0x1000>;
613 interrupts = <GIC_SPI 179 0>;
614 };
615
616 pinctrl_ese: pinctrl@14ca0000 {
617 compatible = "samsung,exynos5433-pinctrl";
618 reg = <0x14ca0000 0x1000>;
619 interrupts = <GIC_SPI 413 0>;
620 };
621
622 pinctrl_finger: pinctrl@14cb0000 {
623 compatible = "samsung,exynos5433-pinctrl";
624 reg = <0x14cb0000 0x1000>;
625 interrupts = <GIC_SPI 414 0>;
626 };
627
628 pinctrl_fsys: pinctrl@15690000 {
629 compatible = "samsung,exynos5433-pinctrl";
630 reg = <0x15690000 0x1000>;
631 interrupts = <GIC_SPI 229 0>;
632 };
633
634 pinctrl_imem: pinctrl@11090000 {
635 compatible = "samsung,exynos5433-pinctrl";
636 reg = <0x11090000 0x1000>;
637 interrupts = <GIC_SPI 325 0>;
638 };
639
640 pinctrl_nfc: pinctrl@14cd0000 {
641 compatible = "samsung,exynos5433-pinctrl";
642 reg = <0x14cd0000 0x1000>;
643 interrupts = <GIC_SPI 441 0>;
644 };
645
646 pinctrl_peric: pinctrl@14cc0000 {
647 compatible = "samsung,exynos5433-pinctrl";
648 reg = <0x14cc0000 0x1100>;
649 interrupts = <GIC_SPI 440 0>;
650 };
651
652 pinctrl_touch: pinctrl@14ce0000 {
653 compatible = "samsung,exynos5433-pinctrl";
654 reg = <0x14ce0000 0x1100>;
655 interrupts = <GIC_SPI 442 0>;
656 };
657
658 pmu_system_controller: system-controller@105c0000 {
659 compatible = "samsung,exynos5433-pmu", "syscon";
660 reg = <0x105c0000 0x5008>;
661 #clock-cells = <1>;
662 clock-names = "clkout16";
663 clocks = <&xxti>;
664 };
665
666 gic: interrupt-controller@11001000 {
667 compatible = "arm,gic-400";
668 #interrupt-cells = <3>;
669 interrupt-controller;
670 reg = <0x11001000 0x1000>,
671 <0x11002000 0x2000>,
672 <0x11004000 0x2000>,
673 <0x11006000 0x2000>;
674 interrupts = <GIC_PPI 9 0xf04>;
675 };
676
677 mipi_phy: video-phy@105c0710 {
678 compatible = "samsung,exynos5433-mipi-video-phy";
679 #phy-cells = <1>;
680 samsung,pmu-syscon = <&pmu_system_controller>;
681 samsung,cam0-sysreg = <&syscon_cam0>;
682 samsung,cam1-sysreg = <&syscon_cam1>;
683 samsung,disp-sysreg = <&syscon_disp>;
684 };
685
686 decon: decon@13800000 {
687 compatible = "samsung,exynos5433-decon";
688 reg = <0x13800000 0x2104>;
689 clocks = <&cmu_disp CLK_PCLK_DECON>,
690 <&cmu_disp CLK_ACLK_DECON>,
691 <&cmu_disp CLK_ACLK_SMMU_DECON0X>,
692 <&cmu_disp CLK_ACLK_XIU_DECON0X>,
693 <&cmu_disp CLK_PCLK_SMMU_DECON0X>,
694 <&cmu_disp CLK_SCLK_DECON_VCLK>,
695 <&cmu_disp CLK_SCLK_DECON_ECLK>;
696 clock-names = "pclk", "aclk_decon", "aclk_smmu_decon0x",
697 "aclk_xiu_decon0x", "pclk_smmu_decon0x",
698 "sclk_decon_vclk", "sclk_decon_eclk";
699 interrupt-names = "fifo", "vsync", "lcd_sys";
700 interrupts = <GIC_SPI 201 0>, <GIC_SPI 202 0>,
701 <GIC_SPI 203 0>;
702 samsung,disp-sysreg = <&syscon_disp>;
703 status = "disabled";
704 iommus = <&sysmmu_decon0x>, <&sysmmu_decon1x>;
705 iommu-names = "m0", "m1";
706
707 ports {
708 #address-cells = <1>;
709 #size-cells = <0>;
710
711 port@0 {
712 reg = <0>;
713 decon_to_mic: endpoint {
714 remote-endpoint =
715 <&mic_to_decon>;
716 };
717 };
718 };
719 };
720
721 dsi: dsi@13900000 {
722 compatible = "samsung,exynos5433-mipi-dsi";
723 reg = <0x13900000 0xC0>;
724 interrupts = <GIC_SPI 205 0>;
725 phys = <&mipi_phy 1>;
726 phy-names = "dsim";
727 clocks = <&cmu_disp CLK_PCLK_DSIM0>,
728 <&cmu_disp CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8>,
729 <&cmu_disp CLK_PHYCLK_MIPIDPHY0_RXCLKESC0>,
730 <&cmu_disp CLK_SCLK_RGB_VCLK_TO_DSIM0>,
731 <&cmu_disp CLK_SCLK_DSIM0>;
732 clock-names = "bus_clk",
733 "phyclk_mipidphy0_bitclkdiv8",
734 "phyclk_mipidphy0_rxclkesc0",
735 "sclk_rgb_vclk_to_dsim0",
736 "sclk_mipi";
737 status = "disabled";
738 #address-cells = <1>;
739 #size-cells = <0>;
740
741 ports {
742 #address-cells = <1>;
743 #size-cells = <0>;
744
745 port@0 {
746 reg = <0>;
747 dsi_to_mic: endpoint {
748 remote-endpoint = <&mic_to_dsi>;
749 };
750 };
751 };
752 };
753
754 mic: mic@13930000 {
755 compatible = "samsung,exynos5433-mic";
756 reg = <0x13930000 0x48>;
757 clocks = <&cmu_disp CLK_PCLK_MIC0>,
758 <&cmu_disp CLK_SCLK_RGB_VCLK_TO_MIC0>;
759 clock-names = "pclk_mic0", "sclk_rgb_vclk_to_mic0";
760 samsung,disp-syscon = <&syscon_disp>;
761 status = "disabled";
762
763 ports {
764 #address-cells = <1>;
765 #size-cells = <0>;
766
767 port@0 {
768 reg = <0>;
769 mic_to_decon: endpoint {
770 remote-endpoint =
771 <&decon_to_mic>;
772 };
773 };
774
775 port@1 {
776 reg = <1>;
777 mic_to_dsi: endpoint {
778 remote-endpoint = <&dsi_to_mic>;
779 };
780 };
781 };
782 };
783
784 syscon_disp: syscon@13b80000 {
785 compatible = "syscon";
786 reg = <0x13b80000 0x1010>;
787 };
788
789 syscon_cam0: syscon@120f0000 {
790 compatible = "syscon";
791 reg = <0x120f0000 0x1020>;
792 };
793
794 syscon_cam1: syscon@145f0000 {
795 compatible = "syscon";
796 reg = <0x145f0000 0x1038>;
797 };
798
799 sysmmu_decon0x: sysmmu@0x13a00000 {
800 compatible = "samsung,exynos-sysmmu";
801 reg = <0x13a00000 0x1000>;
802 interrupts = <GIC_SPI 192 0>;
803 clock-names = "pclk", "aclk";
804 clocks = <&cmu_disp CLK_PCLK_SMMU_DECON0X>,
805 <&cmu_disp CLK_ACLK_SMMU_DECON0X>;
806 #iommu-cells = <0>;
807 };
808
809 sysmmu_decon1x: sysmmu@0x13a10000 {
810 compatible = "samsung,exynos-sysmmu";
811 reg = <0x13a10000 0x1000>;
812 interrupts = <GIC_SPI 194 0>;
813 clock-names = "pclk", "aclk";
814 clocks = <&cmu_disp CLK_PCLK_SMMU_DECON1X>,
815 <&cmu_disp CLK_ACLK_SMMU_DECON1X>;
816 #iommu-cells = <0>;
817 };
818
819 serial_0: serial@14c10000 {
820 compatible = "samsung,exynos5433-uart";
821 reg = <0x14c10000 0x100>;
822 interrupts = <GIC_SPI 421 0>;
823 clocks = <&cmu_peric CLK_PCLK_UART0>,
824 <&cmu_peric CLK_SCLK_UART0>;
825 clock-names = "uart", "clk_uart_baud0";
826 pinctrl-names = "default";
827 pinctrl-0 = <&uart0_bus>;
828 status = "disabled";
829 };
830
831 serial_1: serial@14c20000 {
832 compatible = "samsung,exynos5433-uart";
833 reg = <0x14c20000 0x100>;
834 interrupts = <GIC_SPI 422 0>;
835 clocks = <&cmu_peric CLK_PCLK_UART1>,
836 <&cmu_peric CLK_SCLK_UART1>;
837 clock-names = "uart", "clk_uart_baud0";
838 pinctrl-names = "default";
839 pinctrl-0 = <&uart1_bus>;
840 status = "disabled";
841 };
842
843 serial_2: serial@14c30000 {
844 compatible = "samsung,exynos5433-uart";
845 reg = <0x14c30000 0x100>;
846 interrupts = <GIC_SPI 423 0>;
847 clocks = <&cmu_peric CLK_PCLK_UART2>,
848 <&cmu_peric CLK_SCLK_UART2>;
849 clock-names = "uart", "clk_uart_baud0";
850 pinctrl-names = "default";
851 pinctrl-0 = <&uart2_bus>;
852 status = "disabled";
853 };
854
855 spi_0: spi@14d20000 {
856 compatible = "samsung,exynos5433-spi";
857 reg = <0x14d20000 0x100>;
858 interrupts = <GIC_SPI 432 0>;
859 dmas = <&pdma0 9>, <&pdma0 8>;
860 dma-names = "tx", "rx";
861 #address-cells = <1>;
862 #size-cells = <0>;
863 clocks = <&cmu_peric CLK_PCLK_SPI0>,
864 <&cmu_peric CLK_SCLK_SPI0>,
865 <&cmu_peric CLK_SCLK_IOCLK_SPI0>;
866 clock-names = "spi", "spi_busclk0", "spi_ioclk";
867 samsung,spi-src-clk = <0>;
868 pinctrl-names = "default";
869 pinctrl-0 = <&spi0_bus>;
870 num-cs = <1>;
871 status = "disabled";
872 };
873
874 spi_1: spi@14d30000 {
875 compatible = "samsung,exynos5433-spi";
876 reg = <0x14d30000 0x100>;
877 interrupts = <GIC_SPI 433 0>;
878 dmas = <&pdma0 11>, <&pdma0 10>;
879 dma-names = "tx", "rx";
880 #address-cells = <1>;
881 #size-cells = <0>;
882 clocks = <&cmu_peric CLK_PCLK_SPI1>,
883 <&cmu_peric CLK_SCLK_SPI1>,
884 <&cmu_peric CLK_SCLK_IOCLK_SPI1>;
885 clock-names = "spi", "spi_busclk0", "spi_ioclk";
886 samsung,spi-src-clk = <0>;
887 pinctrl-names = "default";
888 pinctrl-0 = <&spi1_bus>;
889 num-cs = <1>;
890 status = "disabled";
891 };
892
893 spi_2: spi@14d40000 {
894 compatible = "samsung,exynos5433-spi";
895 reg = <0x14d40000 0x100>;
896 interrupts = <GIC_SPI 434 0>;
897 dmas = <&pdma0 13>, <&pdma0 12>;
898 dma-names = "tx", "rx";
899 #address-cells = <1>;
900 #size-cells = <0>;
901 clocks = <&cmu_peric CLK_PCLK_SPI2>,
902 <&cmu_peric CLK_SCLK_SPI2>,
903 <&cmu_peric CLK_SCLK_IOCLK_SPI2>;
904 clock-names = "spi", "spi_busclk0", "spi_ioclk";
905 samsung,spi-src-clk = <0>;
906 pinctrl-names = "default";
907 pinctrl-0 = <&spi2_bus>;
908 num-cs = <1>;
909 status = "disabled";
910 };
911
912 spi_3: spi@14d50000 {
913 compatible = "samsung,exynos5433-spi";
914 reg = <0x14d50000 0x100>;
915 interrupts = <GIC_SPI 447 0>;
916 dmas = <&pdma0 23>, <&pdma0 22>;
917 dma-names = "tx", "rx";
918 #address-cells = <1>;
919 #size-cells = <0>;
920 clocks = <&cmu_peric CLK_PCLK_SPI3>,
921 <&cmu_peric CLK_SCLK_SPI3>,
922 <&cmu_peric CLK_SCLK_IOCLK_SPI3>;
923 clock-names = "spi", "spi_busclk0", "spi_ioclk";
924 samsung,spi-src-clk = <0>;
925 pinctrl-names = "default";
926 pinctrl-0 = <&spi3_bus>;
927 num-cs = <1>;
928 status = "disabled";
929 };
930
931 spi_4: spi@14d00000 {
932 compatible = "samsung,exynos5433-spi";
933 reg = <0x14d00000 0x100>;
934 interrupts = <GIC_SPI 412 0>;
935 dmas = <&pdma0 25>, <&pdma0 24>;
936 dma-names = "tx", "rx";
937 #address-cells = <1>;
938 #size-cells = <0>;
939 clocks = <&cmu_peric CLK_PCLK_SPI4>,
940 <&cmu_peric CLK_SCLK_SPI4>,
941 <&cmu_peric CLK_SCLK_IOCLK_SPI4>;
942 clock-names = "spi", "spi_busclk0", "spi_ioclk";
943 samsung,spi-src-clk = <0>;
944 pinctrl-names = "default";
945 pinctrl-0 = <&spi4_bus>;
946 num-cs = <1>;
947 status = "disabled";
948 };
949
950 adc: adc@14d10000 {
951 compatible = "samsung,exynos7-adc";
952 reg = <0x14d10000 0x100>;
953 interrupts = <GIC_SPI 438 0>;
954 clock-names = "adc";
955 clocks = <&cmu_peric CLK_PCLK_ADCIF>;
956 #io-channel-cells = <1>;
957 io-channel-ranges;
958 status = "disabled";
959 };
960
961 pwm: pwm@14dd0000 {
962 compatible = "samsung,exynos4210-pwm";
963 reg = <0x14dd0000 0x100>;
964 interrupts = <GIC_SPI 416 0>, <GIC_SPI 417 0>,
965 <GIC_SPI 418 0>, <GIC_SPI 419 0>,
966 <GIC_SPI 420 0>;
967 samsung,pwm-outputs = <0>, <1>, <2>, <3>;
968 clocks = <&cmu_peric CLK_PCLK_PWM>;
969 clock-names = "timers";
970 #pwm-cells = <3>;
971 status = "disabled";
972 };
973
974 hsi2c_0: hsi2c@14e40000 {
975 compatible = "samsung,exynos7-hsi2c";
976 reg = <0x14e40000 0x1000>;
977 interrupts = <GIC_SPI 428 0>;
978 #address-cells = <1>;
979 #size-cells = <0>;
980 pinctrl-names = "default";
981 pinctrl-0 = <&hs_i2c0_bus>;
982 clocks = <&cmu_peric CLK_PCLK_HSI2C0>;
983 clock-names = "hsi2c";
984 status = "disabled";
985 };
986
987 hsi2c_1: hsi2c@14e50000 {
988 compatible = "samsung,exynos7-hsi2c";
989 reg = <0x14e50000 0x1000>;
990 interrupts = <GIC_SPI 429 0>;
991 #address-cells = <1>;
992 #size-cells = <0>;
993 pinctrl-names = "default";
994 pinctrl-0 = <&hs_i2c1_bus>;
995 clocks = <&cmu_peric CLK_PCLK_HSI2C1>;
996 clock-names = "hsi2c";
997 status = "disabled";
998 };
999
1000 hsi2c_2: hsi2c@14e60000 {
1001 compatible = "samsung,exynos7-hsi2c";
1002 reg = <0x14e60000 0x1000>;
1003 interrupts = <GIC_SPI 430 0>;
1004 #address-cells = <1>;
1005 #size-cells = <0>;
1006 pinctrl-names = "default";
1007 pinctrl-0 = <&hs_i2c2_bus>;
1008 clocks = <&cmu_peric CLK_PCLK_HSI2C2>;
1009 clock-names = "hsi2c";
1010 status = "disabled";
1011 };
1012
1013 hsi2c_3: hsi2c@14e70000 {
1014 compatible = "samsung,exynos7-hsi2c";
1015 reg = <0x14e70000 0x1000>;
1016 interrupts = <GIC_SPI 431 0>;
1017 #address-cells = <1>;
1018 #size-cells = <0>;
1019 pinctrl-names = "default";
1020 pinctrl-0 = <&hs_i2c3_bus>;
1021 clocks = <&cmu_peric CLK_PCLK_HSI2C3>;
1022 clock-names = "hsi2c";
1023 status = "disabled";
1024 };
1025
1026 hsi2c_4: hsi2c@14ec0000 {
1027 compatible = "samsung,exynos7-hsi2c";
1028 reg = <0x14ec0000 0x1000>;
1029 interrupts = <GIC_SPI 424 0>;
1030 #address-cells = <1>;
1031 #size-cells = <0>;
1032 pinctrl-names = "default";
1033 pinctrl-0 = <&hs_i2c4_bus>;
1034 clocks = <&cmu_peric CLK_PCLK_HSI2C4>;
1035 clock-names = "hsi2c";
1036 status = "disabled";
1037 };
1038
1039 hsi2c_5: hsi2c@14ed0000 {
1040 compatible = "samsung,exynos7-hsi2c";
1041 reg = <0x14ed0000 0x1000>;
1042 interrupts = <GIC_SPI 425 0>;
1043 #address-cells = <1>;
1044 #size-cells = <0>;
1045 pinctrl-names = "default";
1046 pinctrl-0 = <&hs_i2c5_bus>;
1047 clocks = <&cmu_peric CLK_PCLK_HSI2C5>;
1048 clock-names = "hsi2c";
1049 status = "disabled";
1050 };
1051
1052 hsi2c_6: hsi2c@14ee0000 {
1053 compatible = "samsung,exynos7-hsi2c";
1054 reg = <0x14ee0000 0x1000>;
1055 interrupts = <GIC_SPI 426 0>;
1056 #address-cells = <1>;
1057 #size-cells = <0>;
1058 pinctrl-names = "default";
1059 pinctrl-0 = <&hs_i2c6_bus>;
1060 clocks = <&cmu_peric CLK_PCLK_HSI2C6>;
1061 clock-names = "hsi2c";
1062 status = "disabled";
1063 };
1064
1065 hsi2c_7: hsi2c@14ef0000 {
1066 compatible = "samsung,exynos7-hsi2c";
1067 reg = <0x14ef0000 0x1000>;
1068 interrupts = <GIC_SPI 427 0>;
1069 #address-cells = <1>;
1070 #size-cells = <0>;
1071 pinctrl-names = "default";
1072 pinctrl-0 = <&hs_i2c7_bus>;
1073 clocks = <&cmu_peric CLK_PCLK_HSI2C7>;
1074 clock-names = "hsi2c";
1075 status = "disabled";
1076 };
1077
1078 hsi2c_8: hsi2c@14d90000 {
1079 compatible = "samsung,exynos7-hsi2c";
1080 reg = <0x14d90000 0x1000>;
1081 interrupts = <GIC_SPI 443 0>;
1082 #address-cells = <1>;
1083 #size-cells = <0>;
1084 pinctrl-names = "default";
1085 pinctrl-0 = <&hs_i2c8_bus>;
1086 clocks = <&cmu_peric CLK_PCLK_HSI2C8>;
1087 clock-names = "hsi2c";
1088 status = "disabled";
1089 };
1090
1091 hsi2c_9: hsi2c@14da0000 {
1092 compatible = "samsung,exynos7-hsi2c";
1093 reg = <0x14da0000 0x1000>;
1094 interrupts = <GIC_SPI 444 0>;
1095 #address-cells = <1>;
1096 #size-cells = <0>;
1097 pinctrl-names = "default";
1098 pinctrl-0 = <&hs_i2c9_bus>;
1099 clocks = <&cmu_peric CLK_PCLK_HSI2C9>;
1100 clock-names = "hsi2c";
1101 status = "disabled";
1102 };
1103
1104 hsi2c_10: hsi2c@14de0000 {
1105 compatible = "samsung,exynos7-hsi2c";
1106 reg = <0x14de0000 0x1000>;
1107 interrupts = <GIC_SPI 445 0>;
1108 #address-cells = <1>;
1109 #size-cells = <0>;
1110 pinctrl-names = "default";
1111 pinctrl-0 = <&hs_i2c10_bus>;
1112 clocks = <&cmu_peric CLK_PCLK_HSI2C10>;
1113 clock-names = "hsi2c";
1114 status = "disabled";
1115 };
1116
1117 hsi2c_11: hsi2c@14df0000 {
1118 compatible = "samsung,exynos7-hsi2c";
1119 reg = <0x14df0000 0x1000>;
1120 interrupts = <GIC_SPI 446 0>;
1121 #address-cells = <1>;
1122 #size-cells = <0>;
1123 pinctrl-names = "default";
1124 pinctrl-0 = <&hs_i2c11_bus>;
1125 clocks = <&cmu_peric CLK_PCLK_HSI2C11>;
1126 clock-names = "hsi2c";
1127 status = "disabled";
1128 };
1129
1130 usbdrd30: usb@15400000 {
1131 compatible = "samsung,exynos5250-dwusb3";
1132 clocks = <&cmu_fsys CLK_ACLK_USBDRD30>,
1133 <&cmu_fsys CLK_SCLK_USBDRD30>;
1134 clock-names = "usbdrd30", "usbdrd30_susp_clk";
1135 assigned-clocks =
1136 <&cmu_fsys CLK_MOUT_SCLK_USBDRD30_USER>,
1137 <&cmu_top CLK_MOUT_SCLK_USBDRD30>,
1138 <&cmu_top CLK_DIV_SCLK_USBDRD30>;
1139 assigned-clock-parents =
1140 <&cmu_top CLK_SCLK_USBDRD30_FSYS>,
1141 <&cmu_top CLK_MOUT_BUS_PLL_USER>;
1142 assigned-clock-rates = <0>, <0>, <66700000>;
1143 #address-cells = <1>;
1144 #size-cells = <1>;
1145 ranges;
1146 status = "disabled";
1147
1148 dwc3@15400000 {
1149 compatible = "snps,dwc3";
1150 reg = <0x15400000 0x10000>;
1151 interrupts = <GIC_SPI 231 0>;
1152 phys = <&usbdrd30_phy 0>, <&usbdrd30_phy 1>;
1153 phy-names = "usb2-phy", "usb3-phy";
1154 };
1155 };
1156
1157 usbdrd30_phy: phy@15500000 {
1158 compatible = "samsung,exynos5433-usbdrd-phy";
1159 reg = <0x15500000 0x100>;
1160 clocks = <&cmu_fsys CLK_ACLK_USBDRD30>, <&xxti>,
1161 <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK>,
1162 <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK>,
1163 <&cmu_fsys CLK_SCLK_USBDRD30>;
1164 clock-names = "phy", "ref", "phy_utmi", "phy_pipe",
1165 "itp";
1166 assigned-clocks =
1167 <&cmu_fsys CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_USER>,
1168 <&cmu_fsys CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_USER>;
1169 assigned-clock-parents =
1170 <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_PHY>,
1171 <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_PHY>;
1172 #phy-cells = <1>;
1173 samsung,pmu-syscon = <&pmu_system_controller>;
1174 status = "disabled";
1175 };
1176
1177 usbhost30_phy: phy@15580000 {
1178 compatible = "samsung,exynos5433-usbdrd-phy";
1179 reg = <0x15580000 0x100>;
1180 clocks = <&cmu_fsys CLK_ACLK_USBHOST30>, <&xxti>,
1181 <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK>,
1182 <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK>,
1183 <&cmu_fsys CLK_SCLK_USBHOST30>;
1184 clock-names = "phy", "ref", "phy_utmi", "phy_pipe",
1185 "itp";
1186 assigned-clocks =
1187 <&cmu_fsys CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_USER>,
1188 <&cmu_fsys CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_USER>;
1189 assigned-clock-parents =
1190 <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_PHY>,
1191 <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_PHY>;
1192 #phy-cells = <1>;
1193 samsung,pmu-syscon = <&pmu_system_controller>;
1194 status = "disabled";
1195 };
1196
1197 usbhost30: usb@15a00000 {
1198 compatible = "samsung,exynos5250-dwusb3";
1199 clocks = <&cmu_fsys CLK_ACLK_USBHOST30>,
1200 <&cmu_fsys CLK_SCLK_USBHOST30>;
1201 clock-names = "usbdrd30", "usbdrd30_susp_clk";
1202 assigned-clocks =
1203 <&cmu_fsys CLK_MOUT_SCLK_USBHOST30_USER>,
1204 <&cmu_top CLK_MOUT_SCLK_USBHOST30>,
1205 <&cmu_top CLK_DIV_SCLK_USBHOST30>;
1206 assigned-clock-parents =
1207 <&cmu_top CLK_SCLK_USBHOST30_FSYS>,
1208 <&cmu_top CLK_MOUT_BUS_PLL_USER>;
1209 assigned-clock-rates = <0>, <0>, <66700000>;
1210 #address-cells = <1>;
1211 #size-cells = <1>;
1212 ranges;
1213 status = "disabled";
1214
1215 usbdrd_dwc3_0: dwc3@15a00000 {
1216 compatible = "snps,dwc3";
1217 reg = <0x15a00000 0x10000>;
1218 interrupts = <GIC_SPI 244 0>;
1219 phys = <&usbhost30_phy 0>, <&usbhost30_phy 1>;
1220 phy-names = "usb2-phy", "usb3-phy";
1221 };
1222 };
1223
1224 mshc_0: mshc@15540000 {
1225 compatible = "samsung,exynos7-dw-mshc-smu";
1226 interrupts = <GIC_SPI 225 0>;
1227 #address-cells = <1>;
1228 #size-cells = <0>;
1229 reg = <0x15540000 0x2000>;
1230 clocks = <&cmu_fsys CLK_ACLK_MMC0>,
1231 <&cmu_fsys CLK_SCLK_MMC0>;
1232 clock-names = "biu", "ciu";
1233 fifo-depth = <0x40>;
1234 status = "disabled";
1235 };
1236
1237 mshc_1: mshc@15550000 {
1238 compatible = "samsung,exynos7-dw-mshc-smu";
1239 interrupts = <GIC_SPI 226 0>;
1240 #address-cells = <1>;
1241 #size-cells = <0>;
1242 reg = <0x15550000 0x2000>;
1243 clocks = <&cmu_fsys CLK_ACLK_MMC1>,
1244 <&cmu_fsys CLK_SCLK_MMC1>;
1245 clock-names = "biu", "ciu";
1246 fifo-depth = <0x40>;
1247 status = "disabled";
1248 };
1249
1250 mshc_2: mshc@15560000 {
1251 compatible = "samsung,exynos7-dw-mshc-smu";
1252 interrupts = <GIC_SPI 227 0>;
1253 #address-cells = <1>;
1254 #size-cells = <0>;
1255 reg = <0x15560000 0x2000>;
1256 clocks = <&cmu_fsys CLK_ACLK_MMC2>,
1257 <&cmu_fsys CLK_SCLK_MMC2>;
1258 clock-names = "biu", "ciu";
1259 fifo-depth = <0x40>;
1260 status = "disabled";
1261 };
1262
1263 amba {
1264 compatible = "arm,amba-bus";
1265 #address-cells = <1>;
1266 #size-cells = <1>;
1267 ranges;
1268
1269 pdma0: pdma@15610000 {
1270 compatible = "arm,pl330", "arm,primecell";
1271 reg = <0x15610000 0x1000>;
1272 interrupts = <GIC_SPI 228 0>;
1273 clocks = <&cmu_fsys CLK_PDMA0>;
1274 clock-names = "apb_pclk";
1275 #dma-cells = <1>;
1276 #dma-channels = <8>;
1277 #dma-requests = <32>;
1278 };
1279
1280 pdma1: pdma@15600000 {
1281 compatible = "arm,pl330", "arm,primecell";
1282 reg = <0x15600000 0x1000>;
1283 interrupts = <GIC_SPI 246 0>;
1284 clocks = <&cmu_fsys CLK_PDMA1>;
1285 clock-names = "apb_pclk";
1286 #dma-cells = <1>;
1287 #dma-channels = <8>;
1288 #dma-requests = <32>;
1289 };
1290 };
1291
1292 audio-subsystem@11400000 {
1293 compatible = "samsung,exynos5433-lpass";
1294 reg = <0x11400000 0x100>, <0x11500000 0x08>;
1295 samsung,pmu-syscon = <&pmu_system_controller>;
1296 #address-cells = <1>;
1297 #size-cells = <1>;
1298 ranges;
1299
1300 adma: adma@11420000 {
1301 compatible = "arm,pl330", "arm,primecell";
1302 reg = <0x11420000 0x1000>;
1303 interrupts = <GIC_SPI 73 0>;
1304 clocks = <&cmu_aud CLK_ACLK_DMAC>;
1305 clock-names = "apb_pclk";
1306 #dma-cells = <1>;
1307 #dma-channels = <8>;
1308 #dma-requests = <32>;
1309 };
1310
1311 i2s0: i2s0@11440000 {
1312 compatible = "samsung,exynos7-i2s";
1313 reg = <0x11440000 0x100>;
1314 dmas = <&adma 0 &adma 2>;
1315 dma-names = "tx", "rx";
1316 interrupts = <GIC_SPI 70 0>;
1317 #address-cells = <1>;
1318 #size-cells = <0>;
1319 clocks = <&cmu_aud CLK_PCLK_AUD_I2S>,
1320 <&cmu_aud CLK_SCLK_AUD_I2S>,
1321 <&cmu_aud CLK_SCLK_I2S_BCLK>;
1322 clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
1323 pinctrl-names = "default";
1324 pinctrl-0 = <&i2s0_bus>;
1325 status = "disabled";
1326 };
1327
1328 serial_3: serial@11460000 {
1329 compatible = "samsung,exynos5433-uart";
1330 reg = <0x11460000 0x100>;
1331 interrupts = <GIC_SPI 67 0>;
1332 clocks = <&cmu_aud CLK_PCLK_AUD_UART>,
1333 <&cmu_aud CLK_SCLK_AUD_UART>;
1334 clock-names = "uart", "clk_uart_baud0";
1335 pinctrl-names = "default";
1336 pinctrl-0 = <&uart_aud_bus>;
1337 status = "disabled";
1338 };
1339 };
1340 };
1341
1342 timer: timer {
1343 compatible = "arm,armv8-timer";
1344 interrupts = <GIC_PPI 13
1345 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
1346 <GIC_PPI 14
1347 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
1348 <GIC_PPI 11
1349 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
1350 <GIC_PPI 10
1351 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
1352 };
1353};
1354
1355#include "exynos5433-pinctrl.dtsi"
1356#include "exynos5433-tmu.dtsi"
Linux 6.x block layer and io_uring tree(s)