projects / linux-2.6-block.git / blame
| Commit | Line | Data |
|---|---|---|
| 5f04c4cf CC |
1 | /* |
| 2 | * Samsung's Exynos5433 SoC device tree source | |
| 3 | * | |
| 4 | * Copyright (c) 2016 Samsung Electronics Co., Ltd. | |
| 5 | * | |
| 6 | * Samsung's Exynos5433 SoC device nodes are listed in this file. | |
| 7 | * Exynos5433 based board files can include this file and provide | |
| 8 | * values for board specific bindings. | |
| 9 | * | |
| 10 | * Note: This file does not include device nodes for all the controllers in | |
| 11 | * Exynos5433 SoC. As device tree coverage for Exynos5433 increases, | |
| 12 | * additional nodes can be added to this file. | |
| 13 | * | |
| 14 | * This program is free software; you can redistribute it and/or modify | |
| 15 | * it under the terms of the GNU General Public License version 2 as | |
| 16 | * published by the Free Software Foundation. | |
| 17 | */ | |
| 18 | ||
| 19 | #include <dt-bindings/clock/exynos5433.h> | |
| 20 | #include <dt-bindings/interrupt-controller/arm-gic.h> | |
| 21 | ||
| 22 | / { | |
| 23 | compatible = "samsung,exynos5433"; | |
| 24 | #address-cells = <2>; | |
| 25 | #size-cells = <2>; | |
| 26 | ||
| 27 | interrupt-parent = <&gic>; | |
| 28 | ||
| 29 | cpus { | |
| 30 | #address-cells = <1>; | |
| 31 | #size-cells = <0>; | |
| 32 | ||
| 33 | cpu0: cpu@100 { | |
| 34 | device_type = "cpu"; | |
| 35 | compatible = "arm,cortex-a53", "arm,armv8"; | |
| 36 | enable-method = "psci"; | |
| 37 | reg = <0x100>; | |
| 38 | clock-frequency = <1300000000>; | |
| 39 | clocks = <&cmu_apollo CLK_SCLK_APOLLO>; | |
| 40 | clock-names = "apolloclk"; | |
| 41 | operating-points-v2 = <&cluster_a53_opp_table>; | |
| 42 | #cooling-cells = <2>; | |
| 43 | }; | |
| 44 | ||
| 45 | cpu1: cpu@101 { | |
| 46 | device_type = "cpu"; | |
| 47 | compatible = "arm,cortex-a53", "arm,armv8"; | |
| 48 | enable-method = "psci"; | |
| 49 | reg = <0x101>; | |
| 50 | clock-frequency = <1300000000>; | |
| 51 | operating-points-v2 = <&cluster_a53_opp_table>; | |
| 52 | #cooling-cells = <2>; | |
| 53 | }; | |
| 54 | ||
| 55 | cpu2: cpu@102 { | |
| 56 | device_type = "cpu"; | |
| 57 | compatible = "arm,cortex-a53", "arm,armv8"; | |
| 58 | enable-method = "psci"; | |
| 59 | reg = <0x102>; | |
| 60 | clock-frequency = <1300000000>; | |
| 61 | operating-points-v2 = <&cluster_a53_opp_table>; | |
| 62 | #cooling-cells = <2>; | |
| 63 | }; | |
| 64 | ||
| 65 | cpu3: cpu@103 { | |
| 66 | device_type = "cpu"; | |
| 67 | compatible = "arm,cortex-a53", "arm,armv8"; | |
| 68 | enable-method = "psci"; | |
| 69 | reg = <0x103>; | |
| 70 | clock-frequency = <1300000000>; | |
| 71 | operating-points-v2 = <&cluster_a53_opp_table>; | |
| 72 | #cooling-cells = <2>; | |
| 73 | }; | |
| 74 | ||
| 75 | cpu4: cpu@0 { | |
| 76 | device_type = "cpu"; | |
| 77 | compatible = "arm,cortex-a57", "arm,armv8"; | |
| 78 | enable-method = "psci"; | |
| 79 | reg = <0x0>; | |
| 80 | clock-frequency = <1900000000>; | |
| 81 | clocks = <&cmu_atlas CLK_SCLK_ATLAS>; | |
| 82 | clock-names = "atlasclk"; | |
| 83 | operating-points-v2 = <&cluster_a57_opp_table>; | |
| 84 | #cooling-cells = <2>; | |
| 85 | }; | |
| 86 | ||
| 87 | cpu5: cpu@1 { | |
| 88 | device_type = "cpu"; | |
| 89 | compatible = "arm,cortex-a57", "arm,armv8"; | |
| 90 | enable-method = "psci"; | |
| 91 | reg = <0x1>; | |
| 92 | clock-frequency = <1900000000>; | |
| 93 | operating-points-v2 = <&cluster_a57_opp_table>; | |
| 94 | #cooling-cells = <2>; | |
| 95 | }; | |
| 96 | ||
| 97 | cpu6: cpu@2 { | |
| 98 | device_type = "cpu"; | |
| 99 | compatible = "arm,cortex-a57", "arm,armv8"; | |
| 100 | enable-method = "psci"; | |
| 101 | reg = <0x2>; | |
| 102 | clock-frequency = <1900000000>; | |
| 103 | operating-points-v2 = <&cluster_a57_opp_table>; | |
| 104 | #cooling-cells = <2>; | |
| 105 | }; | |
| 106 | ||
| 107 | cpu7: cpu@3 { | |
| 108 | device_type = "cpu"; | |
| 109 | compatible = "arm,cortex-a57", "arm,armv8"; | |
| 110 | enable-method = "psci"; | |
| 111 | reg = <0x3>; | |
| 112 | clock-frequency = <1900000000>; | |
| 113 | operating-points-v2 = <&cluster_a57_opp_table>; | |
| 114 | #cooling-cells = <2>; | |
| 115 | }; | |
| 116 | }; | |
| 117 | ||
| 118 | cluster_a53_opp_table: opp_table0 { | |
| 119 | compatible = "operating-points-v2"; | |
| 120 | opp-shared; | |
| 121 | ||
| 684c581f | 122 | opp-400000000 { |
| 5f04c4cf CC |
123 | opp-hz = /bits/ 64 <400000000>; |
| 124 | opp-microvolt = <900000>; | |
| 125 | }; | |
| 684c581f | 126 | opp-500000000 { |
| 5f04c4cf CC |
127 | opp-hz = /bits/ 64 <500000000>; |
| 128 | opp-microvolt = <925000>; | |
| 129 | }; | |
| 684c581f | 130 | opp-600000000 { |
| 5f04c4cf CC |
131 | opp-hz = /bits/ 64 <600000000>; |
| 132 | opp-microvolt = <950000>; | |
| 133 | }; | |
| 684c581f | 134 | opp-700000000 { |
| 5f04c4cf CC |
135 | opp-hz = /bits/ 64 <700000000>; |
| 136 | opp-microvolt = <975000>; | |
| 137 | }; | |
| 684c581f | 138 | opp-800000000 { |
| 5f04c4cf CC |
139 | opp-hz = /bits/ 64 <800000000>; |
| 140 | opp-microvolt = <1000000>; | |
| 141 | }; | |
| 684c581f | 142 | opp-900000000 { |
| 5f04c4cf CC |
143 | opp-hz = /bits/ 64 <900000000>; |
| 144 | opp-microvolt = <1050000>; | |
| 145 | }; | |
| 684c581f | 146 | opp-1000000000 { |
| 5f04c4cf CC |
147 | opp-hz = /bits/ 64 <1000000000>; |
| 148 | opp-microvolt = <1075000>; | |
| 149 | }; | |
| 684c581f | 150 | opp-1100000000 { |
| 5f04c4cf CC |
151 | opp-hz = /bits/ 64 <1100000000>; |
| 152 | opp-microvolt = <1112500>; | |
| 153 | }; | |
| 684c581f | 154 | opp-1200000000 { |
| 5f04c4cf CC |
155 | opp-hz = /bits/ 64 <1200000000>; |
| 156 | opp-microvolt = <1112500>; | |
| 157 | }; | |
| 684c581f | 158 | opp-1300000000 { |
| 5f04c4cf CC |
159 | opp-hz = /bits/ 64 <1300000000>; |
| 160 | opp-microvolt = <1150000>; | |
| 161 | }; | |
| 162 | }; | |
| 163 | ||
| 164 | cluster_a57_opp_table: opp_table1 { | |
| 165 | compatible = "operating-points-v2"; | |
| 166 | opp-shared; | |
| 167 | ||
| 684c581f | 168 | opp-500000000 { |
| 5f04c4cf CC |
169 | opp-hz = /bits/ 64 <500000000>; |
| 170 | opp-microvolt = <900000>; | |
| 171 | }; | |
| 684c581f | 172 | opp-600000000 { |
| 5f04c4cf CC |
173 | opp-hz = /bits/ 64 <600000000>; |
| 174 | opp-microvolt = <900000>; | |
| 175 | }; | |
| 684c581f | 176 | opp-700000000 { |
| 5f04c4cf CC |
177 | opp-hz = /bits/ 64 <700000000>; |
| 178 | opp-microvolt = <912500>; | |
| 179 | }; | |
| 684c581f | 180 | opp-800000000 { |
| 5f04c4cf CC |
181 | opp-hz = /bits/ 64 <800000000>; |
| 182 | opp-microvolt = <912500>; | |
| 183 | }; | |
| 684c581f | 184 | opp-900000000 { |
| 5f04c4cf CC |
185 | opp-hz = /bits/ 64 <900000000>; |
| 186 | opp-microvolt = <937500>; | |
| 187 | }; | |
| 684c581f | 188 | opp-1000000000 { |
| 5f04c4cf CC |
189 | opp-hz = /bits/ 64 <1000000000>; |
| 190 | opp-microvolt = <975000>; | |
| 191 | }; | |
| 684c581f | 192 | opp-1100000000 { |
| 5f04c4cf CC |
193 | opp-hz = /bits/ 64 <1100000000>; |
| 194 | opp-microvolt = <1012500>; | |
| 195 | }; | |
| 684c581f | 196 | opp-1200000000 { |
| 5f04c4cf CC |
197 | opp-hz = /bits/ 64 <1200000000>; |
| 198 | opp-microvolt = <1037500>; | |
| 199 | }; | |
| 684c581f | 200 | opp-1300000000 { |
| 5f04c4cf CC |
201 | opp-hz = /bits/ 64 <1300000000>; |
| 202 | opp-microvolt = <1062500>; | |
| 203 | }; | |
| 684c581f | 204 | opp-1400000000 { |
| 5f04c4cf CC |
205 | opp-hz = /bits/ 64 <1400000000>; |
| 206 | opp-microvolt = <1087500>; | |
| 207 | }; | |
| 684c581f | 208 | opp-1500000000 { |
| 5f04c4cf CC |
209 | opp-hz = /bits/ 64 <1500000000>; |
| 210 | opp-microvolt = <1125000>; | |
| 211 | }; | |
| 684c581f | 212 | opp-1600000000 { |
| 5f04c4cf CC |
213 | opp-hz = /bits/ 64 <1600000000>; |
| 214 | opp-microvolt = <1137500>; | |
| 215 | }; | |
| 684c581f | 216 | opp-1700000000 { |
| 5f04c4cf CC |
217 | opp-hz = /bits/ 64 <1700000000>; |
| 218 | opp-microvolt = <1175000>; | |
| 219 | }; | |
| 684c581f | 220 | opp-1800000000 { |
| 5f04c4cf CC |
221 | opp-hz = /bits/ 64 <1800000000>; |
| 222 | opp-microvolt = <1212500>; | |
| 223 | }; | |
| 684c581f | 224 | opp-1900000000 { |
| 5f04c4cf CC |
225 | opp-hz = /bits/ 64 <1900000000>; |
| 226 | opp-microvolt = <1262500>; | |
| 227 | }; | |
| 228 | }; | |
| 229 | ||
| 230 | psci { | |
| 231 | compatible = "arm,psci"; | |
| 232 | method = "smc"; | |
| 233 | cpu_off = <0x84000002>; | |
| 234 | cpu_on = <0xC4000003>; | |
| 235 | }; | |
| 236 | ||
| 237 | reboot: syscon-reboot { | |
| 238 | compatible = "syscon-reboot"; | |
| 239 | regmap = <&pmu_system_controller>; | |
| 240 | offset = <0x400>; /* SWRESET */ | |
| 241 | mask = <0x1>; | |
| 242 | }; | |
| 243 | ||
| 244 | soc: soc { | |
| 245 | compatible = "simple-bus"; | |
| 246 | #address-cells = <1>; | |
| 247 | #size-cells = <1>; | |
| 248 | ranges = <0x0 0x0 0x0 0x18000000>; | |
| 249 | ||
| e9cd3444 MS |
250 | arm_a53_pmu { |
| 251 | compatible = "arm,cortex-a53-pmu", "arm,armv8-pmuv3"; | |
| 252 | interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, | |
| 253 | <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, | |
| 254 | <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, | |
| 255 | <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; | |
| 256 | interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; | |
| 257 | }; | |
| 258 | ||
| 259 | arm_a57_pmu { | |
| 260 | compatible = "arm,cortex-a57-pmu", "arm,armv8-pmuv3"; | |
| 261 | interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, | |
| 262 | <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, | |
| 263 | <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, | |
| 264 | <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; | |
| 265 | interrupt-affinity = <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>; | |
| 266 | }; | |
| 267 | ||
| 5f04c4cf CC |
268 | chipid@10000000 { |
| 269 | compatible = "samsung,exynos4210-chipid"; | |
| 270 | reg = <0x10000000 0x100>; | |
| 271 | }; | |
| 272 | ||
| 273 | xxti: xxti { | |
| 274 | compatible = "fixed-clock"; | |
| 275 | clock-output-names = "oscclk"; | |
| 276 | #clock-cells = <0>; | |
| 277 | }; | |
| 278 | ||
| 279 | cmu_top: clock-controller@10030000 { | |
| 280 | compatible = "samsung,exynos5433-cmu-top"; | |
| 281 | reg = <0x10030000 0x1000>; | |
| 282 | #clock-cells = <1>; | |
| 283 | ||
| 284 | clock-names = "oscclk", | |
| 285 | "sclk_mphy_pll", | |
| 286 | "sclk_mfc_pll", | |
| 287 | "sclk_bus_pll"; | |
| 288 | clocks = <&xxti>, | |
| 289 | <&cmu_cpif CLK_SCLK_MPHY_PLL>, | |
| 290 | <&cmu_mif CLK_SCLK_MFC_PLL>, | |
| 291 | <&cmu_mif CLK_SCLK_BUS_PLL>; | |
| 292 | }; | |
| 293 | ||
| 294 | cmu_cpif: clock-controller@10fc0000 { | |
| 295 | compatible = "samsung,exynos5433-cmu-cpif"; | |
| 296 | reg = <0x10fc0000 0x1000>; | |
| 297 | #clock-cells = <1>; | |
| 298 | ||
| 299 | clock-names = "oscclk"; | |
| 300 | clocks = <&xxti>; | |
| 301 | }; | |
| 302 | ||
| 303 | cmu_mif: clock-controller@105b0000 { | |
| 304 | compatible = "samsung,exynos5433-cmu-mif"; | |
| 305 | reg = <0x105b0000 0x2000>; | |
| 306 | #clock-cells = <1>; | |
| 307 | ||
| 308 | clock-names = "oscclk", | |
| 309 | "sclk_mphy_pll"; | |
| 310 | clocks = <&xxti>, | |
| 311 | <&cmu_cpif CLK_SCLK_MPHY_PLL>; | |
| 312 | }; | |
| 313 | ||
| 314 | cmu_peric: clock-controller@14c80000 { | |
| 315 | compatible = "samsung,exynos5433-cmu-peric"; | |
| 316 | reg = <0x14c80000 0x1000>; | |
| 317 | #clock-cells = <1>; | |
| 318 | }; | |
| 319 | ||
| df5d5a93 | 320 | cmu_peris: clock-controller@10040000 { |
| 5f04c4cf CC |
321 | compatible = "samsung,exynos5433-cmu-peris"; |
| 322 | reg = <0x10040000 0x1000>; | |
| 323 | #clock-cells = <1>; | |
| 324 | }; | |
| 325 | ||
| 326 | cmu_fsys: clock-controller@156e0000 { | |
| 327 | compatible = "samsung,exynos5433-cmu-fsys"; | |
| 328 | reg = <0x156e0000 0x1000>; | |
| 329 | #clock-cells = <1>; | |
| 330 | ||
| 331 | clock-names = "oscclk", | |
| 332 | "sclk_ufs_mphy", | |
| e206f85c | 333 | "aclk_fsys_200", |
| 5f04c4cf CC |
334 | "sclk_pcie_100_fsys", |
| 335 | "sclk_ufsunipro_fsys", | |
| 336 | "sclk_mmc2_fsys", | |
| 337 | "sclk_mmc1_fsys", | |
| 338 | "sclk_mmc0_fsys", | |
| 339 | "sclk_usbhost30_fsys", | |
| 340 | "sclk_usbdrd30_fsys"; | |
| 341 | clocks = <&xxti>, | |
| 342 | <&cmu_cpif CLK_SCLK_UFS_MPHY>, | |
| e206f85c | 343 | <&cmu_top CLK_ACLK_FSYS_200>, |
| 5f04c4cf CC |
344 | <&cmu_top CLK_SCLK_PCIE_100_FSYS>, |
| 345 | <&cmu_top CLK_SCLK_UFSUNIPRO_FSYS>, | |
| 346 | <&cmu_top CLK_SCLK_MMC2_FSYS>, | |
| 347 | <&cmu_top CLK_SCLK_MMC1_FSYS>, | |
| 348 | <&cmu_top CLK_SCLK_MMC0_FSYS>, | |
| 349 | <&cmu_top CLK_SCLK_USBHOST30_FSYS>, | |
| 350 | <&cmu_top CLK_SCLK_USBDRD30_FSYS>; | |
| 351 | }; | |
| 352 | ||
| 353 | cmu_g2d: clock-controller@12460000 { | |
| 354 | compatible = "samsung,exynos5433-cmu-g2d"; | |
| 355 | reg = <0x12460000 0x1000>; | |
| 356 | #clock-cells = <1>; | |
| 357 | ||
| 358 | clock-names = "oscclk", | |
| 359 | "aclk_g2d_266", | |
| 360 | "aclk_g2d_400"; | |
| 361 | clocks = <&xxti>, | |
| 362 | <&cmu_top CLK_ACLK_G2D_266>, | |
| 363 | <&cmu_top CLK_ACLK_G2D_400>; | |
| 364 | }; | |
| 365 | ||
| 366 | cmu_disp: clock-controller@13b90000 { | |
| 367 | compatible = "samsung,exynos5433-cmu-disp"; | |
| 368 | reg = <0x13b90000 0x1000>; | |
| 369 | #clock-cells = <1>; | |
| 370 | ||
| 371 | clock-names = "oscclk", | |
| 372 | "sclk_dsim1_disp", | |
| 373 | "sclk_dsim0_disp", | |
| 374 | "sclk_dsd_disp", | |
| 375 | "sclk_decon_tv_eclk_disp", | |
| 376 | "sclk_decon_vclk_disp", | |
| 377 | "sclk_decon_eclk_disp", | |
| 378 | "sclk_decon_tv_vclk_disp", | |
| 379 | "aclk_disp_333"; | |
| 380 | clocks = <&xxti>, | |
| 381 | <&cmu_mif CLK_SCLK_DSIM1_DISP>, | |
| 382 | <&cmu_mif CLK_SCLK_DSIM0_DISP>, | |
| 383 | <&cmu_mif CLK_SCLK_DSD_DISP>, | |
| 384 | <&cmu_mif CLK_SCLK_DECON_TV_ECLK_DISP>, | |
| 385 | <&cmu_mif CLK_SCLK_DECON_VCLK_DISP>, | |
| 386 | <&cmu_mif CLK_SCLK_DECON_ECLK_DISP>, | |
| 387 | <&cmu_mif CLK_SCLK_DECON_TV_VCLK_DISP>, | |
| 388 | <&cmu_mif CLK_ACLK_DISP_333>; | |
| 9715ed87 | 389 | power-domains = <&pd_disp>; |
| 5f04c4cf CC |
390 | }; |
| 391 | ||
| 392 | cmu_aud: clock-controller@114c0000 { | |
| 393 | compatible = "samsung,exynos5433-cmu-aud"; | |
| 394 | reg = <0x114c0000 0x1000>; | |
| 395 | #clock-cells = <1>; | |
| e681376e MS |
396 | clock-names = "oscclk", "fout_aud_pll"; |
| 397 | clocks = <&xxti>, <&cmu_top CLK_FOUT_AUD_PLL>; | |
| 5f04c4cf CC |
398 | }; |
| 399 | ||
| 400 | cmu_bus0: clock-controller@13600000 { | |
| 401 | compatible = "samsung,exynos5433-cmu-bus0"; | |
| 402 | reg = <0x13600000 0x1000>; | |
| 403 | #clock-cells = <1>; | |
| 404 | ||
| 405 | clock-names = "aclk_bus0_400"; | |
| 406 | clocks = <&cmu_top CLK_ACLK_BUS0_400>; | |
| 407 | }; | |
| 408 | ||
| 409 | cmu_bus1: clock-controller@14800000 { | |
| 410 | compatible = "samsung,exynos5433-cmu-bus1"; | |
| 411 | reg = <0x14800000 0x1000>; | |
| 412 | #clock-cells = <1>; | |
| 413 | ||
| 414 | clock-names = "aclk_bus1_400"; | |
| 415 | clocks = <&cmu_top CLK_ACLK_BUS1_400>; | |
| 416 | }; | |
| 417 | ||
| 418 | cmu_bus2: clock-controller@13400000 { | |
| 419 | compatible = "samsung,exynos5433-cmu-bus2"; | |
| 420 | reg = <0x13400000 0x1000>; | |
| 421 | #clock-cells = <1>; | |
| 422 | ||
| 423 | clock-names = "oscclk", "aclk_bus2_400"; | |
| 424 | clocks = <&xxti>, <&cmu_mif CLK_ACLK_BUS2_400>; | |
| 425 | }; | |
| 426 | ||
| 427 | cmu_g3d: clock-controller@14aa0000 { | |
| 428 | compatible = "samsung,exynos5433-cmu-g3d"; | |
| 429 | reg = <0x14aa0000 0x2000>; | |
| 430 | #clock-cells = <1>; | |
| 431 | ||
| 432 | clock-names = "oscclk", "aclk_g3d_400"; | |
| 433 | clocks = <&xxti>, <&cmu_top CLK_ACLK_G3D_400>; | |
| 434 | }; | |
| 435 | ||
| 436 | cmu_gscl: clock-controller@13cf0000 { | |
| 437 | compatible = "samsung,exynos5433-cmu-gscl"; | |
| 438 | reg = <0x13cf0000 0x1000>; | |
| 439 | #clock-cells = <1>; | |
| 440 | ||
| 441 | clock-names = "oscclk", | |
| 442 | "aclk_gscl_111", | |
| 443 | "aclk_gscl_333"; | |
| 444 | clocks = <&xxti>, | |
| 445 | <&cmu_top CLK_ACLK_GSCL_111>, | |
| 446 | <&cmu_top CLK_ACLK_GSCL_333>; | |
| c2607220 | 447 | power-domains = <&pd_gscl>; |
| 5f04c4cf CC |
448 | }; |
| 449 | ||
| 450 | cmu_apollo: clock-controller@11900000 { | |
| 451 | compatible = "samsung,exynos5433-cmu-apollo"; | |
| 452 | reg = <0x11900000 0x2000>; | |
| 453 | #clock-cells = <1>; | |
| 454 | ||
| 455 | clock-names = "oscclk", "sclk_bus_pll_apollo"; | |
| 456 | clocks = <&xxti>, <&cmu_mif CLK_SCLK_BUS_PLL_APOLLO>; | |
| 457 | }; | |
| 458 | ||
| 459 | cmu_atlas: clock-controller@11800000 { | |
| 460 | compatible = "samsung,exynos5433-cmu-atlas"; | |
| 461 | reg = <0x11800000 0x2000>; | |
| 462 | #clock-cells = <1>; | |
| 463 | ||
| 464 | clock-names = "oscclk", "sclk_bus_pll_atlas"; | |
| 465 | clocks = <&xxti>, <&cmu_mif CLK_SCLK_BUS_PLL_ATLAS>; | |
| 466 | }; | |
| 467 | ||
| 468 | cmu_mscl: clock-controller@105d0000 { | |
| 469 | compatible = "samsung,exynos5433-cmu-mscl"; | |
| 470 | reg = <0x150d0000 0x1000>; | |
| 471 | #clock-cells = <1>; | |
| 472 | ||
| 473 | clock-names = "oscclk", | |
| 474 | "sclk_jpeg_mscl", | |
| 475 | "aclk_mscl_400"; | |
| 476 | clocks = <&xxti>, | |
| 477 | <&cmu_top CLK_SCLK_JPEG_MSCL>, | |
| 478 | <&cmu_top CLK_ACLK_MSCL_400>; | |
| e45dda53 | 479 | power-domains = <&pd_mscl>; |
| 5f04c4cf CC |
480 | }; |
| 481 | ||
| 482 | cmu_mfc: clock-controller@15280000 { | |
| 483 | compatible = "samsung,exynos5433-cmu-mfc"; | |
| 484 | reg = <0x15280000 0x1000>; | |
| 485 | #clock-cells = <1>; | |
| 486 | ||
| 487 | clock-names = "oscclk", "aclk_mfc_400"; | |
| 488 | clocks = <&xxti>, <&cmu_top CLK_ACLK_MFC_400>; | |
| c4e7aba6 | 489 | power-domains = <&pd_mfc>; |
| 5f04c4cf CC |
490 | }; |
| 491 | ||
| 492 | cmu_hevc: clock-controller@14f80000 { | |
| 493 | compatible = "samsung,exynos5433-cmu-hevc"; | |
| 494 | reg = <0x14f80000 0x1000>; | |
| 495 | #clock-cells = <1>; | |
| 496 | ||
| 497 | clock-names = "oscclk", "aclk_hevc_400"; | |
| 498 | clocks = <&xxti>, <&cmu_top CLK_ACLK_HEVC_400>; | |
| 499 | }; | |
| 500 | ||
| 501 | cmu_isp: clock-controller@146d0000 { | |
| 502 | compatible = "samsung,exynos5433-cmu-isp"; | |
| 503 | reg = <0x146d0000 0x1000>; | |
| 504 | #clock-cells = <1>; | |
| 505 | ||
| 506 | clock-names = "oscclk", | |
| 507 | "aclk_isp_dis_400", | |
| 508 | "aclk_isp_400"; | |
| 509 | clocks = <&xxti>, | |
| 510 | <&cmu_top CLK_ACLK_ISP_DIS_400>, | |
| 511 | <&cmu_top CLK_ACLK_ISP_400>; | |
| 512 | }; | |
| 513 | ||
| 514 | cmu_cam0: clock-controller@120d0000 { | |
| 515 | compatible = "samsung,exynos5433-cmu-cam0"; | |
| 516 | reg = <0x120d0000 0x1000>; | |
| 517 | #clock-cells = <1>; | |
| 518 | ||
| 519 | clock-names = "oscclk", | |
| 520 | "aclk_cam0_333", | |
| 521 | "aclk_cam0_400", | |
| 522 | "aclk_cam0_552"; | |
| 523 | clocks = <&xxti>, | |
| 524 | <&cmu_top CLK_ACLK_CAM0_333>, | |
| 525 | <&cmu_top CLK_ACLK_CAM0_400>, | |
| 526 | <&cmu_top CLK_ACLK_CAM0_552>; | |
| 527 | }; | |
| 528 | ||
| 529 | cmu_cam1: clock-controller@145d0000 { | |
| 530 | compatible = "samsung,exynos5433-cmu-cam1"; | |
| 531 | reg = <0x145d0000 0x1000>; | |
| 532 | #clock-cells = <1>; | |
| 533 | ||
| 534 | clock-names = "oscclk", | |
| 535 | "sclk_isp_uart_cam1", | |
| 536 | "sclk_isp_spi1_cam1", | |
| 537 | "sclk_isp_spi0_cam1", | |
| 538 | "aclk_cam1_333", | |
| 539 | "aclk_cam1_400", | |
| 540 | "aclk_cam1_552"; | |
| 541 | clocks = <&xxti>, | |
| 542 | <&cmu_top CLK_SCLK_ISP_UART_CAM1>, | |
| 543 | <&cmu_top CLK_SCLK_ISP_SPI1_CAM1>, | |
| 544 | <&cmu_top CLK_SCLK_ISP_SPI0_CAM1>, | |
| 545 | <&cmu_top CLK_ACLK_CAM1_333>, | |
| 546 | <&cmu_top CLK_ACLK_CAM1_400>, | |
| 547 | <&cmu_top CLK_ACLK_CAM1_552>; | |
| 548 | }; | |
| 549 | ||
| c2607220 MS |
550 | pd_gscl: power-domain@105c4000 { |
| 551 | compatible = "samsung,exynos5433-pd"; | |
| 552 | reg = <0x105c4000 0x20>; | |
| 553 | #power-domain-cells = <0>; | |
| 554 | label = "GSCL"; | |
| 555 | }; | |
| 556 | ||
| e45dda53 MS |
557 | pd_mscl: power-domain@105c4040 { |
| 558 | compatible = "samsung,exynos5433-pd"; | |
| 559 | reg = <0x105c4040 0x20>; | |
| 560 | #power-domain-cells = <0>; | |
| 561 | label = "MSCL"; | |
| 562 | }; | |
| 563 | ||
| 9715ed87 MS |
564 | pd_disp: power-domain@105c4080 { |
| 565 | compatible = "samsung,exynos5433-pd"; | |
| 566 | reg = <0x105c4080 0x20>; | |
| 567 | #power-domain-cells = <0>; | |
| 568 | label = "DISP"; | |
| 569 | }; | |
| 570 | ||
| c4e7aba6 MS |
571 | pd_mfc: power-domain@105c4180 { |
| 572 | compatible = "samsung,exynos5433-pd"; | |
| 573 | reg = <0x105c4180 0x20>; | |
| 574 | #power-domain-cells = <0>; | |
| 575 | label = "MFC"; | |
| 576 | }; | |
| 577 | ||
| 5f04c4cf CC |
578 | tmu_atlas0: tmu@10060000 { |
| 579 | compatible = "samsung,exynos5433-tmu"; | |
| 580 | reg = <0x10060000 0x200>; | |
| cebef6be | 581 | interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; |
| 5f04c4cf CC |
582 | clocks = <&cmu_peris CLK_PCLK_TMU0_APBIF>, |
| 583 | <&cmu_peris CLK_SCLK_TMU0>; | |
| 584 | clock-names = "tmu_apbif", "tmu_sclk"; | |
| 585 | #include "exynos5433-tmu-sensor-conf.dtsi" | |
| 586 | status = "disabled"; | |
| 587 | }; | |
| 588 | ||
| 589 | tmu_atlas1: tmu@10068000 { | |
| 590 | compatible = "samsung,exynos5433-tmu"; | |
| 591 | reg = <0x10068000 0x200>; | |
| cebef6be | 592 | interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; |
| 5f04c4cf CC |
593 | clocks = <&cmu_peris CLK_PCLK_TMU0_APBIF>, |
| 594 | <&cmu_peris CLK_SCLK_TMU0>; | |
| 595 | clock-names = "tmu_apbif", "tmu_sclk"; | |
| 596 | #include "exynos5433-tmu-sensor-conf.dtsi" | |
| 597 | status = "disabled"; | |
| 598 | }; | |
| 599 | ||
| 600 | tmu_g3d: tmu@10070000 { | |
| 601 | compatible = "samsung,exynos5433-tmu"; | |
| 602 | reg = <0x10070000 0x200>; | |
| cebef6be | 603 | interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; |
| 5f04c4cf CC |
604 | clocks = <&cmu_peris CLK_PCLK_TMU1_APBIF>, |
| 605 | <&cmu_peris CLK_SCLK_TMU1>; | |
| 606 | clock-names = "tmu_apbif", "tmu_sclk"; | |
| 607 | #include "exynos5433-tmu-g3d-sensor-conf.dtsi" | |
| 608 | status = "disabled"; | |
| 609 | }; | |
| 610 | ||
| 611 | tmu_apollo: tmu@10078000 { | |
| 612 | compatible = "samsung,exynos5433-tmu"; | |
| 613 | reg = <0x10078000 0x200>; | |
| cebef6be | 614 | interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; |
| 5f04c4cf CC |
615 | clocks = <&cmu_peris CLK_PCLK_TMU1_APBIF>, |
| 616 | <&cmu_peris CLK_SCLK_TMU1>; | |
| 617 | clock-names = "tmu_apbif", "tmu_sclk"; | |
| 618 | #include "exynos5433-tmu-sensor-conf.dtsi" | |
| 619 | status = "disabled"; | |
| 620 | }; | |
| 621 | ||
| 622 | tmu_isp: tmu@1007c000 { | |
| 623 | compatible = "samsung,exynos5433-tmu"; | |
| 624 | reg = <0x1007c000 0x200>; | |
| cebef6be | 625 | interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; |
| 5f04c4cf CC |
626 | clocks = <&cmu_peris CLK_PCLK_TMU1_APBIF>, |
| 627 | <&cmu_peris CLK_SCLK_TMU1>; | |
| 628 | clock-names = "tmu_apbif", "tmu_sclk"; | |
| 629 | #include "exynos5433-tmu-sensor-conf.dtsi" | |
| 630 | status = "disabled"; | |
| 631 | }; | |
| 632 | ||
| 633 | mct@101c0000 { | |
| 634 | compatible = "samsung,exynos4210-mct"; | |
| 635 | reg = <0x101c0000 0x800>; | |
| cebef6be MS |
636 | interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, |
| 637 | <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, | |
| 638 | <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, | |
| 639 | <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, | |
| 640 | <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, | |
| 641 | <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, | |
| 642 | <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, | |
| 643 | <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, | |
| 644 | <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, | |
| 645 | <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, | |
| 646 | <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, | |
| 647 | <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; | |
| 5f04c4cf CC |
648 | clocks = <&xxti>, <&cmu_peris CLK_PCLK_MCT>; |
| 649 | clock-names = "fin_pll", "mct"; | |
| 650 | }; | |
| 651 | ||
| 7774f4e2 CC |
652 | ppmu_d0_cpu: ppmu@10480000 { |
| 653 | compatible = "samsung,exynos-ppmu-v2"; | |
| 654 | reg = <0x10480000 0x2000>; | |
| 655 | status = "disabled"; | |
| 656 | }; | |
| 657 | ||
| 658 | ppmu_d0_general: ppmu@10490000 { | |
| 659 | compatible = "samsung,exynos-ppmu-v2"; | |
| 660 | reg = <0x10490000 0x2000>; | |
| 661 | status = "disabled"; | |
| 662 | }; | |
| 663 | ||
| 664 | ppmu_d1_cpu: ppmu@104b0000 { | |
| 665 | compatible = "samsung,exynos-ppmu-v2"; | |
| 666 | reg = <0x104b0000 0x2000>; | |
| 667 | status = "disabled"; | |
| 668 | }; | |
| 669 | ||
| 670 | ppmu_d1_general: ppmu@104c0000 { | |
| 671 | compatible = "samsung,exynos-ppmu-v2"; | |
| 672 | reg = <0x104c0000 0x2000>; | |
| 673 | status = "disabled"; | |
| 674 | }; | |
| 675 | ||
| 5f04c4cf CC |
676 | pinctrl_alive: pinctrl@10580000 { |
| 677 | compatible = "samsung,exynos5433-pinctrl"; | |
| 678 | reg = <0x10580000 0x1a20>, <0x11090000 0x100>; | |
| 679 | ||
| 680 | wakeup-interrupt-controller { | |
| 681 | compatible = "samsung,exynos7-wakeup-eint"; | |
| cebef6be | 682 | interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; |
| 5f04c4cf CC |
683 | }; |
| 684 | }; | |
| 685 | ||
| 686 | pinctrl_aud: pinctrl@114b0000 { | |
| 687 | compatible = "samsung,exynos5433-pinctrl"; | |
| 688 | reg = <0x114b0000 0x1000>; | |
| cebef6be | 689 | interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; |
| 5f04c4cf CC |
690 | }; |
| 691 | ||
| 692 | pinctrl_cpif: pinctrl@10fe0000 { | |
| 693 | compatible = "samsung,exynos5433-pinctrl"; | |
| 694 | reg = <0x10fe0000 0x1000>; | |
| cebef6be | 695 | interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; |
| 5f04c4cf CC |
696 | }; |
| 697 | ||
| 698 | pinctrl_ese: pinctrl@14ca0000 { | |
| 699 | compatible = "samsung,exynos5433-pinctrl"; | |
| 700 | reg = <0x14ca0000 0x1000>; | |
| cebef6be | 701 | interrupts = <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>; |
| 5f04c4cf CC |
702 | }; |
| 703 | ||
| 704 | pinctrl_finger: pinctrl@14cb0000 { | |
| 705 | compatible = "samsung,exynos5433-pinctrl"; | |
| 706 | reg = <0x14cb0000 0x1000>; | |
| cebef6be | 707 | interrupts = <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>; |
| 5f04c4cf CC |
708 | }; |
| 709 | ||
| 710 | pinctrl_fsys: pinctrl@15690000 { | |
| 711 | compatible = "samsung,exynos5433-pinctrl"; | |
| 712 | reg = <0x15690000 0x1000>; | |
| cebef6be | 713 | interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; |
| 5f04c4cf CC |
714 | }; |
| 715 | ||
| 716 | pinctrl_imem: pinctrl@11090000 { | |
| 717 | compatible = "samsung,exynos5433-pinctrl"; | |
| 718 | reg = <0x11090000 0x1000>; | |
| cebef6be | 719 | interrupts = <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>; |
| 5f04c4cf CC |
720 | }; |
| 721 | ||
| 722 | pinctrl_nfc: pinctrl@14cd0000 { | |
| 723 | compatible = "samsung,exynos5433-pinctrl"; | |
| 724 | reg = <0x14cd0000 0x1000>; | |
| cebef6be | 725 | interrupts = <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>; |
| 5f04c4cf CC |
726 | }; |
| 727 | ||
| 728 | pinctrl_peric: pinctrl@14cc0000 { | |
| 729 | compatible = "samsung,exynos5433-pinctrl"; | |
| 730 | reg = <0x14cc0000 0x1100>; | |
| cebef6be | 731 | interrupts = <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>; |
| 5f04c4cf CC |
732 | }; |
| 733 | ||
| 734 | pinctrl_touch: pinctrl@14ce0000 { | |
| 735 | compatible = "samsung,exynos5433-pinctrl"; | |
| 736 | reg = <0x14ce0000 0x1100>; | |
| cebef6be | 737 | interrupts = <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>; |
| 5f04c4cf CC |
738 | }; |
| 739 | ||
| 740 | pmu_system_controller: system-controller@105c0000 { | |
| 741 | compatible = "samsung,exynos5433-pmu", "syscon"; | |
| 742 | reg = <0x105c0000 0x5008>; | |
| 743 | #clock-cells = <1>; | |
| 744 | clock-names = "clkout16"; | |
| 745 | clocks = <&xxti>; | |
| 746 | }; | |
| 747 | ||
| 748 | gic: interrupt-controller@11001000 { | |
| 749 | compatible = "arm,gic-400"; | |
| 750 | #interrupt-cells = <3>; | |
| 751 | interrupt-controller; | |
| 752 | reg = <0x11001000 0x1000>, | |
| 753 | <0x11002000 0x2000>, | |
| 754 | <0x11004000 0x2000>, | |
| 755 | <0x11006000 0x2000>; | |
| 756 | interrupts = <GIC_PPI 9 0xf04>; | |
| 757 | }; | |
| 758 | ||
| 0e879a3e | 759 | mipi_phy: video-phy { |
| 5f04c4cf CC |
760 | compatible = "samsung,exynos5433-mipi-video-phy"; |
| 761 | #phy-cells = <1>; | |
| 762 | samsung,pmu-syscon = <&pmu_system_controller>; | |
| 763 | samsung,cam0-sysreg = <&syscon_cam0>; | |
| 764 | samsung,cam1-sysreg = <&syscon_cam1>; | |
| 765 | samsung,disp-sysreg = <&syscon_disp>; | |
| 766 | }; | |
| 767 | ||
| 768 | decon: decon@13800000 { | |
| 769 | compatible = "samsung,exynos5433-decon"; | |
| 770 | reg = <0x13800000 0x2104>; | |
| 771 | clocks = <&cmu_disp CLK_PCLK_DECON>, | |
| 772 | <&cmu_disp CLK_ACLK_DECON>, | |
| 773 | <&cmu_disp CLK_ACLK_SMMU_DECON0X>, | |
| 774 | <&cmu_disp CLK_ACLK_XIU_DECON0X>, | |
| 775 | <&cmu_disp CLK_PCLK_SMMU_DECON0X>, | |
| 776 | <&cmu_disp CLK_SCLK_DECON_VCLK>, | |
| 777 | <&cmu_disp CLK_SCLK_DECON_ECLK>; | |
| 778 | clock-names = "pclk", "aclk_decon", "aclk_smmu_decon0x", | |
| 779 | "aclk_xiu_decon0x", "pclk_smmu_decon0x", | |
| 780 | "sclk_decon_vclk", "sclk_decon_eclk"; | |
| 9715ed87 | 781 | power-domains = <&pd_disp>; |
| 5f04c4cf | 782 | interrupt-names = "fifo", "vsync", "lcd_sys"; |
| cebef6be MS |
783 | interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, |
| 784 | <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, | |
| 785 | <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; | |
| 5f04c4cf CC |
786 | samsung,disp-sysreg = <&syscon_disp>; |
| 787 | status = "disabled"; | |
| 788 | iommus = <&sysmmu_decon0x>, <&sysmmu_decon1x>; | |
| 789 | iommu-names = "m0", "m1"; | |
| 790 | ||
| 791 | ports { | |
| 792 | #address-cells = <1>; | |
| 793 | #size-cells = <0>; | |
| 794 | ||
| 795 | port@0 { | |
| 796 | reg = <0>; | |
| 797 | decon_to_mic: endpoint { | |
| 798 | remote-endpoint = | |
| 799 | <&mic_to_decon>; | |
| 800 | }; | |
| 801 | }; | |
| 802 | }; | |
| 803 | }; | |
| 804 | ||
| e80deee0 AH |
805 | decon_tv: decon@13880000 { |
| 806 | compatible = "samsung,exynos5433-decon-tv"; | |
| 807 | reg = <0x13880000 0x20b8>; | |
| 808 | clocks = <&cmu_disp CLK_PCLK_DECON_TV>, | |
| 809 | <&cmu_disp CLK_ACLK_DECON_TV>, | |
| 810 | <&cmu_disp CLK_ACLK_SMMU_TV0X>, | |
| 811 | <&cmu_disp CLK_ACLK_XIU_TV0X>, | |
| 812 | <&cmu_disp CLK_PCLK_SMMU_TV0X>, | |
| 813 | <&cmu_disp CLK_SCLK_DECON_TV_VCLK>, | |
| 814 | <&cmu_disp CLK_SCLK_DECON_TV_ECLK>; | |
| 815 | clock-names = "pclk", "aclk_decon", "aclk_smmu_decon0x", | |
| 816 | "aclk_xiu_decon0x", "pclk_smmu_decon0x", | |
| 817 | "sclk_decon_vclk", "sclk_decon_eclk"; | |
| 818 | samsung,disp-sysreg = <&syscon_disp>; | |
| 9715ed87 | 819 | power-domains = <&pd_disp>; |
| e80deee0 AH |
820 | interrupt-names = "fifo", "vsync", "lcd_sys"; |
| 821 | interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, | |
| 822 | <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, | |
| 823 | <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>; | |
| 824 | status = "disabled"; | |
| 825 | iommus = <&sysmmu_tv0x>, <&sysmmu_tv1x>; | |
| 826 | iommu-names = "m0", "m1"; | |
| 827 | }; | |
| 828 | ||
| 5f04c4cf CC |
829 | dsi: dsi@13900000 { |
| 830 | compatible = "samsung,exynos5433-mipi-dsi"; | |
| 831 | reg = <0x13900000 0xC0>; | |
| cebef6be | 832 | interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; |
| 5f04c4cf CC |
833 | phys = <&mipi_phy 1>; |
| 834 | phy-names = "dsim"; | |
| 835 | clocks = <&cmu_disp CLK_PCLK_DSIM0>, | |
| 836 | <&cmu_disp CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8>, | |
| 837 | <&cmu_disp CLK_PHYCLK_MIPIDPHY0_RXCLKESC0>, | |
| 838 | <&cmu_disp CLK_SCLK_RGB_VCLK_TO_DSIM0>, | |
| 839 | <&cmu_disp CLK_SCLK_DSIM0>; | |
| 840 | clock-names = "bus_clk", | |
| 841 | "phyclk_mipidphy0_bitclkdiv8", | |
| 842 | "phyclk_mipidphy0_rxclkesc0", | |
| 843 | "sclk_rgb_vclk_to_dsim0", | |
| 844 | "sclk_mipi"; | |
| 9715ed87 | 845 | power-domains = <&pd_disp>; |
| 5f04c4cf CC |
846 | status = "disabled"; |
| 847 | #address-cells = <1>; | |
| 848 | #size-cells = <0>; | |
| 849 | ||
| 850 | ports { | |
| 851 | #address-cells = <1>; | |
| 852 | #size-cells = <0>; | |
| 853 | ||
| 854 | port@0 { | |
| 855 | reg = <0>; | |
| 856 | dsi_to_mic: endpoint { | |
| 857 | remote-endpoint = <&mic_to_dsi>; | |
| 858 | }; | |
| 859 | }; | |
| 860 | }; | |
| 861 | }; | |
| 862 | ||
| 863 | mic: mic@13930000 { | |
| 864 | compatible = "samsung,exynos5433-mic"; | |
| 865 | reg = <0x13930000 0x48>; | |
| 866 | clocks = <&cmu_disp CLK_PCLK_MIC0>, | |
| 867 | <&cmu_disp CLK_SCLK_RGB_VCLK_TO_MIC0>; | |
| 868 | clock-names = "pclk_mic0", "sclk_rgb_vclk_to_mic0"; | |
| 9715ed87 | 869 | power-domains = <&pd_disp>; |
| 5f04c4cf CC |
870 | samsung,disp-syscon = <&syscon_disp>; |
| 871 | status = "disabled"; | |
| 872 | ||
| 873 | ports { | |
| 874 | #address-cells = <1>; | |
| 875 | #size-cells = <0>; | |
| 876 | ||
| 877 | port@0 { | |
| 878 | reg = <0>; | |
| 879 | mic_to_decon: endpoint { | |
| 880 | remote-endpoint = | |
| 881 | <&decon_to_mic>; | |
| 882 | }; | |
| 883 | }; | |
| 884 | ||
| 885 | port@1 { | |
| 886 | reg = <1>; | |
| 887 | mic_to_dsi: endpoint { | |
| 888 | remote-endpoint = <&dsi_to_mic>; | |
| 889 | }; | |
| 890 | }; | |
| 891 | }; | |
| 892 | }; | |
| 893 | ||
| cb872bd9 AH |
894 | hdmi: hdmi@13970000 { |
| 895 | compatible = "samsung,exynos5433-hdmi"; | |
| 896 | reg = <0x13970000 0x70000>; | |
| 897 | interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; | |
| 898 | clocks = <&cmu_disp CLK_PCLK_HDMI>, | |
| 899 | <&cmu_disp CLK_PCLK_HDMIPHY>, | |
| 900 | <&cmu_disp CLK_PHYCLK_HDMIPHY_TMDS_CLKO>, | |
| 901 | <&cmu_disp CLK_PHYCLK_HDMI_PIXEL>, | |
| 902 | <&cmu_disp CLK_PHYCLK_HDMIPHY_TMDS_CLKO_PHY>, | |
| 903 | <&cmu_disp CLK_MOUT_PHYCLK_HDMIPHY_TMDS_CLKO_USER>, | |
| 904 | <&cmu_disp CLK_PHYCLK_HDMIPHY_PIXEL_CLKO_PHY>, | |
| 905 | <&cmu_disp CLK_MOUT_PHYCLK_HDMIPHY_PIXEL_CLKO_USER>, | |
| 906 | <&xxti>, <&cmu_disp CLK_SCLK_HDMI_SPDIF>; | |
| 907 | clock-names = "hdmi_pclk", "hdmi_i_pclk", | |
| 908 | "i_tmds_clk", "i_pixel_clk", | |
| 909 | "tmds_clko", "tmds_clko_user", | |
| 910 | "pixel_clko", "pixel_clko_user", | |
| 911 | "oscclk", "i_spdif_clk"; | |
| 912 | phy = <&hdmiphy>; | |
| 913 | ddc = <&hsi2c_11>; | |
| 914 | samsung,syscon-phandle = <&pmu_system_controller>; | |
| 915 | samsung,sysreg-phandle = <&syscon_disp>; | |
| 916 | status = "disabled"; | |
| 917 | }; | |
| 918 | ||
| 919 | hdmiphy: hdmiphy@13af0000 { | |
| 920 | reg = <0x13af0000 0x80>; | |
| 921 | }; | |
| 922 | ||
| 5f04c4cf CC |
923 | syscon_disp: syscon@13b80000 { |
| 924 | compatible = "syscon"; | |
| 925 | reg = <0x13b80000 0x1010>; | |
| 926 | }; | |
| 927 | ||
| 928 | syscon_cam0: syscon@120f0000 { | |
| 929 | compatible = "syscon"; | |
| 930 | reg = <0x120f0000 0x1020>; | |
| 931 | }; | |
| 932 | ||
| 933 | syscon_cam1: syscon@145f0000 { | |
| 934 | compatible = "syscon"; | |
| 935 | reg = <0x145f0000 0x1038>; | |
| 936 | }; | |
| 937 | ||
| 88b9ca09 MS |
938 | gsc_0: video-scaler@13C00000 { |
| 939 | compatible = "samsung,exynos5433-gsc"; | |
| 940 | reg = <0x13c00000 0x1000>; | |
| 941 | interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>; | |
| 942 | clock-names = "pclk", "aclk", "aclk_xiu", | |
| 943 | "aclk_gsclbend"; | |
| 944 | clocks = <&cmu_gscl CLK_PCLK_GSCL0>, | |
| 945 | <&cmu_gscl CLK_ACLK_GSCL0>, | |
| 946 | <&cmu_gscl CLK_ACLK_XIU_GSCLX>, | |
| 947 | <&cmu_gscl CLK_ACLK_GSCLBEND_333>; | |
| 948 | iommus = <&sysmmu_gscl0>; | |
| c2607220 | 949 | power-domains = <&pd_gscl>; |
| 88b9ca09 MS |
950 | }; |
| 951 | ||
| 952 | gsc_1: video-scaler@13C10000 { | |
| 953 | compatible = "samsung,exynos5433-gsc"; | |
| 954 | reg = <0x13c10000 0x1000>; | |
| 955 | interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; | |
| 956 | clock-names = "pclk", "aclk", "aclk_xiu", | |
| 957 | "aclk_gsclbend"; | |
| 958 | clocks = <&cmu_gscl CLK_PCLK_GSCL1>, | |
| 959 | <&cmu_gscl CLK_ACLK_GSCL1>, | |
| 960 | <&cmu_gscl CLK_ACLK_XIU_GSCLX>, | |
| 961 | <&cmu_gscl CLK_ACLK_GSCLBEND_333>; | |
| 962 | iommus = <&sysmmu_gscl1>; | |
| c2607220 | 963 | power-domains = <&pd_gscl>; |
| 88b9ca09 MS |
964 | }; |
| 965 | ||
| 966 | gsc_2: video-scaler@13C20000 { | |
| 967 | compatible = "samsung,exynos5433-gsc"; | |
| 968 | reg = <0x13c20000 0x1000>; | |
| 969 | interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; | |
| 970 | clock-names = "pclk", "aclk", "aclk_xiu", | |
| 971 | "aclk_gsclbend"; | |
| 972 | clocks = <&cmu_gscl CLK_PCLK_GSCL2>, | |
| 973 | <&cmu_gscl CLK_ACLK_GSCL2>, | |
| 974 | <&cmu_gscl CLK_ACLK_XIU_GSCLX>, | |
| 975 | <&cmu_gscl CLK_ACLK_GSCLBEND_333>; | |
| 976 | iommus = <&sysmmu_gscl2>; | |
| c2607220 | 977 | power-domains = <&pd_gscl>; |
| 88b9ca09 MS |
978 | }; |
| 979 | ||
| e036c75a MS |
980 | jpeg: codec@15020000 { |
| 981 | compatible = "samsung,exynos5433-jpeg"; | |
| 982 | reg = <0x15020000 0x10000>; | |
| 983 | interrupts = <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>; | |
| 984 | clock-names = "pclk", "aclk", "aclk_xiu", "sclk"; | |
| 985 | clocks = <&cmu_mscl CLK_PCLK_JPEG>, | |
| 986 | <&cmu_mscl CLK_ACLK_JPEG>, | |
| 987 | <&cmu_mscl CLK_ACLK_XIU_MSCLX>, | |
| 988 | <&cmu_mscl CLK_SCLK_JPEG>; | |
| 989 | iommus = <&sysmmu_jpeg>; | |
| e45dda53 | 990 | power-domains = <&pd_mscl>; |
| e036c75a MS |
991 | }; |
| 992 | ||
| 74c78036 MS |
993 | mfc: codec@152E0000 { |
| 994 | compatible = "samsung,exynos5433-mfc"; | |
| 995 | reg = <0x152E0000 0x10000>; | |
| 996 | interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; | |
| 997 | clock-names = "pclk", "aclk", "aclk_xiu"; | |
| 998 | clocks = <&cmu_mfc CLK_PCLK_MFC>, | |
| 999 | <&cmu_mfc CLK_ACLK_MFC>, | |
| 1000 | <&cmu_mfc CLK_ACLK_XIU_MFCX>; | |
| 1001 | iommus = <&sysmmu_mfc_0>, <&sysmmu_mfc_1>; | |
| 1002 | iommu-names = "left", "right"; | |
| c4e7aba6 | 1003 | power-domains = <&pd_mfc>; |
| 74c78036 MS |
1004 | }; |
| 1005 | ||
| df5d5a93 | 1006 | sysmmu_decon0x: sysmmu@13a00000 { |
| 5f04c4cf CC |
1007 | compatible = "samsung,exynos-sysmmu"; |
| 1008 | reg = <0x13a00000 0x1000>; | |
| cebef6be | 1009 | interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; |
| 5f04c4cf CC |
1010 | clock-names = "pclk", "aclk"; |
| 1011 | clocks = <&cmu_disp CLK_PCLK_SMMU_DECON0X>, | |
| 1012 | <&cmu_disp CLK_ACLK_SMMU_DECON0X>; | |
| 9715ed87 | 1013 | power-domains = <&pd_disp>; |
| 5f04c4cf CC |
1014 | #iommu-cells = <0>; |
| 1015 | }; | |
| 1016 | ||
| df5d5a93 | 1017 | sysmmu_decon1x: sysmmu@13a10000 { |
| 5f04c4cf CC |
1018 | compatible = "samsung,exynos-sysmmu"; |
| 1019 | reg = <0x13a10000 0x1000>; | |
| cebef6be | 1020 | interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; |
| 5f04c4cf CC |
1021 | clock-names = "pclk", "aclk"; |
| 1022 | clocks = <&cmu_disp CLK_PCLK_SMMU_DECON1X>, | |
| 1023 | <&cmu_disp CLK_ACLK_SMMU_DECON1X>; | |
| 1024 | #iommu-cells = <0>; | |
| 9715ed87 | 1025 | power-domains = <&pd_disp>; |
| 5f04c4cf CC |
1026 | }; |
| 1027 | ||
| e80deee0 AH |
1028 | sysmmu_tv0x: sysmmu@13a20000 { |
| 1029 | compatible = "samsung,exynos-sysmmu"; | |
| 1030 | reg = <0x13a20000 0x1000>; | |
| 1031 | interrupts = <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>; | |
| 1032 | clock-names = "pclk", "aclk"; | |
| 1033 | clocks = <&cmu_disp CLK_PCLK_SMMU_TV0X>, | |
| 1034 | <&cmu_disp CLK_ACLK_SMMU_TV0X>; | |
| 1035 | #iommu-cells = <0>; | |
| 9715ed87 | 1036 | power-domains = <&pd_disp>; |
| e80deee0 AH |
1037 | }; |
| 1038 | ||
| 1039 | sysmmu_tv1x: sysmmu@13a30000 { | |
| 1040 | compatible = "samsung,exynos-sysmmu"; | |
| 1041 | reg = <0x13a30000 0x1000>; | |
| 1042 | interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>; | |
| 1043 | clock-names = "pclk", "aclk"; | |
| 1044 | clocks = <&cmu_disp CLK_PCLK_SMMU_TV1X>, | |
| 1045 | <&cmu_disp CLK_ACLK_SMMU_TV1X>; | |
| 1046 | #iommu-cells = <0>; | |
| 9715ed87 | 1047 | power-domains = <&pd_disp>; |
| e80deee0 AH |
1048 | }; |
| 1049 | ||
| df5d5a93 | 1050 | sysmmu_gscl0: sysmmu@13c80000 { |
| 88b9ca09 MS |
1051 | compatible = "samsung,exynos-sysmmu"; |
| 1052 | reg = <0x13C80000 0x1000>; | |
| 1053 | interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; | |
| 1054 | clock-names = "aclk", "pclk"; | |
| 1055 | clocks = <&cmu_gscl CLK_ACLK_SMMU_GSCL0>, | |
| 1056 | <&cmu_gscl CLK_PCLK_SMMU_GSCL0>; | |
| 1057 | #iommu-cells = <0>; | |
| c2607220 | 1058 | power-domains = <&pd_gscl>; |
| 88b9ca09 MS |
1059 | }; |
| 1060 | ||
| df5d5a93 | 1061 | sysmmu_gscl1: sysmmu@13c90000 { |
| 88b9ca09 MS |
1062 | compatible = "samsung,exynos-sysmmu"; |
| 1063 | reg = <0x13C90000 0x1000>; | |
| 1064 | interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; | |
| 1065 | clock-names = "aclk", "pclk"; | |
| 1066 | clocks = <&cmu_gscl CLK_ACLK_SMMU_GSCL1>, | |
| 1067 | <&cmu_gscl CLK_PCLK_SMMU_GSCL1>; | |
| 1068 | #iommu-cells = <0>; | |
| c2607220 | 1069 | power-domains = <&pd_gscl>; |
| 88b9ca09 MS |
1070 | }; |
| 1071 | ||
| df5d5a93 | 1072 | sysmmu_gscl2: sysmmu@13ca0000 { |
| 88b9ca09 MS |
1073 | compatible = "samsung,exynos-sysmmu"; |
| 1074 | reg = <0x13CA0000 0x1000>; | |
| 1075 | interrupts = <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>; | |
| 1076 | clock-names = "aclk", "pclk"; | |
| 1077 | clocks = <&cmu_gscl CLK_ACLK_SMMU_GSCL2>, | |
| 1078 | <&cmu_gscl CLK_PCLK_SMMU_GSCL2>; | |
| 1079 | #iommu-cells = <0>; | |
| c2607220 | 1080 | power-domains = <&pd_gscl>; |
| 88b9ca09 MS |
1081 | }; |
| 1082 | ||
| df5d5a93 | 1083 | sysmmu_jpeg: sysmmu@15060000 { |
| e036c75a MS |
1084 | compatible = "samsung,exynos-sysmmu"; |
| 1085 | reg = <0x15060000 0x1000>; | |
| 1086 | interrupts = <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; | |
| 1087 | clock-names = "pclk", "aclk"; | |
| 1088 | clocks = <&cmu_mscl CLK_PCLK_SMMU_JPEG>, | |
| 1089 | <&cmu_mscl CLK_ACLK_SMMU_JPEG>; | |
| 1090 | #iommu-cells = <0>; | |
| e45dda53 | 1091 | power-domains = <&pd_mscl>; |
| e036c75a MS |
1092 | }; |
| 1093 | ||
| df5d5a93 | 1094 | sysmmu_mfc_0: sysmmu@15200000 { |
| 74c78036 MS |
1095 | compatible = "samsung,exynos-sysmmu"; |
| 1096 | reg = <0x15200000 0x1000>; | |
| 1097 | interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; | |
| 1098 | clock-names = "pclk", "aclk"; | |
| 1099 | clocks = <&cmu_mfc CLK_PCLK_SMMU_MFC_0>, | |
| 1100 | <&cmu_mfc CLK_ACLK_SMMU_MFC_0>; | |
| 1101 | #iommu-cells = <0>; | |
| c4e7aba6 | 1102 | power-domains = <&pd_mfc>; |
| 74c78036 MS |
1103 | }; |
| 1104 | ||
| df5d5a93 | 1105 | sysmmu_mfc_1: sysmmu@15210000 { |
| 74c78036 MS |
1106 | compatible = "samsung,exynos-sysmmu"; |
| 1107 | reg = <0x15210000 0x1000>; | |
| 1108 | interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; | |
| 1109 | clock-names = "pclk", "aclk"; | |
| 1110 | clocks = <&cmu_mfc CLK_PCLK_SMMU_MFC_1>, | |
| 1111 | <&cmu_mfc CLK_ACLK_SMMU_MFC_1>; | |
| 1112 | #iommu-cells = <0>; | |
| c4e7aba6 | 1113 | power-domains = <&pd_mfc>; |
| 74c78036 MS |
1114 | }; |
| 1115 | ||
| 5f04c4cf CC |
1116 | serial_0: serial@14c10000 { |
| 1117 | compatible = "samsung,exynos5433-uart"; | |
| 1118 | reg = <0x14c10000 0x100>; | |
| cebef6be | 1119 | interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>; |
| 5f04c4cf CC |
1120 | clocks = <&cmu_peric CLK_PCLK_UART0>, |
| 1121 | <&cmu_peric CLK_SCLK_UART0>; | |
| 1122 | clock-names = "uart", "clk_uart_baud0"; | |
| 1123 | pinctrl-names = "default"; | |
| 1124 | pinctrl-0 = <&uart0_bus>; | |
| 1125 | status = "disabled"; | |
| 1126 | }; | |
| 1127 | ||
| 1128 | serial_1: serial@14c20000 { | |
| 1129 | compatible = "samsung,exynos5433-uart"; | |
| 1130 | reg = <0x14c20000 0x100>; | |
| cebef6be | 1131 | interrupts = <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>; |
| 5f04c4cf CC |
1132 | clocks = <&cmu_peric CLK_PCLK_UART1>, |
| 1133 | <&cmu_peric CLK_SCLK_UART1>; | |
| 1134 | clock-names = "uart", "clk_uart_baud0"; | |
| 1135 | pinctrl-names = "default"; | |
| 1136 | pinctrl-0 = <&uart1_bus>; | |
| 1137 | status = "disabled"; | |
| 1138 | }; | |
| 1139 | ||
| 1140 | serial_2: serial@14c30000 { | |
| 1141 | compatible = "samsung,exynos5433-uart"; | |
| 1142 | reg = <0x14c30000 0x100>; | |
| cebef6be | 1143 | interrupts = <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>; |
| 5f04c4cf CC |
1144 | clocks = <&cmu_peric CLK_PCLK_UART2>, |
| 1145 | <&cmu_peric CLK_SCLK_UART2>; | |
| 1146 | clock-names = "uart", "clk_uart_baud0"; | |
| 1147 | pinctrl-names = "default"; | |
| 1148 | pinctrl-0 = <&uart2_bus>; | |
| 1149 | status = "disabled"; | |
| 1150 | }; | |
| 1151 | ||
| 1152 | spi_0: spi@14d20000 { | |
| 1153 | compatible = "samsung,exynos5433-spi"; | |
| 1154 | reg = <0x14d20000 0x100>; | |
| cebef6be | 1155 | interrupts = <GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>; |
| 5f04c4cf CC |
1156 | dmas = <&pdma0 9>, <&pdma0 8>; |
| 1157 | dma-names = "tx", "rx"; | |
| 1158 | #address-cells = <1>; | |
| 1159 | #size-cells = <0>; | |
| 1160 | clocks = <&cmu_peric CLK_PCLK_SPI0>, | |
| 1161 | <&cmu_peric CLK_SCLK_SPI0>, | |
| 1162 | <&cmu_peric CLK_SCLK_IOCLK_SPI0>; | |
| 1163 | clock-names = "spi", "spi_busclk0", "spi_ioclk"; | |
| 1164 | samsung,spi-src-clk = <0>; | |
| 1165 | pinctrl-names = "default"; | |
| 1166 | pinctrl-0 = <&spi0_bus>; | |
| 1167 | num-cs = <1>; | |
| 1168 | status = "disabled"; | |
| 1169 | }; | |
| 1170 | ||
| 1171 | spi_1: spi@14d30000 { | |
| 1172 | compatible = "samsung,exynos5433-spi"; | |
| 1173 | reg = <0x14d30000 0x100>; | |
| cebef6be | 1174 | interrupts = <GIC_SPI 433 IRQ_TYPE_LEVEL_HIGH>; |
| 5f04c4cf CC |
1175 | dmas = <&pdma0 11>, <&pdma0 10>; |
| 1176 | dma-names = "tx", "rx"; | |
| 1177 | #address-cells = <1>; | |
| 1178 | #size-cells = <0>; | |
| 1179 | clocks = <&cmu_peric CLK_PCLK_SPI1>, | |
| 1180 | <&cmu_peric CLK_SCLK_SPI1>, | |
| 1181 | <&cmu_peric CLK_SCLK_IOCLK_SPI1>; | |
| 1182 | clock-names = "spi", "spi_busclk0", "spi_ioclk"; | |
| 1183 | samsung,spi-src-clk = <0>; | |
| 1184 | pinctrl-names = "default"; | |
| 1185 | pinctrl-0 = <&spi1_bus>; | |
| 1186 | num-cs = <1>; | |
| 1187 | status = "disabled"; | |
| 1188 | }; | |
| 1189 | ||
| 1190 | spi_2: spi@14d40000 { | |
| 1191 | compatible = "samsung,exynos5433-spi"; | |
| 1192 | reg = <0x14d40000 0x100>; | |
| cebef6be | 1193 | interrupts = <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>; |
| 5f04c4cf CC |
1194 | dmas = <&pdma0 13>, <&pdma0 12>; |
| 1195 | dma-names = "tx", "rx"; | |
| 1196 | #address-cells = <1>; | |
| 1197 | #size-cells = <0>; | |
| 1198 | clocks = <&cmu_peric CLK_PCLK_SPI2>, | |
| 1199 | <&cmu_peric CLK_SCLK_SPI2>, | |
| 1200 | <&cmu_peric CLK_SCLK_IOCLK_SPI2>; | |
| 1201 | clock-names = "spi", "spi_busclk0", "spi_ioclk"; | |
| 1202 | samsung,spi-src-clk = <0>; | |
| 1203 | pinctrl-names = "default"; | |
| 1204 | pinctrl-0 = <&spi2_bus>; | |
| 1205 | num-cs = <1>; | |
| 1206 | status = "disabled"; | |
| 1207 | }; | |
| 1208 | ||
| 1209 | spi_3: spi@14d50000 { | |
| 1210 | compatible = "samsung,exynos5433-spi"; | |
| 1211 | reg = <0x14d50000 0x100>; | |
| cebef6be | 1212 | interrupts = <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>; |
| 5f04c4cf CC |
1213 | dmas = <&pdma0 23>, <&pdma0 22>; |
| 1214 | dma-names = "tx", "rx"; | |
| 1215 | #address-cells = <1>; | |
| 1216 | #size-cells = <0>; | |
| 1217 | clocks = <&cmu_peric CLK_PCLK_SPI3>, | |
| 1218 | <&cmu_peric CLK_SCLK_SPI3>, | |
| 1219 | <&cmu_peric CLK_SCLK_IOCLK_SPI3>; | |
| 1220 | clock-names = "spi", "spi_busclk0", "spi_ioclk"; | |
| 1221 | samsung,spi-src-clk = <0>; | |
| 1222 | pinctrl-names = "default"; | |
| 1223 | pinctrl-0 = <&spi3_bus>; | |
| 1224 | num-cs = <1>; | |
| 1225 | status = "disabled"; | |
| 1226 | }; | |
| 1227 | ||
| 1228 | spi_4: spi@14d00000 { | |
| 1229 | compatible = "samsung,exynos5433-spi"; | |
| 1230 | reg = <0x14d00000 0x100>; | |
| cebef6be | 1231 | interrupts = <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>; |
| 5f04c4cf CC |
1232 | dmas = <&pdma0 25>, <&pdma0 24>; |
| 1233 | dma-names = "tx", "rx"; | |
| 1234 | #address-cells = <1>; | |
| 1235 | #size-cells = <0>; | |
| 1236 | clocks = <&cmu_peric CLK_PCLK_SPI4>, | |
| 1237 | <&cmu_peric CLK_SCLK_SPI4>, | |
| 1238 | <&cmu_peric CLK_SCLK_IOCLK_SPI4>; | |
| 1239 | clock-names = "spi", "spi_busclk0", "spi_ioclk"; | |
| 1240 | samsung,spi-src-clk = <0>; | |
| 1241 | pinctrl-names = "default"; | |
| 1242 | pinctrl-0 = <&spi4_bus>; | |
| 1243 | num-cs = <1>; | |
| 1244 | status = "disabled"; | |
| 1245 | }; | |
| 1246 | ||
| 1247 | adc: adc@14d10000 { | |
| 1248 | compatible = "samsung,exynos7-adc"; | |
| 1249 | reg = <0x14d10000 0x100>; | |
| cebef6be | 1250 | interrupts = <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>; |
| 5f04c4cf CC |
1251 | clock-names = "adc"; |
| 1252 | clocks = <&cmu_peric CLK_PCLK_ADCIF>; | |
| 1253 | #io-channel-cells = <1>; | |
| 1254 | io-channel-ranges; | |
| 1255 | status = "disabled"; | |
| 1256 | }; | |
| 1257 | ||
| 1258 | pwm: pwm@14dd0000 { | |
| 1259 | compatible = "samsung,exynos4210-pwm"; | |
| 1260 | reg = <0x14dd0000 0x100>; | |
| cebef6be MS |
1261 | interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, |
| 1262 | <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, | |
| 1263 | <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, | |
| 1264 | <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, | |
| 1265 | <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>; | |
| 5f04c4cf CC |
1266 | samsung,pwm-outputs = <0>, <1>, <2>, <3>; |
| 1267 | clocks = <&cmu_peric CLK_PCLK_PWM>; | |
| 1268 | clock-names = "timers"; | |
| 1269 | #pwm-cells = <3>; | |
| 1270 | status = "disabled"; | |
| 1271 | }; | |
| 1272 | ||
| 1273 | hsi2c_0: hsi2c@14e40000 { | |
| 1274 | compatible = "samsung,exynos7-hsi2c"; | |
| 1275 | reg = <0x14e40000 0x1000>; | |
| cebef6be | 1276 | interrupts = <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>; |
| 5f04c4cf CC |
1277 | #address-cells = <1>; |
| 1278 | #size-cells = <0>; | |
| 1279 | pinctrl-names = "default"; | |
| 1280 | pinctrl-0 = <&hs_i2c0_bus>; | |
| 1281 | clocks = <&cmu_peric CLK_PCLK_HSI2C0>; | |
| 1282 | clock-names = "hsi2c"; | |
| 1283 | status = "disabled"; | |
| 1284 | }; | |
| 1285 | ||
| 1286 | hsi2c_1: hsi2c@14e50000 { | |
| 1287 | compatible = "samsung,exynos7-hsi2c"; | |
| 1288 | reg = <0x14e50000 0x1000>; | |
| cebef6be | 1289 | interrupts = <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>; |
| 5f04c4cf CC |
1290 | #address-cells = <1>; |
| 1291 | #size-cells = <0>; | |
| 1292 | pinctrl-names = "default"; | |
| 1293 | pinctrl-0 = <&hs_i2c1_bus>; | |
| 1294 | clocks = <&cmu_peric CLK_PCLK_HSI2C1>; | |
| 1295 | clock-names = "hsi2c"; | |
| 1296 | status = "disabled"; | |
| 1297 | }; | |
| 1298 | ||
| 1299 | hsi2c_2: hsi2c@14e60000 { | |
| 1300 | compatible = "samsung,exynos7-hsi2c"; | |
| 1301 | reg = <0x14e60000 0x1000>; | |
| cebef6be | 1302 | interrupts = <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>; |
| 5f04c4cf CC |
1303 | #address-cells = <1>; |
| 1304 | #size-cells = <0>; | |
| 1305 | pinctrl-names = "default"; | |
| 1306 | pinctrl-0 = <&hs_i2c2_bus>; | |
| 1307 | clocks = <&cmu_peric CLK_PCLK_HSI2C2>; | |
| 1308 | clock-names = "hsi2c"; | |
| 1309 | status = "disabled"; | |
| 1310 | }; | |
| 1311 | ||
| 1312 | hsi2c_3: hsi2c@14e70000 { | |
| 1313 | compatible = "samsung,exynos7-hsi2c"; | |
| 1314 | reg = <0x14e70000 0x1000>; | |
| cebef6be | 1315 | interrupts = <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>; |
| 5f04c4cf CC |
1316 | #address-cells = <1>; |
| 1317 | #size-cells = <0>; | |
| 1318 | pinctrl-names = "default"; | |
| 1319 | pinctrl-0 = <&hs_i2c3_bus>; | |
| 1320 | clocks = <&cmu_peric CLK_PCLK_HSI2C3>; | |
| 1321 | clock-names = "hsi2c"; | |
| 1322 | status = "disabled"; | |
| 1323 | }; | |
| 1324 | ||
| 1325 | hsi2c_4: hsi2c@14ec0000 { | |
| 1326 | compatible = "samsung,exynos7-hsi2c"; | |
| 1327 | reg = <0x14ec0000 0x1000>; | |
| cebef6be | 1328 | interrupts = <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>; |
| 5f04c4cf CC |
1329 | #address-cells = <1>; |
| 1330 | #size-cells = <0>; | |
| 1331 | pinctrl-names = "default"; | |
| 1332 | pinctrl-0 = <&hs_i2c4_bus>; | |
| 1333 | clocks = <&cmu_peric CLK_PCLK_HSI2C4>; | |
| 1334 | clock-names = "hsi2c"; | |
| 1335 | status = "disabled"; | |
| 1336 | }; | |
| 1337 | ||
| 1338 | hsi2c_5: hsi2c@14ed0000 { | |
| 1339 | compatible = "samsung,exynos7-hsi2c"; | |
| 1340 | reg = <0x14ed0000 0x1000>; | |
| cebef6be | 1341 | interrupts = <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>; |
| 5f04c4cf CC |
1342 | #address-cells = <1>; |
| 1343 | #size-cells = <0>; | |
| 1344 | pinctrl-names = "default"; | |
| 1345 | pinctrl-0 = <&hs_i2c5_bus>; | |
| 1346 | clocks = <&cmu_peric CLK_PCLK_HSI2C5>; | |
| 1347 | clock-names = "hsi2c"; | |
| 1348 | status = "disabled"; | |
| 1349 | }; | |
| 1350 | ||
| 1351 | hsi2c_6: hsi2c@14ee0000 { | |
| 1352 | compatible = "samsung,exynos7-hsi2c"; | |
| 1353 | reg = <0x14ee0000 0x1000>; | |
| cebef6be | 1354 | interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>; |
| 5f04c4cf CC |
1355 | #address-cells = <1>; |
| 1356 | #size-cells = <0>; | |
| 1357 | pinctrl-names = "default"; | |
| 1358 | pinctrl-0 = <&hs_i2c6_bus>; | |
| 1359 | clocks = <&cmu_peric CLK_PCLK_HSI2C6>; | |
| 1360 | clock-names = "hsi2c"; | |
| 1361 | status = "disabled"; | |
| 1362 | }; | |
| 1363 | ||
| 1364 | hsi2c_7: hsi2c@14ef0000 { | |
| 1365 | compatible = "samsung,exynos7-hsi2c"; | |
| 1366 | reg = <0x14ef0000 0x1000>; | |
| cebef6be | 1367 | interrupts = <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>; |
| 5f04c4cf CC |
1368 | #address-cells = <1>; |
| 1369 | #size-cells = <0>; | |
| 1370 | pinctrl-names = "default"; | |
| 1371 | pinctrl-0 = <&hs_i2c7_bus>; | |
| 1372 | clocks = <&cmu_peric CLK_PCLK_HSI2C7>; | |
| 1373 | clock-names = "hsi2c"; | |
| 1374 | status = "disabled"; | |
| 1375 | }; | |
| 1376 | ||
| 1377 | hsi2c_8: hsi2c@14d90000 { | |
| 1378 | compatible = "samsung,exynos7-hsi2c"; | |
| 1379 | reg = <0x14d90000 0x1000>; | |
| cebef6be | 1380 | interrupts = <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>; |
| 5f04c4cf CC |
1381 | #address-cells = <1>; |
| 1382 | #size-cells = <0>; | |
| 1383 | pinctrl-names = "default"; | |
| 1384 | pinctrl-0 = <&hs_i2c8_bus>; | |
| 1385 | clocks = <&cmu_peric CLK_PCLK_HSI2C8>; | |
| 1386 | clock-names = "hsi2c"; | |
| 1387 | status = "disabled"; | |
| 1388 | }; | |
| 1389 | ||
| 1390 | hsi2c_9: hsi2c@14da0000 { | |
| 1391 | compatible = "samsung,exynos7-hsi2c"; | |
| 1392 | reg = <0x14da0000 0x1000>; | |
| cebef6be | 1393 | interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>; |
| 5f04c4cf CC |
1394 | #address-cells = <1>; |
| 1395 | #size-cells = <0>; | |
| 1396 | pinctrl-names = "default"; | |
| 1397 | pinctrl-0 = <&hs_i2c9_bus>; | |
| 1398 | clocks = <&cmu_peric CLK_PCLK_HSI2C9>; | |
| 1399 | clock-names = "hsi2c"; | |
| 1400 | status = "disabled"; | |
| 1401 | }; | |
| 1402 | ||
| 1403 | hsi2c_10: hsi2c@14de0000 { | |
| 1404 | compatible = "samsung,exynos7-hsi2c"; | |
| 1405 | reg = <0x14de0000 0x1000>; | |
| cebef6be | 1406 | interrupts = <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>; |
| 5f04c4cf CC |
1407 | #address-cells = <1>; |
| 1408 | #size-cells = <0>; | |
| 1409 | pinctrl-names = "default"; | |
| 1410 | pinctrl-0 = <&hs_i2c10_bus>; | |
| 1411 | clocks = <&cmu_peric CLK_PCLK_HSI2C10>; | |
| 1412 | clock-names = "hsi2c"; | |
| 1413 | status = "disabled"; | |
| 1414 | }; | |
| 1415 | ||
| 1416 | hsi2c_11: hsi2c@14df0000 { | |
| 1417 | compatible = "samsung,exynos7-hsi2c"; | |
| 1418 | reg = <0x14df0000 0x1000>; | |
| cebef6be | 1419 | interrupts = <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>; |
| 5f04c4cf CC |
1420 | #address-cells = <1>; |
| 1421 | #size-cells = <0>; | |
| 1422 | pinctrl-names = "default"; | |
| 1423 | pinctrl-0 = <&hs_i2c11_bus>; | |
| 1424 | clocks = <&cmu_peric CLK_PCLK_HSI2C11>; | |
| 1425 | clock-names = "hsi2c"; | |
| 1426 | status = "disabled"; | |
| 1427 | }; | |
| 1428 | ||
| 0e879a3e | 1429 | usbdrd30: usbdrd { |
| 5f04c4cf CC |
1430 | compatible = "samsung,exynos5250-dwusb3"; |
| 1431 | clocks = <&cmu_fsys CLK_ACLK_USBDRD30>, | |
| 1432 | <&cmu_fsys CLK_SCLK_USBDRD30>; | |
| 1433 | clock-names = "usbdrd30", "usbdrd30_susp_clk"; | |
| 5f04c4cf CC |
1434 | #address-cells = <1>; |
| 1435 | #size-cells = <1>; | |
| 1436 | ranges; | |
| 1437 | status = "disabled"; | |
| 1438 | ||
| a64d0ece | 1439 | usbdrd_dwc3: dwc3@15400000 { |
| 5f04c4cf CC |
1440 | compatible = "snps,dwc3"; |
| 1441 | reg = <0x15400000 0x10000>; | |
| cebef6be | 1442 | interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; |
| 5f04c4cf CC |
1443 | phys = <&usbdrd30_phy 0>, <&usbdrd30_phy 1>; |
| 1444 | phy-names = "usb2-phy", "usb3-phy"; | |
| 1445 | }; | |
| 1446 | }; | |
| 1447 | ||
| 1448 | usbdrd30_phy: phy@15500000 { | |
| 1449 | compatible = "samsung,exynos5433-usbdrd-phy"; | |
| 1450 | reg = <0x15500000 0x100>; | |
| 1451 | clocks = <&cmu_fsys CLK_ACLK_USBDRD30>, <&xxti>, | |
| 1452 | <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK>, | |
| 1453 | <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK>, | |
| 1454 | <&cmu_fsys CLK_SCLK_USBDRD30>; | |
| 1455 | clock-names = "phy", "ref", "phy_utmi", "phy_pipe", | |
| 1456 | "itp"; | |
| 5f04c4cf CC |
1457 | #phy-cells = <1>; |
| 1458 | samsung,pmu-syscon = <&pmu_system_controller>; | |
| 1459 | status = "disabled"; | |
| 1460 | }; | |
| 1461 | ||
| 1462 | usbhost30_phy: phy@15580000 { | |
| 1463 | compatible = "samsung,exynos5433-usbdrd-phy"; | |
| 1464 | reg = <0x15580000 0x100>; | |
| 1465 | clocks = <&cmu_fsys CLK_ACLK_USBHOST30>, <&xxti>, | |
| 1466 | <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK>, | |
| 1467 | <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK>, | |
| 1468 | <&cmu_fsys CLK_SCLK_USBHOST30>; | |
| 1469 | clock-names = "phy", "ref", "phy_utmi", "phy_pipe", | |
| 1470 | "itp"; | |
| 5f04c4cf CC |
1471 | #phy-cells = <1>; |
| 1472 | samsung,pmu-syscon = <&pmu_system_controller>; | |
| 1473 | status = "disabled"; | |
| 1474 | }; | |
| 1475 | ||
| 0e879a3e | 1476 | usbhost30: usbhost { |
| 5f04c4cf CC |
1477 | compatible = "samsung,exynos5250-dwusb3"; |
| 1478 | clocks = <&cmu_fsys CLK_ACLK_USBHOST30>, | |
| 1479 | <&cmu_fsys CLK_SCLK_USBHOST30>; | |
| 1480 | clock-names = "usbdrd30", "usbdrd30_susp_clk"; | |
| 5f04c4cf CC |
1481 | #address-cells = <1>; |
| 1482 | #size-cells = <1>; | |
| 1483 | ranges; | |
| 1484 | status = "disabled"; | |
| 1485 | ||
| a64d0ece | 1486 | usbhost_dwc3: dwc3@15a00000 { |
| 5f04c4cf CC |
1487 | compatible = "snps,dwc3"; |
| 1488 | reg = <0x15a00000 0x10000>; | |
| cebef6be | 1489 | interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>; |
| 5f04c4cf CC |
1490 | phys = <&usbhost30_phy 0>, <&usbhost30_phy 1>; |
| 1491 | phy-names = "usb2-phy", "usb3-phy"; | |
| 1492 | }; | |
| 1493 | }; | |
| 1494 | ||
| 1495 | mshc_0: mshc@15540000 { | |
| 1496 | compatible = "samsung,exynos7-dw-mshc-smu"; | |
| cebef6be | 1497 | interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; |
| 5f04c4cf CC |
1498 | #address-cells = <1>; |
| 1499 | #size-cells = <0>; | |
| 1500 | reg = <0x15540000 0x2000>; | |
| 1501 | clocks = <&cmu_fsys CLK_ACLK_MMC0>, | |
| 1502 | <&cmu_fsys CLK_SCLK_MMC0>; | |
| 1503 | clock-names = "biu", "ciu"; | |
| 1504 | fifo-depth = <0x40>; | |
| 1505 | status = "disabled"; | |
| 1506 | }; | |
| 1507 | ||
| 1508 | mshc_1: mshc@15550000 { | |
| 1509 | compatible = "samsung,exynos7-dw-mshc-smu"; | |
| cebef6be | 1510 | interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; |
| 5f04c4cf CC |
1511 | #address-cells = <1>; |
| 1512 | #size-cells = <0>; | |
| 1513 | reg = <0x15550000 0x2000>; | |
| 1514 | clocks = <&cmu_fsys CLK_ACLK_MMC1>, | |
| 1515 | <&cmu_fsys CLK_SCLK_MMC1>; | |
| 1516 | clock-names = "biu", "ciu"; | |
| 1517 | fifo-depth = <0x40>; | |
| 1518 | status = "disabled"; | |
| 1519 | }; | |
| 1520 | ||
| 1521 | mshc_2: mshc@15560000 { | |
| 1522 | compatible = "samsung,exynos7-dw-mshc-smu"; | |
| cebef6be | 1523 | interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; |
| 5f04c4cf CC |
1524 | #address-cells = <1>; |
| 1525 | #size-cells = <0>; | |
| 1526 | reg = <0x15560000 0x2000>; | |
| 1527 | clocks = <&cmu_fsys CLK_ACLK_MMC2>, | |
| 1528 | <&cmu_fsys CLK_SCLK_MMC2>; | |
| 1529 | clock-names = "biu", "ciu"; | |
| 1530 | fifo-depth = <0x40>; | |
| 1531 | status = "disabled"; | |
| 1532 | }; | |
| 1533 | ||
| 1534 | amba { | |
| 64cbff44 | 1535 | compatible = "simple-bus"; |
| 5f04c4cf CC |
1536 | #address-cells = <1>; |
| 1537 | #size-cells = <1>; | |
| 1538 | ranges; | |
| 1539 | ||
| 1540 | pdma0: pdma@15610000 { | |
| 1541 | compatible = "arm,pl330", "arm,primecell"; | |
| 1542 | reg = <0x15610000 0x1000>; | |
| cebef6be | 1543 | interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>; |
| 5f04c4cf CC |
1544 | clocks = <&cmu_fsys CLK_PDMA0>; |
| 1545 | clock-names = "apb_pclk"; | |
| 1546 | #dma-cells = <1>; | |
| 1547 | #dma-channels = <8>; | |
| 1548 | #dma-requests = <32>; | |
| 1549 | }; | |
| 1550 | ||
| 1551 | pdma1: pdma@15600000 { | |
| 1552 | compatible = "arm,pl330", "arm,primecell"; | |
| 1553 | reg = <0x15600000 0x1000>; | |
| cebef6be | 1554 | interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; |
| 5f04c4cf CC |
1555 | clocks = <&cmu_fsys CLK_PDMA1>; |
| 1556 | clock-names = "apb_pclk"; | |
| 1557 | #dma-cells = <1>; | |
| 1558 | #dma-channels = <8>; | |
| 1559 | #dma-requests = <32>; | |
| 1560 | }; | |
| 1561 | }; | |
| 1562 | ||
| 1563 | audio-subsystem@11400000 { | |
| 1564 | compatible = "samsung,exynos5433-lpass"; | |
| 1565 | reg = <0x11400000 0x100>, <0x11500000 0x08>; | |
| 7547162a MS |
1566 | clocks = <&cmu_aud CLK_PCLK_SFR0_CTRL>; |
| 1567 | clock-names = "sfr0_ctrl"; | |
| 5f04c4cf CC |
1568 | samsung,pmu-syscon = <&pmu_system_controller>; |
| 1569 | #address-cells = <1>; | |
| 1570 | #size-cells = <1>; | |
| 1571 | ranges; | |
| 1572 | ||
| 1573 | adma: adma@11420000 { | |
| 1574 | compatible = "arm,pl330", "arm,primecell"; | |
| 1575 | reg = <0x11420000 0x1000>; | |
| cebef6be | 1576 | interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; |
| 5f04c4cf CC |
1577 | clocks = <&cmu_aud CLK_ACLK_DMAC>; |
| 1578 | clock-names = "apb_pclk"; | |
| 1579 | #dma-cells = <1>; | |
| 1580 | #dma-channels = <8>; | |
| 1581 | #dma-requests = <32>; | |
| 1582 | }; | |
| 1583 | ||
| 1584 | i2s0: i2s0@11440000 { | |
| 1585 | compatible = "samsung,exynos7-i2s"; | |
| 1586 | reg = <0x11440000 0x100>; | |
| 1587 | dmas = <&adma 0 &adma 2>; | |
| 1588 | dma-names = "tx", "rx"; | |
| cebef6be | 1589 | interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; |
| 5f04c4cf CC |
1590 | #address-cells = <1>; |
| 1591 | #size-cells = <0>; | |
| 1592 | clocks = <&cmu_aud CLK_PCLK_AUD_I2S>, | |
| 1593 | <&cmu_aud CLK_SCLK_AUD_I2S>, | |
| 1594 | <&cmu_aud CLK_SCLK_I2S_BCLK>; | |
| 1595 | clock-names = "iis", "i2s_opclk0", "i2s_opclk1"; | |
| 1596 | pinctrl-names = "default"; | |
| 1597 | pinctrl-0 = <&i2s0_bus>; | |
| 1598 | status = "disabled"; | |
| 1599 | }; | |
| 1600 | ||
| 1601 | serial_3: serial@11460000 { | |
| 1602 | compatible = "samsung,exynos5433-uart"; | |
| 1603 | reg = <0x11460000 0x100>; | |
| cebef6be | 1604 | interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; |
| 5f04c4cf CC |
1605 | clocks = <&cmu_aud CLK_PCLK_AUD_UART>, |
| 1606 | <&cmu_aud CLK_SCLK_AUD_UART>; | |
| 1607 | clock-names = "uart", "clk_uart_baud0"; | |
| 1608 | pinctrl-names = "default"; | |
| 1609 | pinctrl-0 = <&uart_aud_bus>; | |
| 1610 | status = "disabled"; | |
| 1611 | }; | |
| 1612 | }; | |
| 1613 | }; | |
| 1614 | ||
| 1615 | timer: timer { | |
| 1616 | compatible = "arm,armv8-timer"; | |
| 1617 | interrupts = <GIC_PPI 13 | |
| 1618 | (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>, | |
| 1619 | <GIC_PPI 14 | |
| 1620 | (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>, | |
| 1621 | <GIC_PPI 11 | |
| 1622 | (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>, | |
| 1623 | <GIC_PPI 10 | |
| 1624 | (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; | |
| 1625 | }; | |
| 1626 | }; | |
| 1627 | ||
| ce23eb93 | 1628 | #include "exynos5433-bus.dtsi" |
| 5f04c4cf CC |
1629 | #include "exynos5433-pinctrl.dtsi" |
| 1630 | #include "exynos5433-tmu.dtsi" |