[linux-2.6-block.git] / arch / arm64 / boot / dts / broadcom / stingray / stingray.dtsi

/*
 *  BSD LICENSE
 *
 *  Copyright(c) 2015-2017 Broadcom.  All rights reserved.
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions
 *  are met:
 *
 *    * Redistributions of source code must retain the above copyright
 *      notice, this list of conditions and the following disclaimer.
 *    * Redistributions in binary form must reproduce the above copyright
 *      notice, this list of conditions and the following disclaimer in
 *      the documentation and/or other materials provided with the
 *      distribution.
 *    * Neither the name of Broadcom nor the names of its
 *      contributors may be used to endorse or promote products derived
 *      from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

#include <dt-bindings/interrupt-controller/arm-gic.h>

/ {
	compatible = "brcm,stingray";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a72";
			reg = <0x0 0x0>;
			enable-method = "psci";
			next-level-cache = <&CLUSTER0_L2>;
		};

		cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a72";
			reg = <0x0 0x1>;
			enable-method = "psci";
			next-level-cache = <&CLUSTER0_L2>;
		};

		cpu@100 {
			device_type = "cpu";
			compatible = "arm,cortex-a72";
			reg = <0x0 0x100>;
			enable-method = "psci";
			next-level-cache = <&CLUSTER1_L2>;
		};

		cpu@101 {
			device_type = "cpu";
			compatible = "arm,cortex-a72";
			reg = <0x0 0x101>;
			enable-method = "psci";
			next-level-cache = <&CLUSTER1_L2>;
		};

		cpu@200 {
			device_type = "cpu";
			compatible = "arm,cortex-a72";
			reg = <0x0 0x200>;
			enable-method = "psci";
			next-level-cache = <&CLUSTER2_L2>;
		};

		cpu@201 {
			device_type = "cpu";
			compatible = "arm,cortex-a72";
			reg = <0x0 0x201>;
			enable-method = "psci";
			next-level-cache = <&CLUSTER2_L2>;
		};

		cpu@300 {
			device_type = "cpu";
			compatible = "arm,cortex-a72";
			reg = <0x0 0x300>;
			enable-method = "psci";
			next-level-cache = <&CLUSTER3_L2>;
		};

		cpu@301 {
			device_type = "cpu";
			compatible = "arm,cortex-a72";
			reg = <0x0 0x301>;
			enable-method = "psci";
			next-level-cache = <&CLUSTER3_L2>;
		};

		CLUSTER0_L2: l2-cache@0 {
			compatible = "cache";
			cache-level = <2>;
			cache-unified;
		};

		CLUSTER1_L2: l2-cache@100 {
			compatible = "cache";
			cache-level = <2>;
			cache-unified;
		};

		CLUSTER2_L2: l2-cache@200 {
			compatible = "cache";
			cache-level = <2>;
			cache-unified;
		};

		CLUSTER3_L2: l2-cache@300 {
			compatible = "cache";
			cache-level = <2>;
			cache-unified;
		};
	};

	memory: memory@80000000 {
		device_type = "memory";
		reg = <0x00000000 0x80000000 0 0x40000000>;
	};

	psci {
		compatible = "arm,psci-0.2";
		method = "smc";
	};

	pmu {
		compatible = "arm,armv8-pmuv3";
		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
	};

	mhb: syscon@60401000 {
		compatible = "brcm,sr-mhb", "syscon";
		reg = <0 0x60401000 0 0x38c>;
	};

	scr {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x0 0x0 0x61000000 0x05000000>;

		ccn: ccn@0 {
			compatible = "arm,ccn-502";
			reg = <0x00000000 0x900000>;
			interrupts = <GIC_SPI 799 IRQ_TYPE_LEVEL_HIGH>;
		};

		gic: interrupt-controller@2c00000 {
			compatible = "arm,gic-v3";
			#interrupt-cells = <3>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;
			interrupt-controller;
			reg = <0x02c00000 0x010000>, /* GICD */
			      <0x02e00000 0x600000>; /* GICR */
			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;

			gic_its: msi-controller@63c20000 {
				compatible = "arm,gic-v3-its";
				msi-controller;
				#msi-cells = <1>;
				reg = <0x02c20000 0x10000>;
			};
		};

		smmu: iommu@3000000 {
			compatible = "arm,mmu-500";
			reg = <0x03000000 0x80000>;
			#global-interrupts = <1>;
			interrupts = <GIC_SPI 704 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 716 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 717 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 718 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 719 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 720 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 721 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 722 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 723 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 724 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 725 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 726 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 727 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 728 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 729 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 730 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 731 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 732 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 733 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 734 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 735 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 736 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 737 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 738 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 739 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 740 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 741 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 742 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 743 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 744 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 745 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 746 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 747 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 748 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 749 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 750 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 751 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 752 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 753 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 754 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 755 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 756 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 757 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 758 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 759 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 760 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 761 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 762 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 763 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 764 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 765 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 766 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 767 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 768 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 769 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 770 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 771 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 772 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 773 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH>;
			#iommu-cells = <2>;
		};
	};

	crmu: crmu {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x0 0x0 0x66400000 0x100000>;

		#include "stingray-clock.dtsi"

		otp: otp@1c400 {
			compatible = "brcm,ocotp-v2";
			reg = <0x0001c400 0x68>;
			brcm,ocotp-size = <2048>;
			status = "okay";
		};

		cdru: syscon@1d000 {
			compatible = "brcm,sr-cdru", "syscon";
			reg = <0x0001d000 0x400>;
		};

		gpio_crmu: gpio@24800 {
			compatible = "brcm,iproc-gpio";
			reg = <0x00024800 0x4c>;
			ngpios = <6>;
			#gpio-cells = <2>;
			gpio-controller;
		};
	};

	#include "stingray-fs4.dtsi"
	#include "stingray-pcie.dtsi"
	#include "stingray-usb.dtsi"

	hsls {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x0 0x0 0x68900000 0x17700000>;

		#include "stingray-pinctrl.dtsi"

		mdio_mux_iproc: mdio-mux@20000 {
			compatible = "brcm,mdio-mux-iproc";
			reg = <0x00020000 0x250>;
			#address-cells = <1>;
			#size-cells = <0>;

			mdio@0 { /* PCIe serdes */
				reg = <0x0>;
				#address-cells = <1>;
				#size-cells = <0>;
			};

			mdio@3 { /* USB */
				reg = <0x3>;
				#address-cells = <1>;
				#size-cells = <0>;
			};

			mdio@10 { /* RGMII */
				reg = <0x10>;
				#address-cells = <1>;
				#size-cells = <0>;
			};
		};

		pwm: pwm@10000 {
			compatible = "brcm,iproc-pwm";
			reg = <0x00010000 0x1000>;
			clocks = <&crmu_ref25m>;
			#pwm-cells = <3>;
			status = "disabled";
		};

		timer0: timer@30000 {
			compatible = "arm,sp804", "arm,primecell";
			reg = <0x00030000 0x1000>;
			interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&hsls_25m_div2_clk>,
				 <&hsls_25m_div2_clk>,
				 <&hsls_div4_clk>;
			clock-names = "timer1", "timer2", "apb_pclk";
			status = "disabled";
		};

		timer1: timer@40000 {
			compatible = "arm,sp804", "arm,primecell";
			reg = <0x00040000 0x1000>;
			interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&hsls_25m_div2_clk>,
				 <&hsls_25m_div2_clk>,
				 <&hsls_div4_clk>;
			clock-names = "timer1", "timer2", "apb_pclk";
		};

		timer2: timer@50000 {
			compatible = "arm,sp804", "arm,primecell";
			reg = <0x00050000 0x1000>;
			interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&hsls_25m_div2_clk>,
				 <&hsls_25m_div2_clk>,
				 <&hsls_div4_clk>;
			clock-names = "timer1", "timer2", "apb_pclk";
			status = "disabled";
		};

		timer3: timer@60000 {
			compatible = "arm,sp804", "arm,primecell";
			reg = <0x00060000 0x1000>;
			interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&hsls_25m_div2_clk>,
				 <&hsls_25m_div2_clk>,
				 <&hsls_div4_clk>;
			clock-names = "timer1", "timer2", "apb_pclk";
			status = "disabled";
		};

		timer4: timer@70000 {
			compatible = "arm,sp804", "arm,primecell";
			reg = <0x00070000 0x1000>;
			interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&hsls_25m_div2_clk>,
				 <&hsls_25m_div2_clk>,
				 <&hsls_div4_clk>;
			clock-names = "timer1", "timer2", "apb_pclk";
			status = "disabled";
		};

		timer5: timer@80000 {
			compatible = "arm,sp804", "arm,primecell";
			reg = <0x00080000 0x1000>;
			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&hsls_25m_div2_clk>,
				 <&hsls_25m_div2_clk>,
				 <&hsls_div4_clk>;
			clock-names = "timer1", "timer2", "apb_pclk";
			status = "disabled";
		};

		timer6: timer@90000 {
			compatible = "arm,sp804", "arm,primecell";
			reg = <0x00090000 0x1000>;
			interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&hsls_25m_div2_clk>,
				 <&hsls_25m_div2_clk>,
				 <&hsls_div4_clk>;
			clock-names = "timer1", "timer2", "apb_pclk";
			status = "disabled";
		};

		timer7: timer@a0000 {
			compatible = "arm,sp804", "arm,primecell";
			reg = <0x000a0000 0x1000>;
			interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&hsls_25m_div2_clk>,
				 <&hsls_25m_div2_clk>,
				 <&hsls_div4_clk>;
			clock-names = "timer1", "timer2", "apb_pclk";
			status = "disabled";
		};

		i2c0: i2c@b0000 {
			compatible = "brcm,iproc-i2c";
			reg = <0x000b0000 0x100>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
			clock-frequency = <100000>;
			status = "disabled";
		};

		wdt0: watchdog@c0000 {
			compatible = "arm,sp805", "arm,primecell";
			reg = <0x000c0000 0x1000>;
			interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&hsls_25m_div2_clk>, <&hsls_div4_clk>;
			clock-names = "wdog_clk", "apb_pclk";
			timeout-sec = <60>;
		};

		gpio_hsls: gpio@d0000 {
			compatible = "brcm,iproc-gpio";
			reg = <0x000d0000 0x864>;
			ngpios = <151>;
			#gpio-cells = <2>;
			gpio-controller;
			interrupt-controller;
			#interrupt-cells = <2>;
			interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
			gpio-ranges = <&pinmux 0 0 16>,
					<&pinmux 16 71 2>,
					<&pinmux 18 131 8>,
					<&pinmux 26 83 6>,
					<&pinmux 32 123 4>,
					<&pinmux 36 43 24>,
					<&pinmux 60 89 2>,
					<&pinmux 62 73 4>,
					<&pinmux 66 95 28>,
					<&pinmux 94 127 4>,
					<&pinmux 98 139 10>,
					<&pinmux 108 16 27>,
					<&pinmux 135 77 6>,
					<&pinmux 141 67 4>,
					<&pinmux 145 149 6>;
		};

		i2c1: i2c@e0000 {
			compatible = "brcm,iproc-i2c";
			reg = <0x000e0000 0x100>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
			clock-frequency = <100000>;
			status = "disabled";
		};

		uart0: serial@100000 {
			compatible = "snps,dw-apb-uart";
			reg = <0x00100000 0x1000>;
			reg-shift = <2>;
			clock-frequency = <25000000>;
			interrupt-parent = <&gic>;
			interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
		};

		uart1: serial@110000 {
			compatible = "snps,dw-apb-uart";
			reg = <0x00110000 0x1000>;
			reg-shift = <2>;
			clock-frequency = <25000000>;
			interrupt-parent = <&gic>;
			interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
		};

		uart2: serial@120000 {
			compatible = "snps,dw-apb-uart";
			reg = <0x00120000 0x1000>;
			reg-shift = <2>;
			clock-frequency = <25000000>;
			interrupt-parent = <&gic>;
			interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
		};

		uart3: serial@130000 {
			compatible = "snps,dw-apb-uart";
			reg = <0x00130000 0x1000>;
			reg-shift = <2>;
			clock-frequency = <25000000>;
			interrupt-parent = <&gic>;
			interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
		};

		ssp0: spi@180000 {
			compatible = "arm,pl022", "arm,primecell";
			reg = <0x00180000 0x1000>;
			interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&hsls_div2_clk>, <&hsls_div2_clk>;
			clock-names = "sspclk", "apb_pclk";
			num-cs = <1>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		ssp1: spi@190000 {
			compatible = "arm,pl022", "arm,primecell";
			reg = <0x00190000 0x1000>;
			interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&hsls_div2_clk>, <&hsls_div2_clk>;
			clock-names = "sspclk", "apb_pclk";
			num-cs = <1>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		hwrng: hwrng@220000 {
			compatible = "brcm,iproc-rng200";
			reg = <0x00220000 0x28>;
		};

		dma0: dma-controller@310000 {
			compatible = "arm,pl330", "arm,primecell";
			reg = <0x00310000 0x1000>;
			interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
			#dma-cells = <1>;
			clocks = <&hsls_div2_clk>;
			clock-names = "apb_pclk";
			iommus = <&smmu 0x6000 0x0000>;
		};

		enet: ethernet@340000 {
			compatible = "brcm,amac";
			reg = <0x00340000 0x1000>;
			reg-names = "amac_base";
			dma-coherent;
			interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
		};

		nand: nand@360000 {
			compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1";
			reg = <0x00360000 0x600>,
			      <0x0050a408 0x600>,
			      <0x00360f00 0x20>;
			reg-names = "nand", "iproc-idm", "iproc-ext";
			interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <1>;
			#size-cells = <0>;
			brcm,nand-has-wp;
			status = "disabled";
		};

		sdio0: sdhci@3f1000 {
			compatible = "brcm,sdhci-iproc";
			reg = <0x003f1000 0x100>;
			interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
			bus-width = <8>;
			clocks = <&sdio0_clk>;
			iommus = <&smmu 0x6002 0x0000>;
			status = "disabled";
		};

		sdio1: sdhci@3f2000 {
			compatible = "brcm,sdhci-iproc";
			reg = <0x003f2000 0x100>;
			interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
			bus-width = <8>;
			clocks = <&sdio1_clk>;
			iommus = <&smmu 0x6003 0x0000>;
			status = "disabled";
		};
	};

	tmons {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x0 0x0 0x8f100000 0x100>;

		tmon: tmon@0 {
			compatible = "brcm,sr-thermal";
			reg = <0x0 0x40>;
			brcm,tmon-mask = <0x3f>;
			#thermal-sensor-cells = <1>;
		};
	};

	thermal-zones {
		ihost0_thermal: ihost0-thermal {
			polling-delay-passive = <0>;
			polling-delay = <1000>;
			thermal-sensors = <&tmon 0>;
			trips {
				cpu-crit {
					temperature = <105000>;
					hysteresis = <0>;
					type = "critical";
				};
			};
		};
		ihost1_thermal: ihost1-thermal {
			polling-delay-passive = <0>;
			polling-delay = <1000>;
			thermal-sensors = <&tmon 1>;
			trips {
				cpu-crit {
					temperature = <105000>;
					hysteresis = <0>;
					type = "critical";
				};
			};
		};
		ihost2_thermal: ihost2-thermal {
			polling-delay-passive = <0>;
			polling-delay = <1000>;
			thermal-sensors = <&tmon 2>;
			trips {
				cpu-crit {
					temperature = <105000>;
					hysteresis = <0>;
					type = "critical";
				};
			};
		};
		ihost3_thermal: ihost3-thermal {
			polling-delay-passive = <0>;
			polling-delay = <1000>;
			thermal-sensors = <&tmon 3>;
			trips {
				cpu-crit {
					temperature = <105000>;
					hysteresis = <0>;
					type = "critical";
				};
			};
		};
		crmu_thermal: crmu-thermal {
			polling-delay-passive = <0>;
			polling-delay = <1000>;
			thermal-sensors = <&tmon 4>;
			trips {
				cpu-crit {
					temperature = <105000>;
					hysteresis = <0>;
					type = "critical";
				};
			};
		};
		nitro_thermal: nitro-thermal {
			polling-delay-passive = <0>;
			polling-delay = <1000>;
			thermal-sensors = <&tmon 5>;
			trips {
				cpu-crit {
					temperature = <105000>;
					hysteresis = <0>;
					type = "critical";
				};
			};
		};
	};

	nic-hsls {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x0 0x0  0x0 0x7fffffff>;

		nic_i2c0: i2c@60826100 {
			compatible = "brcm,iproc-nic-i2c";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x60826100 0x100>,
			      <0x60e00408 0x1000>;
			brcm,ape-hsls-addr-mask = <0x03400000>;
			clock-frequency = <100000>;
			status = "disabled";
		};
	};
};
Commit	Line	Data
d4b4aba6 AP	1	/*
	2	* BSD LICENSE
	3	*
	4	* Copyright(c) 2015-2017 Broadcom. All rights reserved.
	5	*
	6	* Redistribution and use in source and binary forms, with or without
	7	* modification, are permitted provided that the following conditions
	8	* are met:
	9	*
	10	* * Redistributions of source code must retain the above copyright
	11	* notice, this list of conditions and the following disclaimer.
	12	* * Redistributions in binary form must reproduce the above copyright
	13	* notice, this list of conditions and the following disclaimer in
	14	* the documentation and/or other materials provided with the
	15	* distribution.
	16	* * Neither the name of Broadcom nor the names of its
	17	* contributors may be used to endorse or promote products derived
	18	* from this software without specific prior written permission.
	19	*
	20	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
	21	* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
	22	* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
	23	* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
	24	* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
	25	* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
	26	* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
	27	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
	28	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
	29	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
	30	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	31	*/
	32
	33	#include <dt-bindings/interrupt-controller/arm-gic.h>
	34
	35	/ {
	36	compatible = "brcm,stingray";
	37	interrupt-parent = <&gic>;
	38	#address-cells = <2>;
	39	#size-cells = <2>;
	40
	41	cpus {
	42	#address-cells = <2>;
	43	#size-cells = <0>;
	44
d8bcaabe	45	cpu@0 {
d4b4aba6	46	device_type = "cpu";
31af04cd	47	compatible = "arm,cortex-a72";
d4b4aba6 AP	48	reg = <0x0 0x0>;
	49	enable-method = "psci";
	50	next-level-cache = <&CLUSTER0_L2>;
	51	};
	52
d8bcaabe	53	cpu@1 {
d4b4aba6	54	device_type = "cpu";
31af04cd	55	compatible = "arm,cortex-a72";
d4b4aba6 AP	56	reg = <0x0 0x1>;
	57	enable-method = "psci";
	58	next-level-cache = <&CLUSTER0_L2>;
	59	};
	60
	61	cpu@100 {
	62	device_type = "cpu";
31af04cd	63	compatible = "arm,cortex-a72";
d4b4aba6 AP	64	reg = <0x0 0x100>;
	65	enable-method = "psci";
	66	next-level-cache = <&CLUSTER1_L2>;
	67	};
	68
	69	cpu@101 {
	70	device_type = "cpu";
31af04cd	71	compatible = "arm,cortex-a72";
d4b4aba6 AP	72	reg = <0x0 0x101>;
	73	enable-method = "psci";
	74	next-level-cache = <&CLUSTER1_L2>;
	75	};
	76
	77	cpu@200 {
	78	device_type = "cpu";
31af04cd	79	compatible = "arm,cortex-a72";
d4b4aba6 AP	80	reg = <0x0 0x200>;
	81	enable-method = "psci";
	82	next-level-cache = <&CLUSTER2_L2>;
	83	};
	84
	85	cpu@201 {
	86	device_type = "cpu";
31af04cd	87	compatible = "arm,cortex-a72";
d4b4aba6 AP	88	reg = <0x0 0x201>;
	89	enable-method = "psci";
	90	next-level-cache = <&CLUSTER2_L2>;
	91	};
	92
	93	cpu@300 {
	94	device_type = "cpu";
31af04cd	95	compatible = "arm,cortex-a72";
d4b4aba6 AP	96	reg = <0x0 0x300>;
	97	enable-method = "psci";
	98	next-level-cache = <&CLUSTER3_L2>;
	99	};
	100
	101	cpu@301 {
	102	device_type = "cpu";
31af04cd	103	compatible = "arm,cortex-a72";
d4b4aba6 AP	104	reg = <0x0 0x301>;
	105	enable-method = "psci";
	106	next-level-cache = <&CLUSTER3_L2>;
	107	};
	108
d8bcaabe	109	CLUSTER0_L2: l2-cache@0 {
d4b4aba6	110	compatible = "cache";
e567e58d	111	cache-level = <2>;
0709e55e	112	cache-unified;
d4b4aba6 AP	113	};
	114
	115	CLUSTER1_L2: l2-cache@100 {
	116	compatible = "cache";
e567e58d	117	cache-level = <2>;
0709e55e	118	cache-unified;
d4b4aba6 AP	119	};
	120
	121	CLUSTER2_L2: l2-cache@200 {
	122	compatible = "cache";
e567e58d	123	cache-level = <2>;
0709e55e	124	cache-unified;
d4b4aba6 AP	125	};
	126
	127	CLUSTER3_L2: l2-cache@300 {
	128	compatible = "cache";
e567e58d	129	cache-level = <2>;
0709e55e	130	cache-unified;
d4b4aba6 AP	131	};
	132	};
	133
	134	memory: memory@80000000 {
	135	device_type = "memory";
	136	reg = <0x00000000 0x80000000 0 0x40000000>;
	137	};
	138
	139	psci {
	140	compatible = "arm,psci-0.2";
	141	method = "smc";
	142	};
	143
	144	pmu {
	145	compatible = "arm,armv8-pmuv3";
	146	interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
	147	};
	148
	149	timer {
	150	compatible = "arm,armv8-timer";
	151	interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
	152	<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
	153	<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
	154	<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
	155	};
	156
133de204 RJ	157	mhb: syscon@60401000 {
	158	compatible = "brcm,sr-mhb", "syscon";
	159	reg = <0 0x60401000 0 0x38c>;
	160	};
	161
d4b4aba6 AP	162	scr {
	163	compatible = "simple-bus";
	164	#address-cells = <1>;
	165	#size-cells = <1>;
	166	ranges = <0x0 0x0 0x61000000 0x05000000>;
	167
d8bcaabe	168	ccn: ccn@0 {
5ace3533 VM	169	compatible = "arm,ccn-502";
	170	reg = <0x00000000 0x900000>;
	171	interrupts = <GIC_SPI 799 IRQ_TYPE_LEVEL_HIGH>;
	172	};
	173
d8bcaabe	174	gic: interrupt-controller@2c00000 {
d4b4aba6 AP	175	compatible = "arm,gic-v3";
	176	#interrupt-cells = <3>;
	177	#address-cells = <1>;
	178	#size-cells = <1>;
	179	ranges;
	180	interrupt-controller;
	181	reg = <0x02c00000 0x010000>, /* GICD */
	182	<0x02e00000 0x600000>; /* GICR */
	183	interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
	184
47600f84	185	gic_its: msi-controller@63c20000 {
d4b4aba6 AP	186	compatible = "arm,gic-v3-its";
	187	msi-controller;
	188	#msi-cells = <1>;
	189	reg = <0x02c20000 0x10000>;
	190	};
	191	};
	192
b76e1186	193	smmu: iommu@3000000 {
d4b4aba6 AP	194	compatible = "arm,mmu-500";
	195	reg = <0x03000000 0x80000>;
	196	#global-interrupts = <1>;
	197	interrupts = <GIC_SPI 704 IRQ_TYPE_LEVEL_HIGH>,
	198	<GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>,
	199	<GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>,
	200	<GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>,
	201	<GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>,
	202	<GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>,
	203	<GIC_SPI 716 IRQ_TYPE_LEVEL_HIGH>,
	204	<GIC_SPI 717 IRQ_TYPE_LEVEL_HIGH>,
	205	<GIC_SPI 718 IRQ_TYPE_LEVEL_HIGH>,
	206	<GIC_SPI 719 IRQ_TYPE_LEVEL_HIGH>,
	207	<GIC_SPI 720 IRQ_TYPE_LEVEL_HIGH>,
	208	<GIC_SPI 721 IRQ_TYPE_LEVEL_HIGH>,
	209	<GIC_SPI 722 IRQ_TYPE_LEVEL_HIGH>,
	210	<GIC_SPI 723 IRQ_TYPE_LEVEL_HIGH>,
	211	<GIC_SPI 724 IRQ_TYPE_LEVEL_HIGH>,
	212	<GIC_SPI 725 IRQ_TYPE_LEVEL_HIGH>,
	213	<GIC_SPI 726 IRQ_TYPE_LEVEL_HIGH>,
	214	<GIC_SPI 727 IRQ_TYPE_LEVEL_HIGH>,
	215	<GIC_SPI 728 IRQ_TYPE_LEVEL_HIGH>,
	216	<GIC_SPI 729 IRQ_TYPE_LEVEL_HIGH>,
	217	<GIC_SPI 730 IRQ_TYPE_LEVEL_HIGH>,
	218	<GIC_SPI 731 IRQ_TYPE_LEVEL_HIGH>,
	219	<GIC_SPI 732 IRQ_TYPE_LEVEL_HIGH>,
	220	<GIC_SPI 733 IRQ_TYPE_LEVEL_HIGH>,
	221	<GIC_SPI 734 IRQ_TYPE_LEVEL_HIGH>,
	222	<GIC_SPI 735 IRQ_TYPE_LEVEL_HIGH>,
	223	<GIC_SPI 736 IRQ_TYPE_LEVEL_HIGH>,
	224	<GIC_SPI 737 IRQ_TYPE_LEVEL_HIGH>,
	225	<GIC_SPI 738 IRQ_TYPE_LEVEL_HIGH>,
	226	<GIC_SPI 739 IRQ_TYPE_LEVEL_HIGH>,
	227	<GIC_SPI 740 IRQ_TYPE_LEVEL_HIGH>,
	228	<GIC_SPI 741 IRQ_TYPE_LEVEL_HIGH>,
	229	<GIC_SPI 742 IRQ_TYPE_LEVEL_HIGH>,
	230	<GIC_SPI 743 IRQ_TYPE_LEVEL_HIGH>,
	231	<GIC_SPI 744 IRQ_TYPE_LEVEL_HIGH>,
	232	<GIC_SPI 745 IRQ_TYPE_LEVEL_HIGH>,
	233	<GIC_SPI 746 IRQ_TYPE_LEVEL_HIGH>,
	234	<GIC_SPI 747 IRQ_TYPE_LEVEL_HIGH>,
	235	<GIC_SPI 748 IRQ_TYPE_LEVEL_HIGH>,
	236	<GIC_SPI 749 IRQ_TYPE_LEVEL_HIGH>,
	237	<GIC_SPI 750 IRQ_TYPE_LEVEL_HIGH>,
	238	<GIC_SPI 751 IRQ_TYPE_LEVEL_HIGH>,
	239	<GIC_SPI 752 IRQ_TYPE_LEVEL_HIGH>,
	240	<GIC_SPI 753 IRQ_TYPE_LEVEL_HIGH>,
	241	<GIC_SPI 754 IRQ_TYPE_LEVEL_HIGH>,
	242	<GIC_SPI 755 IRQ_TYPE_LEVEL_HIGH>,
	243	<GIC_SPI 756 IRQ_TYPE_LEVEL_HIGH>,
	244	<GIC_SPI 757 IRQ_TYPE_LEVEL_HIGH>,
	245	<GIC_SPI 758 IRQ_TYPE_LEVEL_HIGH>,
	246	<GIC_SPI 759 IRQ_TYPE_LEVEL_HIGH>,
	247	<GIC_SPI 760 IRQ_TYPE_LEVEL_HIGH>,
	248	<GIC_SPI 761 IRQ_TYPE_LEVEL_HIGH>,
	249	<GIC_SPI 762 IRQ_TYPE_LEVEL_HIGH>,
	250	<GIC_SPI 763 IRQ_TYPE_LEVEL_HIGH>,
	251	<GIC_SPI 764 IRQ_TYPE_LEVEL_HIGH>,
	252	<GIC_SPI 765 IRQ_TYPE_LEVEL_HIGH>,
	253	<GIC_SPI 766 IRQ_TYPE_LEVEL_HIGH>,
	254	<GIC_SPI 767 IRQ_TYPE_LEVEL_HIGH>,
	255	<GIC_SPI 768 IRQ_TYPE_LEVEL_HIGH>,
	256	<GIC_SPI 769 IRQ_TYPE_LEVEL_HIGH>,
	257	<GIC_SPI 770 IRQ_TYPE_LEVEL_HIGH>,
258	<GIC_SPI 771 IRQ_TYPE_LEVEL_HIGH>,
259	<GIC_SPI 772 IRQ_TYPE_LEVEL_HIGH>,
260	<GIC_SPI 773 IRQ_TYPE_LEVEL_HIGH>,
261	<GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH>;
262	#iommu-cells = <2>;
263	};
264	};
265
73da8f97 ST	266	crmu: crmu {
	267	compatible = "simple-bus";
	268	#address-cells = <1>;
	269	#size-cells = <1>;
	270	ranges = <0x0 0x0 0x66400000 0x100000>;
	271
	272	#include "stingray-clock.dtsi"
2fa9e9e2	273
8dd970a2 SB	274	otp: otp@1c400 {
	275	compatible = "brcm,ocotp-v2";
	276	reg = <0x0001c400 0x68>;
	277	brcm,ocotp-size = <2048>;
	278	status = "okay";
	279	};
	280
133de204 RJ	281	cdru: syscon@1d000 {
	282	compatible = "brcm,sr-cdru", "syscon";
	283	reg = <0x0001d000 0x400>;
	284	};
	285
d8bcaabe	286	gpio_crmu: gpio@24800 {
2fa9e9e2 PK	287	compatible = "brcm,iproc-gpio";
	288	reg = <0x00024800 0x4c>;
	289	ngpios = <6>;
	290	#gpio-cells = <2>;
	291	gpio-controller;
	292	};
73da8f97 ST	293	};
73da8f97 ST	294
c6e95598	295	#include "stingray-fs4.dtsi"
133de204	296	#include "stingray-pcie.dtsi"
ad77d3db	297	#include "stingray-usb.dtsi"
344a2e51	298
d4b4aba6 AP	299	hsls {
	300	compatible = "simple-bus";
	301	#address-cells = <1>;
	302	#size-cells = <1>;
	303	ranges = <0x0 0x0 0x68900000 0x17700000>;
	304
8aa428cc PK	305	#include "stingray-pinctrl.dtsi"
8aa428cc PK	306
18b872d8	307	mdio_mux_iproc: mdio-mux@20000 {
fd898f75	308	compatible = "brcm,mdio-mux-iproc";
18b872d8	309	reg = <0x00020000 0x250>;
fd898f75 SM	310	#address-cells = <1>;
	311	#size-cells = <0>;
	312
	313	mdio@0 { /* PCIe serdes */
	314	reg = <0x0>;
	315	#address-cells = <1>;
	316	#size-cells = <0>;
	317	};
	318
fd898f75 SM	319	mdio@3 { /* USB */
	320	reg = <0x3>;
	321	#address-cells = <1>;
	322	#size-cells = <0>;
	323	};
	324
	325	mdio@10 { /* RGMII */
	326	reg = <0x10>;
	327	#address-cells = <1>;
	328	#size-cells = <0>;
	329	};
	330	};
	331
d8bcaabe	332	pwm: pwm@10000 {
552df263 SM	333	compatible = "brcm,iproc-pwm";
	334	reg = <0x00010000 0x1000>;
	335	clocks = <&crmu_ref25m>;
	336	#pwm-cells = <3>;
	337	status = "disabled";
	338	};
	339
d8bcaabe	340	timer0: timer@30000 {
567b3b0a AP	341	compatible = "arm,sp804", "arm,primecell";
	342	reg = <0x00030000 0x1000>;
	343	interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
	344	clocks = <&hsls_25m_div2_clk>,
	345	<&hsls_25m_div2_clk>,
	346	<&hsls_div4_clk>;
	347	clock-names = "timer1", "timer2", "apb_pclk";
	348	status = "disabled";
	349	};
	350
d8bcaabe	351	timer1: timer@40000 {
567b3b0a AP	352	compatible = "arm,sp804", "arm,primecell";
	353	reg = <0x00040000 0x1000>;
	354	interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
	355	clocks = <&hsls_25m_div2_clk>,
	356	<&hsls_25m_div2_clk>,
	357	<&hsls_div4_clk>;
	358	clock-names = "timer1", "timer2", "apb_pclk";
	359	};
	360
d8bcaabe	361	timer2: timer@50000 {
567b3b0a AP	362	compatible = "arm,sp804", "arm,primecell";
	363	reg = <0x00050000 0x1000>;
	364	interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>;
	365	clocks = <&hsls_25m_div2_clk>,
	366	<&hsls_25m_div2_clk>,
	367	<&hsls_div4_clk>;
	368	clock-names = "timer1", "timer2", "apb_pclk";
	369	status = "disabled";
	370	};
	371
d8bcaabe	372	timer3: timer@60000 {
567b3b0a AP	373	compatible = "arm,sp804", "arm,primecell";
	374	reg = <0x00060000 0x1000>;
	375	interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
	376	clocks = <&hsls_25m_div2_clk>,
	377	<&hsls_25m_div2_clk>,
	378	<&hsls_div4_clk>;
	379	clock-names = "timer1", "timer2", "apb_pclk";
	380	status = "disabled";
	381	};
	382
d8bcaabe	383	timer4: timer@70000 {
567b3b0a AP	384	compatible = "arm,sp804", "arm,primecell";
	385	reg = <0x00070000 0x1000>;
	386	interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
	387	clocks = <&hsls_25m_div2_clk>,
	388	<&hsls_25m_div2_clk>,
	389	<&hsls_div4_clk>;
	390	clock-names = "timer1", "timer2", "apb_pclk";
	391	status = "disabled";
	392	};
	393
d8bcaabe	394	timer5: timer@80000 {
567b3b0a AP	395	compatible = "arm,sp804", "arm,primecell";
	396	reg = <0x00080000 0x1000>;
	397	interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
	398	clocks = <&hsls_25m_div2_clk>,
	399	<&hsls_25m_div2_clk>,
	400	<&hsls_div4_clk>;
	401	clock-names = "timer1", "timer2", "apb_pclk";
	402	status = "disabled";
	403	};
	404
d8bcaabe	405	timer6: timer@90000 {
567b3b0a AP	406	compatible = "arm,sp804", "arm,primecell";
	407	reg = <0x00090000 0x1000>;
	408	interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
	409	clocks = <&hsls_25m_div2_clk>,
	410	<&hsls_25m_div2_clk>,
	411	<&hsls_div4_clk>;
	412	clock-names = "timer1", "timer2", "apb_pclk";
	413	status = "disabled";
	414	};
	415
d8bcaabe	416	timer7: timer@a0000 {
567b3b0a AP	417	compatible = "arm,sp804", "arm,primecell";
	418	reg = <0x000a0000 0x1000>;
	419	interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>;
	420	clocks = <&hsls_25m_div2_clk>,
	421	<&hsls_25m_div2_clk>,
	422	<&hsls_div4_clk>;
	423	clock-names = "timer1", "timer2", "apb_pclk";
	424	status = "disabled";
	425	};
	426
d8bcaabe	427	i2c0: i2c@b0000 {
1256ea18 OP	428	compatible = "brcm,iproc-i2c";
	429	reg = <0x000b0000 0x100>;
	430	#address-cells = <1>;
	431	#size-cells = <0>;
75af23c4	432	interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
1256ea18 OP	433	clock-frequency = <100000>;
	434	status = "disabled";
	435	};
	436
d8bcaabe	437	wdt0: watchdog@c0000 {
0dc454ee AP	438	compatible = "arm,sp805", "arm,primecell";
	439	reg = <0x000c0000 0x1000>;
	440	interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
	441	clocks = <&hsls_25m_div2_clk>, <&hsls_div4_clk>;
6534dfbb	442	clock-names = "wdog_clk", "apb_pclk";
71e962a0	443	timeout-sec = <60>;
0dc454ee AP	444	};
0dc454ee AP	445
d8bcaabe	446	gpio_hsls: gpio@d0000 {
2fa9e9e2 PK	447	compatible = "brcm,iproc-gpio";
	448	reg = <0x000d0000 0x864>;
	449	ngpios = <151>;
	450	#gpio-cells = <2>;
	451	gpio-controller;
	452	interrupt-controller;
91adecf9	453	#interrupt-cells = <2>;
2fa9e9e2 PK	454	interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
	455	gpio-ranges = <&pinmux 0 0 16>,
	456	<&pinmux 16 71 2>,
	457	<&pinmux 18 131 8>,
	458	<&pinmux 26 83 6>,
	459	<&pinmux 32 123 4>,
	460	<&pinmux 36 43 24>,
	461	<&pinmux 60 89 2>,
	462	<&pinmux 62 73 4>,
	463	<&pinmux 66 95 28>,
	464	<&pinmux 94 127 4>,
	465	<&pinmux 98 139 10>,
	466	<&pinmux 108 16 27>,
	467	<&pinmux 135 77 6>,
	468	<&pinmux 141 67 4>,
965f6603	469	<&pinmux 145 149 6>;
2fa9e9e2 PK	470	};
2fa9e9e2 PK	471
d8bcaabe	472	i2c1: i2c@e0000 {
1256ea18 OP	473	compatible = "brcm,iproc-i2c";
	474	reg = <0x000e0000 0x100>;
	475	#address-cells = <1>;
	476	#size-cells = <0>;
75af23c4	477	interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
1256ea18 OP	478	clock-frequency = <100000>;
	479	status = "disabled";
	480	};
	481
cd49f71c	482	uart0: serial@100000 {
d4b4aba6 AP	483	compatible = "snps,dw-apb-uart";
	484	reg = <0x00100000 0x1000>;
	485	reg-shift = <2>;
	486	clock-frequency = <25000000>;
	487	interrupt-parent = <&gic>;
	488	interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
	489	status = "disabled";
	490	};
	491
cd49f71c	492	uart1: serial@110000 {
d4b4aba6 AP	493	compatible = "snps,dw-apb-uart";
	494	reg = <0x00110000 0x1000>;
	495	reg-shift = <2>;
	496	clock-frequency = <25000000>;
	497	interrupt-parent = <&gic>;
	498	interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
	499	status = "disabled";
	500	};
	501
cd49f71c	502	uart2: serial@120000 {
d4b4aba6 AP	503	compatible = "snps,dw-apb-uart";
	504	reg = <0x00120000 0x1000>;
	505	reg-shift = <2>;
	506	clock-frequency = <25000000>;
	507	interrupt-parent = <&gic>;
	508	interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
	509	status = "disabled";
	510	};
	511
cd49f71c	512	uart3: serial@130000 {
d4b4aba6 AP	513	compatible = "snps,dw-apb-uart";
	514	reg = <0x00130000 0x1000>;
	515	reg-shift = <2>;
	516	clock-frequency = <25000000>;
	517	interrupt-parent = <&gic>;
	518	interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
	519	status = "disabled";
	520	};
	521
7cdbe45d	522	ssp0: spi@180000 {
0dc454ee AP	523	compatible = "arm,pl022", "arm,primecell";
	524	reg = <0x00180000 0x1000>;
	525	interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
	526	clocks = <&hsls_div2_clk>, <&hsls_div2_clk>;
66435063	527	clock-names = "sspclk", "apb_pclk";
0dc454ee AP	528	num-cs = <1>;
	529	#address-cells = <1>;
	530	#size-cells = <0>;
	531	status = "disabled";
	532	};
	533
7cdbe45d	534	ssp1: spi@190000 {
0dc454ee AP	535	compatible = "arm,pl022", "arm,primecell";
	536	reg = <0x00190000 0x1000>;
	537	interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
	538	clocks = <&hsls_div2_clk>, <&hsls_div2_clk>;
66435063	539	clock-names = "sspclk", "apb_pclk";
0dc454ee AP	540	num-cs = <1>;
	541	#address-cells = <1>;
	542	#size-cells = <0>;
	543	status = "disabled";
	544	};
	545
d8bcaabe	546	hwrng: hwrng@220000 {
d4b4aba6 AP	547	compatible = "brcm,iproc-rng200";
	548	reg = <0x00220000 0x28>;
	549	};
0f67ae37	550
c210c1d8	551	dma0: dma-controller@310000 {
0dc454ee AP	552	compatible = "arm,pl330", "arm,primecell";
	553	reg = <0x00310000 0x1000>;
	554	interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>,
	555	<GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>,
	556	<GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>,
	557	<GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
	558	<GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
	559	<GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
	560	<GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
	561	<GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
	562	<GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
	563	#dma-cells = <1>;
0dc454ee AP	564	clocks = <&hsls_div2_clk>;
	565	clock-names = "apb_pclk";
	566	iommus = <&smmu 0x6000 0x0000>;
	567	};
	568
a3660e59	569	enet: ethernet@340000 {
80e2cbc1 AS	570	compatible = "brcm,amac";
	571	reg = <0x00340000 0x1000>;
	572	reg-names = "amac_base";
	573	dma-coherent;
	574	interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>;
b65b9477	575	status = "disabled";
80e2cbc1 AS	576	};
80e2cbc1 AS	577
d8bcaabe	578	nand: nand@360000 {
0f67ae37 PK	579	compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1";
	580	reg = <0x00360000 0x600>,
	581	<0x0050a408 0x600>,
	582	<0x00360f00 0x20>;
	583	reg-names = "nand", "iproc-idm", "iproc-ext";
	584	interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
	585	#address-cells = <1>;
	586	#size-cells = <0>;
	587	brcm,nand-has-wp;
	588	status = "disabled";
	589	};
552df263	590
d8bcaabe	591	sdio0: sdhci@3f1000 {
552df263 SM	592	compatible = "brcm,sdhci-iproc";
	593	reg = <0x003f1000 0x100>;
	594	interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
	595	bus-width = <8>;
	596	clocks = <&sdio0_clk>;
	597	iommus = <&smmu 0x6002 0x0000>;
	598	status = "disabled";
	599	};
	600
d8bcaabe	601	sdio1: sdhci@3f2000 {
552df263 SM	602	compatible = "brcm,sdhci-iproc";
	603	reg = <0x003f2000 0x100>;
	604	interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
	605	bus-width = <8>;
	606	clocks = <&sdio1_clk>;
	607	iommus = <&smmu 0x6003 0x0000>;
	608	status = "disabled";
	609	};
d4b4aba6	610	};
aa78426d PK	611
	612	tmons {
	613	compatible = "simple-bus";
	614	#address-cells = <1>;
	615	#size-cells = <1>;
	616	ranges = <0x0 0x0 0x8f100000 0x100>;
	617
	618	tmon: tmon@0 {
	619	compatible = "brcm,sr-thermal";
	620	reg = <0x0 0x40>;
	621	brcm,tmon-mask = <0x3f>;
	622	#thermal-sensor-cells = <1>;
	623	};
	624	};
	625
	626	thermal-zones {
	627	ihost0_thermal: ihost0-thermal {
	628	polling-delay-passive = <0>;
	629	polling-delay = <1000>;
	630	thermal-sensors = <&tmon 0>;
	631	trips {
	632	cpu-crit {
	633	temperature = <105000>;
	634	hysteresis = <0>;
	635	type = "critical";
	636	};
	637	};
	638	};
	639	ihost1_thermal: ihost1-thermal {
	640	polling-delay-passive = <0>;
	641	polling-delay = <1000>;
	642	thermal-sensors = <&tmon 1>;
	643	trips {
	644	cpu-crit {
	645	temperature = <105000>;
	646	hysteresis = <0>;
	647	type = "critical";
	648	};
	649	};
	650	};
	651	ihost2_thermal: ihost2-thermal {
	652	polling-delay-passive = <0>;
	653	polling-delay = <1000>;
	654	thermal-sensors = <&tmon 2>;
	655	trips {
	656	cpu-crit {
	657	temperature = <105000>;
	658	hysteresis = <0>;
	659	type = "critical";
	660	};
	661	};
	662	};
	663	ihost3_thermal: ihost3-thermal {
	664	polling-delay-passive = <0>;
	665	polling-delay = <1000>;
	666	thermal-sensors = <&tmon 3>;
	667	trips {
	668	cpu-crit {
	669	temperature = <105000>;
	670	hysteresis = <0>;
	671	type = "critical";
	672	};
	673	};
	674	};
675	crmu_thermal: crmu-thermal {
676	polling-delay-passive = <0>;
677	polling-delay = <1000>;
678	thermal-sensors = <&tmon 4>;
679	trips {
680	cpu-crit {
681	temperature = <105000>;
682	hysteresis = <0>;
683	type = "critical";
684	};
685	};
686	};
687	nitro_thermal: nitro-thermal {
688	polling-delay-passive = <0>;
689	polling-delay = <1000>;
690	thermal-sensors = <&tmon 5>;
691	trips {
692	cpu-crit {
693	temperature = <105000>;
694	hysteresis = <0>;
695	type = "critical";
696	};
697	};
698	};
699	};
f8526c2d RK	700
	701	nic-hsls {
	702	compatible = "simple-bus";
	703	#address-cells = <1>;
	704	#size-cells = <1>;
	705	ranges = <0x0 0x0 0x0 0x7fffffff>;
	706
	707	nic_i2c0: i2c@60826100 {
	708	compatible = "brcm,iproc-nic-i2c";
	709	#address-cells = <1>;
	710	#size-cells = <0>;
	711	reg = <0x60826100 0x100>,
	712	<0x60e00408 0x1000>;
	713	brcm,ape-hsls-addr-mask = <0x03400000>;
	714	clock-frequency = <100000>;
	715	status = "disabled";
	716	};
	717	};
d4b4aba6	718	};