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6aad8bf9 RJ |
1 | /* |
2 | * BSD LICENSE | |
3 | * | |
59a5bede | 4 | * Copyright (c) 2015 Broadcom. All rights reserved. |
6aad8bf9 RJ |
5 | * |
6 | * Redistribution and use in source and binary forms, with or without | |
7 | * modification, are permitted provided that the following conditions | |
8 | * are met: | |
9 | * | |
10 | * * Redistributions of source code must retain the above copyright | |
11 | * notice, this list of conditions and the following disclaimer. | |
12 | * * Redistributions in binary form must reproduce the above copyright | |
13 | * notice, this list of conditions and the following disclaimer in | |
14 | * the documentation and/or other materials provided with the | |
15 | * distribution. | |
16 | * * Neither the name of Broadcom Corporation nor the names of its | |
17 | * contributors may be used to endorse or promote products derived | |
18 | * from this software without specific prior written permission. | |
19 | * | |
20 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS | |
21 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT | |
22 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR | |
23 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT | |
24 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, | |
25 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT | |
26 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, | |
27 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY | |
28 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
29 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | |
30 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
31 | */ | |
32 | ||
0cc878d6 JM |
33 | /memreserve/ 0x81000000 0x00200000; |
34 | ||
6aad8bf9 | 35 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
d8bd64c1 | 36 | #include <dt-bindings/clock/bcm-ns2.h> |
6aad8bf9 | 37 | |
6aad8bf9 RJ |
38 | / { |
39 | compatible = "brcm,ns2"; | |
40 | interrupt-parent = <&gic>; | |
41 | #address-cells = <2>; | |
42 | #size-cells = <2>; | |
43 | ||
44 | cpus { | |
45 | #address-cells = <2>; | |
46 | #size-cells = <0>; | |
47 | ||
5b31d875 | 48 | A57_0: cpu@0 { |
6aad8bf9 RJ |
49 | device_type = "cpu"; |
50 | compatible = "arm,cortex-a57", "arm,armv8"; | |
51 | reg = <0 0>; | |
a9abb475 | 52 | enable-method = "psci"; |
33a93aa4 | 53 | next-level-cache = <&CLUSTER0_L2>; |
6aad8bf9 RJ |
54 | }; |
55 | ||
5b31d875 | 56 | A57_1: cpu@1 { |
6aad8bf9 RJ |
57 | device_type = "cpu"; |
58 | compatible = "arm,cortex-a57", "arm,armv8"; | |
59 | reg = <0 1>; | |
a9abb475 | 60 | enable-method = "psci"; |
33a93aa4 | 61 | next-level-cache = <&CLUSTER0_L2>; |
6aad8bf9 RJ |
62 | }; |
63 | ||
5b31d875 | 64 | A57_2: cpu@2 { |
6aad8bf9 RJ |
65 | device_type = "cpu"; |
66 | compatible = "arm,cortex-a57", "arm,armv8"; | |
67 | reg = <0 2>; | |
a9abb475 | 68 | enable-method = "psci"; |
33a93aa4 | 69 | next-level-cache = <&CLUSTER0_L2>; |
6aad8bf9 RJ |
70 | }; |
71 | ||
5b31d875 | 72 | A57_3: cpu@3 { |
6aad8bf9 RJ |
73 | device_type = "cpu"; |
74 | compatible = "arm,cortex-a57", "arm,armv8"; | |
75 | reg = <0 3>; | |
a9abb475 | 76 | enable-method = "psci"; |
33a93aa4 AP |
77 | next-level-cache = <&CLUSTER0_L2>; |
78 | }; | |
79 | ||
d8bcaabe | 80 | CLUSTER0_L2: l2-cache@0 { |
33a93aa4 | 81 | compatible = "cache"; |
6aad8bf9 RJ |
82 | }; |
83 | }; | |
84 | ||
a9abb475 LS |
85 | psci { |
86 | compatible = "arm,psci-1.0"; | |
87 | method = "smc"; | |
88 | }; | |
89 | ||
6aad8bf9 RJ |
90 | timer { |
91 | compatible = "arm,armv8-timer"; | |
92 | interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0xff) | | |
f2a89d3b | 93 | IRQ_TYPE_LEVEL_LOW)>, |
6aad8bf9 | 94 | <GIC_PPI 14 (GIC_CPU_MASK_RAW(0xff) | |
f2a89d3b | 95 | IRQ_TYPE_LEVEL_LOW)>, |
6aad8bf9 | 96 | <GIC_PPI 11 (GIC_CPU_MASK_RAW(0xff) | |
f2a89d3b | 97 | IRQ_TYPE_LEVEL_LOW)>, |
6aad8bf9 | 98 | <GIC_PPI 10 (GIC_CPU_MASK_RAW(0xff) | |
f2a89d3b | 99 | IRQ_TYPE_LEVEL_LOW)>; |
6aad8bf9 RJ |
100 | }; |
101 | ||
5b31d875 AP |
102 | pmu { |
103 | compatible = "arm,armv8-pmuv3"; | |
104 | interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, | |
105 | <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, | |
106 | <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, | |
107 | <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; | |
108 | interrupt-affinity = <&A57_0>, | |
109 | <&A57_1>, | |
110 | <&A57_2>, | |
111 | <&A57_3>; | |
112 | }; | |
113 | ||
fd5e5dd5 RJ |
114 | pcie0: pcie@20020000 { |
115 | compatible = "brcm,iproc-pcie"; | |
116 | reg = <0 0x20020000 0 0x1000>; | |
f0c0cb99 | 117 | dma-coherent; |
fd5e5dd5 RJ |
118 | |
119 | #interrupt-cells = <1>; | |
120 | interrupt-map-mask = <0 0 0 0>; | |
177232d2 | 121 | interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 281 IRQ_TYPE_NONE>; |
fd5e5dd5 RJ |
122 | |
123 | linux,pci-domain = <0>; | |
124 | ||
125 | bus-range = <0x00 0xff>; | |
126 | ||
127 | #address-cells = <3>; | |
128 | #size-cells = <2>; | |
129 | device_type = "pci"; | |
130 | ranges = <0x83000000 0 0x00000000 0 0x00000000 0 0x20000000>; | |
131 | ||
132 | brcm,pcie-ob; | |
133 | brcm,pcie-ob-oarr-size; | |
134 | brcm,pcie-ob-axi-offset = <0x00000000>; | |
135 | brcm,pcie-ob-window-size = <256>; | |
136 | ||
137 | status = "disabled"; | |
138 | ||
7af371a7 JM |
139 | phys = <&pci_phy0>; |
140 | phy-names = "pcie-phy"; | |
141 | ||
177232d2 | 142 | msi-parent = <&v2m0>; |
fd5e5dd5 RJ |
143 | }; |
144 | ||
145 | pcie4: pcie@50020000 { | |
146 | compatible = "brcm,iproc-pcie"; | |
147 | reg = <0 0x50020000 0 0x1000>; | |
f0c0cb99 | 148 | dma-coherent; |
fd5e5dd5 RJ |
149 | |
150 | #interrupt-cells = <1>; | |
151 | interrupt-map-mask = <0 0 0 0>; | |
177232d2 | 152 | interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 305 IRQ_TYPE_NONE>; |
fd5e5dd5 RJ |
153 | |
154 | linux,pci-domain = <4>; | |
155 | ||
156 | bus-range = <0x00 0xff>; | |
157 | ||
158 | #address-cells = <3>; | |
159 | #size-cells = <2>; | |
160 | device_type = "pci"; | |
161 | ranges = <0x83000000 0 0x00000000 0 0x30000000 0 0x20000000>; | |
162 | ||
163 | brcm,pcie-ob; | |
164 | brcm,pcie-ob-oarr-size; | |
165 | brcm,pcie-ob-axi-offset = <0x30000000>; | |
166 | brcm,pcie-ob-window-size = <256>; | |
167 | ||
168 | status = "disabled"; | |
169 | ||
7af371a7 JM |
170 | phys = <&pci_phy1>; |
171 | phy-names = "pcie-phy"; | |
172 | ||
177232d2 | 173 | msi-parent = <&v2m0>; |
fd5e5dd5 RJ |
174 | }; |
175 | ||
2f5cb59c JM |
176 | pcie8: pcie@60c00000 { |
177 | compatible = "brcm,iproc-pcie-paxc"; | |
178 | reg = <0 0x60c00000 0 0x1000>; | |
f0c0cb99 | 179 | dma-coherent; |
2f5cb59c JM |
180 | linux,pci-domain = <8>; |
181 | ||
182 | bus-range = <0x0 0x1>; | |
183 | ||
184 | #address-cells = <3>; | |
185 | #size-cells = <2>; | |
186 | device_type = "pci"; | |
187 | ranges = <0x83000000 0 0x00000000 0 0x60000000 0 0x00c00000>; | |
188 | ||
189 | status = "disabled"; | |
190 | ||
191 | msi-parent = <&v2m0>; | |
192 | }; | |
193 | ||
6aad8bf9 RJ |
194 | soc: soc { |
195 | compatible = "simple-bus"; | |
196 | #address-cells = <1>; | |
197 | #size-cells = <1>; | |
198 | ranges = <0 0 0 0xffffffff>; | |
199 | ||
59a5bede AP |
200 | #include "ns2-clock.dtsi" |
201 | ||
dddc3c9d JM |
202 | enet: ethernet@61000000 { |
203 | compatible = "brcm,ns2-amac"; | |
204 | reg = <0x61000000 0x1000>, | |
205 | <0x61090000 0x1000>, | |
206 | <0x61030000 0x100>; | |
207 | reg-names = "amac_base", "idm_base", "nicpm_base"; | |
208 | interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>; | |
f0c0cb99 | 209 | dma-coherent; |
dddc3c9d JM |
210 | phy-handle = <&gphy0>; |
211 | phy-mode = "rgmii"; | |
212 | status = "disabled"; | |
213 | }; | |
214 | ||
e7924914 RR |
215 | pdc0: iproc-pdc0@612c0000 { |
216 | compatible = "brcm,iproc-pdc-mbox"; | |
217 | reg = <0x612c0000 0x445>; /* PDC FS0 regs */ | |
218 | interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; | |
219 | #mbox-cells = <1>; | |
f0c0cb99 | 220 | dma-coherent; |
e7924914 RR |
221 | brcm,rx-status-len = <32>; |
222 | brcm,use-bcm-hdr; | |
223 | }; | |
224 | ||
264f5f26 RR |
225 | crypto0: crypto@612d0000 { |
226 | compatible = "brcm,spum-crypto"; | |
227 | reg = <0x612d0000 0x900>; | |
228 | mboxes = <&pdc0 0>; | |
229 | }; | |
230 | ||
e7924914 RR |
231 | pdc1: iproc-pdc1@612e0000 { |
232 | compatible = "brcm,iproc-pdc-mbox"; | |
233 | reg = <0x612e0000 0x445>; /* PDC FS1 regs */ | |
234 | interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; | |
235 | #mbox-cells = <1>; | |
f0c0cb99 | 236 | dma-coherent; |
e7924914 RR |
237 | brcm,rx-status-len = <32>; |
238 | brcm,use-bcm-hdr; | |
239 | }; | |
240 | ||
264f5f26 RR |
241 | crypto1: crypto@612f0000 { |
242 | compatible = "brcm,spum-crypto"; | |
243 | reg = <0x612f0000 0x900>; | |
244 | mboxes = <&pdc1 0>; | |
245 | }; | |
246 | ||
e7924914 RR |
247 | pdc2: iproc-pdc2@61300000 { |
248 | compatible = "brcm,iproc-pdc-mbox"; | |
249 | reg = <0x61300000 0x445>; /* PDC FS2 regs */ | |
250 | interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; | |
251 | #mbox-cells = <1>; | |
f0c0cb99 | 252 | dma-coherent; |
e7924914 RR |
253 | brcm,rx-status-len = <32>; |
254 | brcm,use-bcm-hdr; | |
255 | }; | |
256 | ||
264f5f26 RR |
257 | crypto2: crypto@61310000 { |
258 | compatible = "brcm,spum-crypto"; | |
259 | reg = <0x61310000 0x900>; | |
260 | mboxes = <&pdc2 0>; | |
261 | }; | |
262 | ||
e7924914 RR |
263 | pdc3: iproc-pdc3@61320000 { |
264 | compatible = "brcm,iproc-pdc-mbox"; | |
265 | reg = <0x61320000 0x445>; /* PDC FS3 regs */ | |
266 | interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; | |
267 | #mbox-cells = <1>; | |
f0c0cb99 | 268 | dma-coherent; |
e7924914 RR |
269 | brcm,rx-status-len = <32>; |
270 | brcm,use-bcm-hdr; | |
271 | }; | |
272 | ||
264f5f26 RR |
273 | crypto3: crypto@61330000 { |
274 | compatible = "brcm,spum-crypto"; | |
275 | reg = <0x61330000 0x900>; | |
276 | mboxes = <&pdc3 0>; | |
277 | }; | |
278 | ||
538fb37c AP |
279 | dma0: dma@61360000 { |
280 | compatible = "arm,pl330", "arm,primecell"; | |
281 | reg = <0x61360000 0x1000>; | |
282 | interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, | |
283 | <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>, | |
284 | <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, | |
285 | <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, | |
286 | <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, | |
287 | <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, | |
288 | <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, | |
289 | <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>, | |
290 | <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>; | |
291 | #dma-cells = <1>; | |
292 | #dma-channels = <8>; | |
293 | #dma-requests = <32>; | |
294 | clocks = <&iprocslow>; | |
295 | clock-names = "apb_pclk"; | |
296 | }; | |
297 | ||
6ec5f3c5 AP |
298 | smmu: mmu@64000000 { |
299 | compatible = "arm,mmu-500"; | |
300 | reg = <0x64000000 0x40000>; | |
301 | #global-interrupts = <2>; | |
302 | interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, | |
303 | <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>, | |
304 | <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, | |
305 | <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>, | |
306 | <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>, | |
307 | <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>, | |
308 | <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>, | |
309 | <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>, | |
310 | <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>, | |
311 | <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, | |
312 | <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>, | |
313 | <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, | |
314 | <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>, | |
315 | <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>, | |
316 | <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>, | |
317 | <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, | |
318 | <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, | |
319 | <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, | |
320 | <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, | |
321 | <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, | |
322 | <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, | |
323 | <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, | |
324 | <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, | |
325 | <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, | |
326 | <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, | |
327 | <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, | |
328 | <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, | |
329 | <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, | |
330 | <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, | |
331 | <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, | |
332 | <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, | |
333 | <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, | |
334 | <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, | |
335 | <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>; | |
62b69232 | 336 | #iommu-cells = <1>; |
6ec5f3c5 AP |
337 | }; |
338 | ||
97b1504a YRDR |
339 | pinctrl: pinctrl@6501d130 { |
340 | compatible = "brcm,ns2-pinmux"; | |
341 | reg = <0x6501d130 0x08>, | |
342 | <0x660a0028 0x04>, | |
343 | <0x660009b0 0x40>; | |
344 | }; | |
345 | ||
5f2fb241 YRDR |
346 | gpio_aon: gpio@65024800 { |
347 | compatible = "brcm,iproc-gpio"; | |
348 | reg = <0x65024800 0x50>, | |
349 | <0x65024008 0x18>; | |
350 | ngpios = <6>; | |
351 | #gpio-cells = <2>; | |
352 | gpio-controller; | |
353 | }; | |
354 | ||
6aad8bf9 RJ |
355 | gic: interrupt-controller@65210000 { |
356 | compatible = "arm,gic-400"; | |
357 | #interrupt-cells = <3>; | |
358 | interrupt-controller; | |
359 | reg = <0x65210000 0x1000>, | |
360 | <0x65220000 0x1000>, | |
361 | <0x65240000 0x2000>, | |
362 | <0x65260000 0x1000>; | |
b2f9cd48 AP |
363 | interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) | |
364 | IRQ_TYPE_LEVEL_HIGH)>; | |
177232d2 JM |
365 | |
366 | #address-cells = <1>; | |
367 | #size-cells = <1>; | |
368 | ranges = <0 0x652e0000 0x80000>; | |
369 | ||
d8bcaabe | 370 | v2m0: v2m@0 { |
177232d2 JM |
371 | compatible = "arm,gic-v2m-frame"; |
372 | interrupt-parent = <&gic>; | |
373 | msi-controller; | |
374 | reg = <0x00000 0x1000>; | |
375 | arm,msi-base-spi = <72>; | |
376 | arm,msi-num-spis = <16>; | |
377 | }; | |
378 | ||
379 | v2m1: v2m@10000 { | |
380 | compatible = "arm,gic-v2m-frame"; | |
381 | interrupt-parent = <&gic>; | |
382 | msi-controller; | |
383 | reg = <0x10000 0x1000>; | |
384 | arm,msi-base-spi = <88>; | |
385 | arm,msi-num-spis = <16>; | |
386 | }; | |
387 | ||
388 | v2m2: v2m@20000 { | |
389 | compatible = "arm,gic-v2m-frame"; | |
390 | interrupt-parent = <&gic>; | |
391 | msi-controller; | |
392 | reg = <0x20000 0x1000>; | |
393 | arm,msi-base-spi = <104>; | |
394 | arm,msi-num-spis = <16>; | |
395 | }; | |
396 | ||
397 | v2m3: v2m@30000 { | |
398 | compatible = "arm,gic-v2m-frame"; | |
399 | interrupt-parent = <&gic>; | |
400 | msi-controller; | |
401 | reg = <0x30000 0x1000>; | |
402 | arm,msi-base-spi = <120>; | |
403 | arm,msi-num-spis = <16>; | |
404 | }; | |
405 | ||
406 | v2m4: v2m@40000 { | |
407 | compatible = "arm,gic-v2m-frame"; | |
408 | interrupt-parent = <&gic>; | |
409 | msi-controller; | |
410 | reg = <0x40000 0x1000>; | |
411 | arm,msi-base-spi = <136>; | |
412 | arm,msi-num-spis = <16>; | |
413 | }; | |
414 | ||
415 | v2m5: v2m@50000 { | |
416 | compatible = "arm,gic-v2m-frame"; | |
417 | interrupt-parent = <&gic>; | |
418 | msi-controller; | |
419 | reg = <0x50000 0x1000>; | |
420 | arm,msi-base-spi = <152>; | |
421 | arm,msi-num-spis = <16>; | |
422 | }; | |
423 | ||
424 | v2m6: v2m@60000 { | |
425 | compatible = "arm,gic-v2m-frame"; | |
426 | interrupt-parent = <&gic>; | |
427 | msi-controller; | |
428 | reg = <0x60000 0x1000>; | |
429 | arm,msi-base-spi = <168>; | |
430 | arm,msi-num-spis = <16>; | |
431 | }; | |
432 | ||
433 | v2m7: v2m@70000 { | |
434 | compatible = "arm,gic-v2m-frame"; | |
435 | interrupt-parent = <&gic>; | |
436 | msi-controller; | |
437 | reg = <0x70000 0x1000>; | |
438 | arm,msi-base-spi = <184>; | |
439 | arm,msi-num-spis = <16>; | |
440 | }; | |
6aad8bf9 RJ |
441 | }; |
442 | ||
5dcc9c76 JM |
443 | cci@65590000 { |
444 | compatible = "arm,cci-400"; | |
445 | #address-cells = <1>; | |
446 | #size-cells = <1>; | |
447 | reg = <0x65590000 0x1000>; | |
448 | ranges = <0 0x65590000 0x10000>; | |
449 | ||
450 | pmu@9000 { | |
451 | compatible = "arm,cci-400-pmu,r1", | |
452 | "arm,cci-400-pmu"; | |
453 | reg = <0x9000 0x4000>; | |
454 | interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, | |
455 | <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, | |
456 | <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>, | |
457 | <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>, | |
458 | <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>, | |
459 | <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>; | |
460 | }; | |
461 | }; | |
462 | ||
779ec2a6 RG |
463 | usbdrd_phy: phy@66000960 { |
464 | #phy-cells = <0>; | |
465 | compatible = "brcm,ns2-drd-phy"; | |
466 | reg = <0x66000960 0x24>, | |
467 | <0x67012800 0x4>, | |
468 | <0x6501d148 0x4>, | |
469 | <0x664d0700 0x4>; | |
470 | reg-names = "icfg", "rst-ctrl", | |
471 | "crmu-ctrl", "usb2-strap"; | |
472 | id-gpios = <&gpio_g 30 0>; | |
473 | vbus-gpios = <&gpio_g 31 0>; | |
474 | status = "disabled"; | |
475 | }; | |
476 | ||
5072ed1f YRDR |
477 | pwm: pwm@66010000 { |
478 | compatible = "brcm,iproc-pwm"; | |
479 | reg = <0x66010000 0x28>; | |
480 | clocks = <&osc>; | |
481 | #pwm-cells = <3>; | |
482 | status = "disabled"; | |
483 | }; | |
484 | ||
5f1a067b PK |
485 | mdio_mux_iproc: mdio-mux@6602023c { |
486 | compatible = "brcm,mdio-mux-iproc"; | |
487 | reg = <0x6602023c 0x14>; | |
488 | #address-cells = <1>; | |
489 | #size-cells = <0>; | |
490 | ||
491 | mdio@0 { | |
492 | reg = <0x0>; | |
493 | #address-cells = <1>; | |
494 | #size-cells = <0>; | |
495 | ||
496 | pci_phy0: pci-phy@0 { | |
497 | compatible = "brcm,ns2-pcie-phy"; | |
498 | reg = <0x0>; | |
499 | #phy-cells = <0>; | |
500 | status = "disabled"; | |
501 | }; | |
502 | }; | |
503 | ||
504 | mdio@7 { | |
505 | reg = <0x7>; | |
506 | #address-cells = <1>; | |
507 | #size-cells = <0>; | |
508 | ||
509 | pci_phy1: pci-phy@0 { | |
510 | compatible = "brcm,ns2-pcie-phy"; | |
511 | reg = <0x0>; | |
512 | #phy-cells = <0>; | |
513 | status = "disabled"; | |
514 | }; | |
515 | }; | |
516 | ||
517 | mdio@10 { | |
518 | reg = <0x10>; | |
519 | #address-cells = <1>; | |
520 | #size-cells = <0>; | |
521 | }; | |
522 | }; | |
523 | ||
e99df8fd AP |
524 | timer0: timer@66030000 { |
525 | compatible = "arm,sp804", "arm,primecell"; | |
526 | reg = <0x66030000 0x1000>; | |
527 | interrupts = <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>; | |
528 | clocks = <&iprocslow>, | |
529 | <&iprocslow>, | |
530 | <&iprocslow>; | |
531 | clock-names = "timer1", "timer2", "apb_pclk"; | |
532 | }; | |
533 | ||
534 | timer1: timer@66040000 { | |
535 | compatible = "arm,sp804", "arm,primecell"; | |
536 | reg = <0x66040000 0x1000>; | |
537 | interrupts = <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>; | |
538 | clocks = <&iprocslow>, | |
539 | <&iprocslow>, | |
540 | <&iprocslow>; | |
541 | clock-names = "timer1", "timer2", "apb_pclk"; | |
542 | }; | |
543 | ||
544 | timer2: timer@66050000 { | |
545 | compatible = "arm,sp804", "arm,primecell"; | |
546 | reg = <0x66050000 0x1000>; | |
547 | interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>; | |
548 | clocks = <&iprocslow>, | |
549 | <&iprocslow>, | |
550 | <&iprocslow>; | |
551 | clock-names = "timer1", "timer2", "apb_pclk"; | |
552 | }; | |
553 | ||
554 | timer3: timer@66060000 { | |
555 | compatible = "arm,sp804", "arm,primecell"; | |
556 | reg = <0x66060000 0x1000>; | |
557 | interrupts = <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>; | |
558 | clocks = <&iprocslow>, | |
559 | <&iprocslow>, | |
560 | <&iprocslow>; | |
561 | clock-names = "timer1", "timer2", "apb_pclk"; | |
562 | }; | |
563 | ||
7ac674e8 RJ |
564 | i2c0: i2c@66080000 { |
565 | compatible = "brcm,iproc-i2c"; | |
566 | reg = <0x66080000 0x100>; | |
567 | #address-cells = <1>; | |
568 | #size-cells = <0>; | |
e605c287 | 569 | interrupts = <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>; |
7ac674e8 RJ |
570 | clock-frequency = <100000>; |
571 | status = "disabled"; | |
572 | }; | |
573 | ||
6e79e7cf AP |
574 | wdt0: watchdog@66090000 { |
575 | compatible = "arm,sp805", "arm,primecell"; | |
576 | reg = <0x66090000 0x1000>; | |
577 | interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>; | |
578 | clocks = <&iprocslow>, <&iprocslow>; | |
579 | clock-names = "wdogclk", "apb_pclk"; | |
580 | }; | |
581 | ||
5f2fb241 YRDR |
582 | gpio_g: gpio@660a0000 { |
583 | compatible = "brcm,iproc-gpio"; | |
584 | reg = <0x660a0000 0x50>; | |
585 | ngpios = <32>; | |
586 | #gpio-cells = <2>; | |
587 | gpio-controller; | |
588 | interrupt-controller; | |
589 | interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>; | |
590 | }; | |
591 | ||
7ac674e8 RJ |
592 | i2c1: i2c@660b0000 { |
593 | compatible = "brcm,iproc-i2c"; | |
594 | reg = <0x660b0000 0x100>; | |
595 | #address-cells = <1>; | |
596 | #size-cells = <0>; | |
e605c287 | 597 | interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>; |
7ac674e8 RJ |
598 | clock-frequency = <100000>; |
599 | status = "disabled"; | |
600 | }; | |
601 | ||
1e0fdee8 JM |
602 | uart0: serial@66100000 { |
603 | compatible = "snps,dw-apb-uart"; | |
604 | reg = <0x66100000 0x100>; | |
605 | interrupts = <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>; | |
606 | clocks = <&iprocslow>; | |
607 | reg-shift = <2>; | |
608 | reg-io-width = <4>; | |
609 | status = "disabled"; | |
610 | }; | |
611 | ||
612 | uart1: serial@66110000 { | |
613 | compatible = "snps,dw-apb-uart"; | |
614 | reg = <0x66110000 0x100>; | |
615 | interrupts = <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>; | |
616 | clocks = <&iprocslow>; | |
617 | reg-shift = <2>; | |
618 | reg-io-width = <4>; | |
619 | status = "disabled"; | |
620 | }; | |
621 | ||
622 | uart2: serial@66120000 { | |
623 | compatible = "snps,dw-apb-uart"; | |
624 | reg = <0x66120000 0x100>; | |
625 | interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>; | |
626 | clocks = <&iprocslow>; | |
627 | reg-shift = <2>; | |
628 | reg-io-width = <4>; | |
629 | status = "disabled"; | |
630 | }; | |
631 | ||
6aad8bf9 RJ |
632 | uart3: serial@66130000 { |
633 | compatible = "snps,dw-apb-uart"; | |
634 | reg = <0x66130000 0x100>; | |
635 | interrupts = <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>; | |
636 | reg-shift = <2>; | |
637 | reg-io-width = <4>; | |
d8bd64c1 | 638 | clocks = <&osc>; |
6aad8bf9 RJ |
639 | status = "disabled"; |
640 | }; | |
e8a6e265 | 641 | |
d69dbd9f AP |
642 | ssp0: ssp@66180000 { |
643 | compatible = "arm,pl022", "arm,primecell"; | |
644 | reg = <0x66180000 0x1000>; | |
645 | interrupts = <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>; | |
646 | clocks = <&iprocslow>, <&iprocslow>; | |
647 | clock-names = "spiclk", "apb_pclk"; | |
648 | #address-cells = <1>; | |
649 | #size-cells = <0>; | |
650 | status = "disabled"; | |
651 | }; | |
652 | ||
653 | ssp1: ssp@66190000 { | |
654 | compatible = "arm,pl022", "arm,primecell"; | |
655 | reg = <0x66190000 0x1000>; | |
656 | interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>; | |
657 | clocks = <&iprocslow>, <&iprocslow>; | |
658 | clock-names = "spiclk", "apb_pclk"; | |
659 | #address-cells = <1>; | |
660 | #size-cells = <0>; | |
661 | status = "disabled"; | |
662 | }; | |
663 | ||
e8a6e265 AP |
664 | hwrng: hwrng@66220000 { |
665 | compatible = "brcm,iproc-rng200"; | |
666 | reg = <0x66220000 0x28>; | |
667 | }; | |
c6fe9a2e | 668 | |
ac9aae00 AP |
669 | sata_phy: sata_phy@663f0100 { |
670 | compatible = "brcm,iproc-ns2-sata-phy"; | |
671 | reg = <0x663f0100 0x1f00>, | |
672 | <0x663f004c 0x10>; | |
673 | reg-names = "phy", "phy-ctrl"; | |
674 | #address-cells = <1>; | |
675 | #size-cells = <0>; | |
676 | ||
677 | sata_phy0: sata-phy@0 { | |
678 | reg = <0>; | |
679 | #phy-cells = <0>; | |
680 | status = "disabled"; | |
681 | }; | |
682 | ||
683 | sata_phy1: sata-phy@1 { | |
684 | reg = <1>; | |
685 | #phy-cells = <0>; | |
686 | status = "disabled"; | |
687 | }; | |
688 | }; | |
689 | ||
690 | sata: ahci@663f2000 { | |
691 | compatible = "brcm,iproc-ahci", "generic-ahci"; | |
692 | reg = <0x663f2000 0x1000>; | |
f0c0cb99 | 693 | dma-coherent; |
ac9aae00 AP |
694 | reg-names = "ahci"; |
695 | interrupts = <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>; | |
696 | #address-cells = <1>; | |
697 | #size-cells = <0>; | |
698 | status = "disabled"; | |
699 | ||
700 | sata0: sata-port@0 { | |
701 | reg = <0>; | |
702 | phys = <&sata_phy0>; | |
703 | phy-names = "sata-phy"; | |
704 | }; | |
705 | ||
706 | sata1: sata-port@1 { | |
707 | reg = <1>; | |
708 | phys = <&sata_phy1>; | |
709 | phy-names = "sata-phy"; | |
710 | }; | |
711 | }; | |
712 | ||
efc87767 AP |
713 | sdio0: sdhci@66420000 { |
714 | compatible = "brcm,sdhci-iproc-cygnus"; | |
715 | reg = <0x66420000 0x100>; | |
716 | interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>; | |
f0c0cb99 | 717 | dma-coherent; |
efc87767 AP |
718 | bus-width = <8>; |
719 | clocks = <&genpll_sw BCM_NS2_GENPLL_SW_SDIO_CLK>; | |
720 | status = "disabled"; | |
721 | }; | |
722 | ||
723 | sdio1: sdhci@66430000 { | |
724 | compatible = "brcm,sdhci-iproc-cygnus"; | |
725 | reg = <0x66430000 0x100>; | |
726 | interrupts = <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>; | |
f0c0cb99 | 727 | dma-coherent; |
efc87767 AP |
728 | bus-width = <8>; |
729 | clocks = <&genpll_sw BCM_NS2_GENPLL_SW_SDIO_CLK>; | |
730 | status = "disabled"; | |
731 | }; | |
732 | ||
c6fe9a2e AP |
733 | nand: nand@66460000 { |
734 | compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1"; | |
735 | reg = <0x66460000 0x600>, | |
736 | <0x67015408 0x600>, | |
737 | <0x66460f00 0x20>; | |
738 | reg-names = "nand", "iproc-idm", "iproc-ext"; | |
739 | interrupts = <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>; | |
740 | ||
741 | #address-cells = <1>; | |
742 | #size-cells = <0>; | |
743 | ||
744 | brcm,nand-has-wp; | |
745 | }; | |
ff73917d KD |
746 | |
747 | qspi: spi@66470200 { | |
748 | compatible = "brcm,spi-bcm-qspi", "brcm,spi-ns2-qspi"; | |
749 | reg = <0x66470200 0x184>, | |
750 | <0x66470000 0x124>, | |
751 | <0x67017408 0x004>, | |
752 | <0x664703a0 0x01c>; | |
753 | reg-names = "mspi", "bspi", "intr_regs", | |
754 | "intr_status_reg"; | |
755 | interrupts = <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>; | |
756 | interrupt-names = "spi_l1_intr"; | |
757 | clocks = <&iprocmed>; | |
758 | clock-names = "iprocmed"; | |
759 | num-cs = <2>; | |
760 | #address-cells = <1>; | |
761 | #size-cells = <0>; | |
762 | }; | |
763 | ||
6aad8bf9 RJ |
764 | }; |
765 | }; |