Commit | Line | Data |
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b2441318 | 1 | // SPDX-License-Identifier: GPL-2.0 |
90556ca1 PM |
2 | /* |
3 | * ARM Ltd. Fast Models | |
4 | * | |
5 | * Versatile Express (VE) system model | |
6 | * Motherboard component | |
7 | * | |
8 | * VEMotherBoard.lisa | |
9 | */ | |
349b0f95 | 10 | / { |
bee7ff37 | 11 | bus@8000000 { |
349b0f95 SH |
12 | motherboard { |
13 | arm,v2m-memory-map = "rs1"; | |
14 | compatible = "arm,vexpress,v2m-p1", "simple-bus"; | |
15 | #address-cells = <2>; /* SMB chipselect number and offset */ | |
90556ca1 | 16 | #size-cells = <1>; |
349b0f95 SH |
17 | #interrupt-cells = <1>; |
18 | ranges; | |
19 | ||
20 | flash@0,00000000 { | |
21 | compatible = "arm,vexpress-flash", "cfi-flash"; | |
22 | reg = <0 0x00000000 0x04000000>, | |
23 | <4 0x00000000 0x04000000>; | |
24 | bank-width = <4>; | |
90556ca1 PM |
25 | }; |
26 | ||
349b0f95 SH |
27 | ethernet@2,02000000 { |
28 | compatible = "smsc,lan91c111"; | |
29 | reg = <2 0x02000000 0x10000>; | |
30 | interrupts = <15>; | |
90556ca1 PM |
31 | }; |
32 | ||
349b0f95 SH |
33 | v2m_clk24mhz: clk24mhz { |
34 | compatible = "fixed-clock"; | |
35 | #clock-cells = <0>; | |
36 | clock-frequency = <24000000>; | |
37 | clock-output-names = "v2m:clk24mhz"; | |
90556ca1 PM |
38 | }; |
39 | ||
349b0f95 SH |
40 | v2m_refclk1mhz: refclk1mhz { |
41 | compatible = "fixed-clock"; | |
42 | #clock-cells = <0>; | |
43 | clock-frequency = <1000000>; | |
44 | clock-output-names = "v2m:refclk1mhz"; | |
90556ca1 PM |
45 | }; |
46 | ||
349b0f95 SH |
47 | v2m_refclk32khz: refclk32khz { |
48 | compatible = "fixed-clock"; | |
49 | #clock-cells = <0>; | |
50 | clock-frequency = <32768>; | |
51 | clock-output-names = "v2m:refclk32khz"; | |
90556ca1 PM |
52 | }; |
53 | ||
349b0f95 SH |
54 | iofpga@3,00000000 { |
55 | compatible = "simple-bus"; | |
56 | #address-cells = <1>; | |
57 | #size-cells = <1>; | |
58 | ranges = <0 3 0 0x200000>; | |
59 | ||
60 | v2m_sysreg: sysreg@10000 { | |
61 | compatible = "arm,vexpress-sysreg"; | |
62 | reg = <0x010000 0x1000>; | |
63 | gpio-controller; | |
64 | #gpio-cells = <2>; | |
65 | }; | |
90556ca1 | 66 | |
349b0f95 SH |
67 | v2m_sysctl: sysctl@20000 { |
68 | compatible = "arm,sp810", "arm,primecell"; | |
69 | reg = <0x020000 0x1000>; | |
70 | clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&v2m_clk24mhz>; | |
71 | clock-names = "refclk", "timclk", "apb_pclk"; | |
72 | #clock-cells = <1>; | |
73 | clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3"; | |
74 | assigned-clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_sysctl 3>, <&v2m_sysctl 3>; | |
75 | assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>; | |
76 | }; | |
90556ca1 | 77 | |
349b0f95 SH |
78 | aaci@40000 { |
79 | compatible = "arm,pl041", "arm,primecell"; | |
80 | reg = <0x040000 0x1000>; | |
81 | interrupts = <11>; | |
82 | clocks = <&v2m_clk24mhz>; | |
83 | clock-names = "apb_pclk"; | |
84 | }; | |
90556ca1 | 85 | |
349b0f95 SH |
86 | mmci@50000 { |
87 | compatible = "arm,pl180", "arm,primecell"; | |
88 | reg = <0x050000 0x1000>; | |
88c2ccc0 | 89 | interrupts = <9>, <10>; |
349b0f95 SH |
90 | cd-gpios = <&v2m_sysreg 0 0>; |
91 | wp-gpios = <&v2m_sysreg 1 0>; | |
92 | max-frequency = <12000000>; | |
93 | vmmc-supply = <&v2m_fixed_3v3>; | |
94 | clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; | |
95 | clock-names = "mclk", "apb_pclk"; | |
96 | }; | |
90556ca1 | 97 | |
349b0f95 SH |
98 | kmi@60000 { |
99 | compatible = "arm,pl050", "arm,primecell"; | |
100 | reg = <0x060000 0x1000>; | |
101 | interrupts = <12>; | |
102 | clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; | |
103 | clock-names = "KMIREFCLK", "apb_pclk"; | |
104 | }; | |
90556ca1 | 105 | |
349b0f95 SH |
106 | kmi@70000 { |
107 | compatible = "arm,pl050", "arm,primecell"; | |
108 | reg = <0x070000 0x1000>; | |
109 | interrupts = <13>; | |
110 | clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; | |
111 | clock-names = "KMIREFCLK", "apb_pclk"; | |
112 | }; | |
90556ca1 | 113 | |
349b0f95 SH |
114 | v2m_serial0: uart@90000 { |
115 | compatible = "arm,pl011", "arm,primecell"; | |
116 | reg = <0x090000 0x1000>; | |
117 | interrupts = <5>; | |
118 | clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; | |
119 | clock-names = "uartclk", "apb_pclk"; | |
120 | }; | |
90556ca1 | 121 | |
349b0f95 SH |
122 | v2m_serial1: uart@a0000 { |
123 | compatible = "arm,pl011", "arm,primecell"; | |
124 | reg = <0x0a0000 0x1000>; | |
125 | interrupts = <6>; | |
126 | clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; | |
127 | clock-names = "uartclk", "apb_pclk"; | |
128 | }; | |
90556ca1 | 129 | |
349b0f95 SH |
130 | v2m_serial2: uart@b0000 { |
131 | compatible = "arm,pl011", "arm,primecell"; | |
132 | reg = <0x0b0000 0x1000>; | |
133 | interrupts = <7>; | |
134 | clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; | |
135 | clock-names = "uartclk", "apb_pclk"; | |
e2b6b35e CM |
136 | }; |
137 | ||
349b0f95 SH |
138 | v2m_serial3: uart@c0000 { |
139 | compatible = "arm,pl011", "arm,primecell"; | |
140 | reg = <0x0c0000 0x1000>; | |
141 | interrupts = <8>; | |
142 | clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; | |
143 | clock-names = "uartclk", "apb_pclk"; | |
144 | }; | |
145 | ||
146 | wdt@f0000 { | |
147 | compatible = "arm,sp805", "arm,primecell"; | |
148 | reg = <0x0f0000 0x1000>; | |
149 | interrupts = <0>; | |
150 | clocks = <&v2m_refclk32khz>, <&v2m_clk24mhz>; | |
151 | clock-names = "wdogclk", "apb_pclk"; | |
152 | }; | |
153 | ||
154 | v2m_timer01: timer@110000 { | |
155 | compatible = "arm,sp804", "arm,primecell"; | |
156 | reg = <0x110000 0x1000>; | |
157 | interrupts = <2>; | |
158 | clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_clk24mhz>; | |
159 | clock-names = "timclken1", "timclken2", "apb_pclk"; | |
160 | }; | |
161 | ||
162 | v2m_timer23: timer@120000 { | |
163 | compatible = "arm,sp804", "arm,primecell"; | |
164 | reg = <0x120000 0x1000>; | |
165 | interrupts = <3>; | |
166 | clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&v2m_clk24mhz>; | |
167 | clock-names = "timclken1", "timclken2", "apb_pclk"; | |
168 | }; | |
169 | ||
20d00c40 SH |
170 | virtio-block@130000 { |
171 | compatible = "virtio,mmio"; | |
172 | reg = <0x130000 0x200>; | |
173 | interrupts = <42>; | |
174 | }; | |
175 | ||
349b0f95 SH |
176 | rtc@170000 { |
177 | compatible = "arm,pl031", "arm,primecell"; | |
178 | reg = <0x170000 0x1000>; | |
179 | interrupts = <4>; | |
180 | clocks = <&v2m_clk24mhz>; | |
181 | clock-names = "apb_pclk"; | |
182 | }; | |
183 | ||
184 | clcd@1f0000 { | |
185 | compatible = "arm,pl111", "arm,primecell"; | |
186 | reg = <0x1f0000 0x1000>; | |
187 | interrupt-names = "combined"; | |
188 | interrupts = <14>; | |
189 | clocks = <&v2m_oscclk1>, <&v2m_clk24mhz>; | |
190 | clock-names = "clcdclk", "apb_pclk"; | |
f1fe12c8 | 191 | memory-region = <&vram>; |
e2b6b35e CM |
192 | |
193 | port { | |
f1fe12c8 LW |
194 | clcd_pads: endpoint { |
195 | remote-endpoint = <&panel_in>; | |
349b0f95 | 196 | arm,pl11x,tft-r0g0b0-pads = <0 8 16>; |
e2b6b35e CM |
197 | }; |
198 | }; | |
e2b6b35e | 199 | }; |
1bb2cbb6 | 200 | }; |
90556ca1 | 201 | |
349b0f95 SH |
202 | v2m_fixed_3v3: v2m-3v3 { |
203 | compatible = "regulator-fixed"; | |
204 | regulator-name = "3V3"; | |
205 | regulator-min-microvolt = <3300000>; | |
206 | regulator-max-microvolt = <3300000>; | |
207 | regulator-always-on; | |
90556ca1 PM |
208 | }; |
209 | ||
349b0f95 SH |
210 | mcc { |
211 | compatible = "arm,vexpress,config-bus"; | |
212 | arm,vexpress,config-bridge = <&v2m_sysreg>; | |
213 | ||
214 | v2m_oscclk1: oscclk1 { | |
215 | /* CLCD clock */ | |
216 | compatible = "arm,vexpress-osc"; | |
217 | arm,vexpress-sysreg,func = <1 1>; | |
218 | freq-range = <23750000 63500000>; | |
219 | #clock-cells = <0>; | |
220 | clock-output-names = "v2m:oscclk1"; | |
221 | }; | |
90556ca1 | 222 | |
349b0f95 SH |
223 | reset { |
224 | compatible = "arm,vexpress-reset"; | |
225 | arm,vexpress-sysreg,func = <5 0>; | |
226 | }; | |
90556ca1 | 227 | |
349b0f95 SH |
228 | muxfpga { |
229 | compatible = "arm,vexpress-muxfpga"; | |
230 | arm,vexpress-sysreg,func = <7 0>; | |
231 | }; | |
90556ca1 | 232 | |
349b0f95 SH |
233 | shutdown { |
234 | compatible = "arm,vexpress-shutdown"; | |
235 | arm,vexpress-sysreg,func = <8 0>; | |
236 | }; | |
237 | ||
238 | reboot { | |
239 | compatible = "arm,vexpress-reboot"; | |
240 | arm,vexpress-sysreg,func = <9 0>; | |
241 | }; | |
90556ca1 | 242 | |
349b0f95 SH |
243 | dvimode { |
244 | compatible = "arm,vexpress-dvimode"; | |
245 | arm,vexpress-sysreg,func = <11 0>; | |
246 | }; | |
90556ca1 PM |
247 | }; |
248 | }; | |
249 | }; | |
349b0f95 | 250 | }; |