[linux-2.6-block.git] / arch / arm64 / boot / dts / arm / rtsm_ve-aemv8a.dts

// SPDX-License-Identifier: GPL-2.0
/*
 * ARM Ltd. Fast Models
 *
 * Architecture Envelope Model (AEM) ARMv8-A
 * ARMAEMv8AMPCT
 *
 * RTSM_VE_AEMv8A.lisa
 */

/dts-v1/;

#include <dt-bindings/interrupt-controller/arm-gic.h>

/memreserve/ 0x80000000 0x00010000;

#include "rtsm_ve-motherboard.dtsi"

/ {
	model = "RTSM_VE_AEMv8A";
	compatible = "arm,rtsm_ve,aemv8a", "arm,vexpress";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	chosen {
		stdout-path = "serial0:115200n8";
	};

	aliases {
		serial0 = &v2m_serial0;
		serial1 = &v2m_serial1;
		serial2 = &v2m_serial2;
		serial3 = &v2m_serial3;
	};

	cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,armv8";
			reg = <0x0 0x0>;
			enable-method = "spin-table";
			cpu-release-addr = <0x0 0x8000fff8>;
			next-level-cache = <&L2_0>;
		};
		cpu@1 {
			device_type = "cpu";
			compatible = "arm,armv8";
			reg = <0x0 0x1>;
			enable-method = "spin-table";
			cpu-release-addr = <0x0 0x8000fff8>;
			next-level-cache = <&L2_0>;
		};
		cpu@2 {
			device_type = "cpu";
			compatible = "arm,armv8";
			reg = <0x0 0x2>;
			enable-method = "spin-table";
			cpu-release-addr = <0x0 0x8000fff8>;
			next-level-cache = <&L2_0>;
		};
		cpu@3 {
			device_type = "cpu";
			compatible = "arm,armv8";
			reg = <0x0 0x3>;
			enable-method = "spin-table";
			cpu-release-addr = <0x0 0x8000fff8>;
			next-level-cache = <&L2_0>;
		};

		L2_0: l2-cache0 {
			compatible = "cache";
			cache-level = <2>;
			cache-unified;
		};
	};

	memory@80000000 {
		device_type = "memory";
		reg = <0x00000000 0x80000000 0 0x80000000>,
		      <0x00000008 0x80000000 0 0x80000000>;
	};

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		/* Chipselect 2,00000000 is physically at 0x18000000 */
		vram: vram@18000000 {
			/* 8 MB of designated video RAM */
			compatible = "shared-dma-pool";
			reg = <0x00000000 0x18000000 0 0x00800000>;
			no-map;
		};
	};

	gic: interrupt-controller@2c001000 {
		compatible = "arm,gic-400", "arm,cortex-a15-gic";
		#interrupt-cells = <3>;
		#address-cells = <0>;
		interrupt-controller;
		reg = <0x0 0x2c001000 0 0x1000>,
		      <0x0 0x2c002000 0 0x2000>,
		      <0x0 0x2c004000 0 0x2000>,
		      <0x0 0x2c006000 0 0x2000>;
		interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
		clock-frequency = <100000000>;
	};

	pmu {
		compatible = "arm,armv8-pmuv3";
		interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
	};

	panel {
		compatible = "arm,rtsm-display";
		port {
			panel_in: endpoint {
				remote-endpoint = <&clcd_pads>;
			};
		};
	};

	bus@8000000 {
		#interrupt-cells = <1>;
		interrupt-map-mask = <0 0 63>;
		interrupt-map = <0 0  0 &gic GIC_SPI  0 IRQ_TYPE_LEVEL_HIGH>,
				<0 0  1 &gic GIC_SPI  1 IRQ_TYPE_LEVEL_HIGH>,
				<0 0  2 &gic GIC_SPI  2 IRQ_TYPE_LEVEL_HIGH>,
				<0 0  3 &gic GIC_SPI  3 IRQ_TYPE_LEVEL_HIGH>,
				<0 0  4 &gic GIC_SPI  4 IRQ_TYPE_LEVEL_HIGH>,
				<0 0  5 &gic GIC_SPI  5 IRQ_TYPE_LEVEL_HIGH>,
				<0 0  6 &gic GIC_SPI  6 IRQ_TYPE_LEVEL_HIGH>,
				<0 0  7 &gic GIC_SPI  7 IRQ_TYPE_LEVEL_HIGH>,
				<0 0  8 &gic GIC_SPI  8 IRQ_TYPE_LEVEL_HIGH>,
				<0 0  9 &gic GIC_SPI  9 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 10 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 11 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 12 &gic GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 13 &gic GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 14 &gic GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 15 &gic GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 16 &gic GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 17 &gic GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 18 &gic GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 19 &gic GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 20 &gic GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 21 &gic GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 22 &gic GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 23 &gic GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 24 &gic GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 25 &gic GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 26 &gic GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 27 &gic GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 28 &gic GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 29 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 30 &gic GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 31 &gic GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 32 &gic GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 33 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 34 &gic GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 35 &gic GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 36 &gic GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 37 &gic GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 38 &gic GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 39 &gic GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 40 &gic GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 41 &gic GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 42 &gic GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
	};
};
Commit	Line	Data
b2441318	1	// SPDX-License-Identifier: GPL-2.0
90556ca1 PM	2	/*
	3	* ARM Ltd. Fast Models
	4	*
	5	* Architecture Envelope Model (AEM) ARMv8-A
	6	* ARMAEMv8AMPCT
	7	*
	8	* RTSM_VE_AEMv8A.lisa
	9	*/
	10
	11	/dts-v1/;
	12
ef972714 SH	13	#include <dt-bindings/interrupt-controller/arm-gic.h>
ef972714 SH	14
90556ca1 PM	15	/memreserve/ 0x80000000 0x00010000;
90556ca1 PM	16
349b0f95 SH	17	#include "rtsm_ve-motherboard.dtsi"
349b0f95 SH	18
90556ca1 PM	19	/ {
	20	model = "RTSM_VE_AEMv8A";
	21	compatible = "arm,rtsm_ve,aemv8a", "arm,vexpress";
	22	interrupt-parent = <&gic>;
	23	#address-cells = <2>;
	24	#size-cells = <2>;
	25
9d4a984a DM	26	chosen {
	27	stdout-path = "serial0:115200n8";
	28	};
90556ca1 PM	29
	30	aliases {
	31	serial0 = &v2m_serial0;
	32	serial1 = &v2m_serial1;
	33	serial2 = &v2m_serial2;
	34	serial3 = &v2m_serial3;
	35	};
	36
	37	cpus {
	38	#address-cells = <2>;
	39	#size-cells = <0>;
	40
	41	cpu@0 {
	42	device_type = "cpu";
	43	compatible = "arm,armv8";
	44	reg = <0x0 0x0>;
	45	enable-method = "spin-table";
	46	cpu-release-addr = <0x0 0x8000fff8>;
7934d69a	47	next-level-cache = <&L2_0>;
90556ca1 PM	48	};
	49	cpu@1 {
	50	device_type = "cpu";
	51	compatible = "arm,armv8";
	52	reg = <0x0 0x1>;
	53	enable-method = "spin-table";
	54	cpu-release-addr = <0x0 0x8000fff8>;
7934d69a	55	next-level-cache = <&L2_0>;
90556ca1 PM	56	};
	57	cpu@2 {
	58	device_type = "cpu";
	59	compatible = "arm,armv8";
	60	reg = <0x0 0x2>;
	61	enable-method = "spin-table";
	62	cpu-release-addr = <0x0 0x8000fff8>;
7934d69a	63	next-level-cache = <&L2_0>;
90556ca1 PM	64	};
	65	cpu@3 {
	66	device_type = "cpu";
	67	compatible = "arm,armv8";
	68	reg = <0x0 0x3>;
	69	enable-method = "spin-table";
	70	cpu-release-addr = <0x0 0x8000fff8>;
7934d69a SH	71	next-level-cache = <&L2_0>;
	72	};
	73
	74	L2_0: l2-cache0 {
	75	compatible = "cache";
59fb813f	76	cache-level = <2>;
55b37d9c	77	cache-unified;
90556ca1 PM	78	};
	79	};
	80
	81	memory@80000000 {
	82	device_type = "memory";
	83	reg = <0x00000000 0x80000000 0 0x80000000>,
	84	<0x00000008 0x80000000 0 0x80000000>;
	85	};
	86
f1fe12c8 LW	87	reserved-memory {
	88	#address-cells = <2>;
	89	#size-cells = <2>;
	90	ranges;
	91
	92	/* Chipselect 2,00000000 is physically at 0x18000000 */
	93	vram: vram@18000000 {
	94	/* 8 MB of designated video RAM */
	95	compatible = "shared-dma-pool";
	96	reg = <0x00000000 0x18000000 0 0x00800000>;
	97	no-map;
	98	};
	99	};
	100
90556ca1	101	gic: interrupt-controller@2c001000 {
336edacf	102	compatible = "arm,gic-400", "arm,cortex-a15-gic";
90556ca1 PM	103	#interrupt-cells = <3>;
	104	#address-cells = <0>;
	105	interrupt-controller;
	106	reg = <0x0 0x2c001000 0 0x1000>,
1dff32d7	107	<0x0 0x2c002000 0 0x2000>,
90556ca1 PM	108	<0x0 0x2c004000 0 0x2000>,
90556ca1 PM	109	<0x0 0x2c006000 0 0x2000>;
ef972714	110	interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_HIGH)>;
90556ca1 PM	111	};
	112
	113	timer {
	114	compatible = "arm,armv8-timer";
ef972714 SH	115	interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
	116	<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
	117	<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
	118	<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>;
90556ca1 PM	119	clock-frequency = <100000000>;
	120	};
	121
	122	pmu {
	123	compatible = "arm,armv8-pmuv3";
ef972714 SH	124	interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
	125	<GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
	126	<GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
	127	<GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
90556ca1 PM	128	};
90556ca1 PM	129
f1fe12c8 LW	130	panel {
	131	compatible = "arm,rtsm-display";
	132	port {
	133	panel_in: endpoint {
	134	remote-endpoint = <&clcd_pads>;
	135	};
	136	};
	137	};
	138
bee7ff37	139	bus@8000000 {
90556ca1 PM	140	#interrupt-cells = <1>;
90556ca1 PM	141	interrupt-map-mask = <0 0 63>;
ef972714 SH	142	interrupt-map = <0 0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
	143	<0 0 1 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
	144	<0 0 2 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
	145	<0 0 3 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
	146	<0 0 4 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
	147	<0 0 5 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
	148	<0 0 6 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
	149	<0 0 7 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
	150	<0 0 8 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
	151	<0 0 9 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
	152	<0 0 10 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
	153	<0 0 11 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
	154	<0 0 12 &gic GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
	155	<0 0 13 &gic GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
	156	<0 0 14 &gic GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
	157	<0 0 15 &gic GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
	158	<0 0 16 &gic GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
	159	<0 0 17 &gic GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
	160	<0 0 18 &gic GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
	161	<0 0 19 &gic GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
	162	<0 0 20 &gic GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
	163	<0 0 21 &gic GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
	164	<0 0 22 &gic GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
	165	<0 0 23 &gic GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
	166	<0 0 24 &gic GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
	167	<0 0 25 &gic GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
	168	<0 0 26 &gic GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
	169	<0 0 27 &gic GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
	170	<0 0 28 &gic GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
	171	<0 0 29 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
	172	<0 0 30 &gic GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
	173	<0 0 31 &gic GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
	174	<0 0 32 &gic GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
	175	<0 0 33 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
	176	<0 0 34 &gic GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
	177	<0 0 35 &gic GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
	178	<0 0 36 &gic GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
	179	<0 0 37 &gic GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
	180	<0 0 38 &gic GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
	181	<0 0 39 &gic GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
	182	<0 0 40 &gic GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
	183	<0 0 41 &gic GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
	184	<0 0 42 &gic GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
90556ca1 PM	185	};
90556ca1 PM	186	};