[linux-block.git] / arch / arm64 / boot / dts / amlogic / meson-s4.dtsi

// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (c) 2021 Amlogic, Inc. All rights reserved.
 */

#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/gpio/meson-s4-gpio.h>
#include <dt-bindings/clock/amlogic,s4-pll-clkc.h>
#include <dt-bindings/clock/amlogic,s4-peripherals-clkc.h>
#include <dt-bindings/power/meson-s4-power.h>

/ {
	cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a35";
			reg = <0x0 0x0>;
			enable-method = "psci";
		};

		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a35";
			reg = <0x0 0x1>;
			enable-method = "psci";
		};

		cpu2: cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a35";
			reg = <0x0 0x2>;
			enable-method = "psci";
		};

		cpu3: cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a35";
			reg = <0x0 0x3>;
			enable-method = "psci";
		};
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
	};

	psci {
		compatible = "arm,psci-1.0";
		method = "smc";
	};

	xtal: xtal-clk {
		compatible = "fixed-clock";
		clock-frequency = <24000000>;
		clock-output-names = "xtal";
		#clock-cells = <0>;
	};

	firmware {
		sm: secure-monitor {
			compatible = "amlogic,meson-gxbb-sm";

			pwrc: power-controller {
				compatible = "amlogic,meson-s4-pwrc";
				#power-domain-cells = <1>;
			};
		};
	};

	soc {
		compatible = "simple-bus";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		gic: interrupt-controller@fff01000 {
			compatible = "arm,gic-400";
			#interrupt-cells = <3>;
			#address-cells = <0>;
			interrupt-controller;
			reg = <0x0 0xfff01000 0 0x1000>,
			      <0x0 0xfff02000 0 0x2000>,
			      <0x0 0xfff04000 0 0x2000>,
			      <0x0 0xfff06000 0 0x2000>;
			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
		};

		apb4: bus@fe000000 {
			compatible = "simple-bus";
			reg = <0x0 0xfe000000 0x0 0x480000>;
			#address-cells = <2>;
			#size-cells = <2>;
			ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x480000>;

			clkc_periphs: clock-controller@0 {
				compatible = "amlogic,s4-peripherals-clkc";
				reg = <0x0 0x0 0x0 0x49c>;
				clocks = <&clkc_pll CLKID_FCLK_DIV2>,
					<&clkc_pll CLKID_FCLK_DIV2P5>,
					<&clkc_pll CLKID_FCLK_DIV3>,
					<&clkc_pll CLKID_FCLK_DIV4>,
					<&clkc_pll CLKID_FCLK_DIV5>,
					<&clkc_pll CLKID_FCLK_DIV7>,
					<&clkc_pll CLKID_HIFI_PLL>,
					<&clkc_pll CLKID_GP0_PLL>,
					<&clkc_pll CLKID_MPLL0>,
					<&clkc_pll CLKID_MPLL1>,
					<&clkc_pll CLKID_MPLL2>,
					<&clkc_pll CLKID_MPLL3>,
					<&clkc_pll CLKID_HDMI_PLL>,
					<&xtal>;
				clock-names = "fclk_div2", "fclk_div2p5", "fclk_div3",
						"fclk_div4", "fclk_div5", "fclk_div7",
						"hifi_pll", "gp0_pll", "mpll0", "mpll1",
						"mpll2", "mpll3", "hdmi_pll", "xtal";
				#clock-cells = <1>;
			};

			clkc_pll: clock-controller@8000 {
				compatible = "amlogic,s4-pll-clkc";
				reg = <0x0 0x8000 0x0 0x1e8>;
				clocks = <&xtal>;
				clock-names = "xtal";
				#clock-cells = <1>;
			};

			watchdog@2100 {
				compatible = "amlogic,s4-wdt", "amlogic,t7-wdt";
				reg = <0x0 0x2100 0x0 0x10>;
				clocks = <&xtal>;
			};

			periphs_pinctrl: pinctrl@4000 {
				compatible = "amlogic,meson-s4-periphs-pinctrl";
				#address-cells = <2>;
				#size-cells = <2>;
				ranges;

				gpio: bank@4000 {
					reg = <0x0 0x4000 0x0 0x004c>,
					      <0x0 0x40c0 0x0 0x0220>;
					reg-names = "mux", "gpio";
					gpio-controller;
					#gpio-cells = <2>;
					gpio-ranges = <&periphs_pinctrl 0 0 82>;
				};

				remote_pins: remote-pin {
					mux {
						groups = "remote_in";
						function = "remote_in";
						bias-disable;
					};
				};

				i2c0_pins1: i2c0-pins1 {
					mux {
						groups = "i2c0_sda",
						       "i2c0_scl";
						function = "i2c0";
						drive-strength-microamp = <3000>;
						bias-disable;
					};
				};

				i2c1_pins1: i2c1-pins1 {
					mux {
						groups = "i2c1_sda_c",
						       "i2c1_scl_c";
						function = "i2c1";
						drive-strength-microamp = <3000>;
						bias-disable;
					};
				};

				i2c1_pins2: i2c1-pins2 {
					mux {
						groups = "i2c1_sda_d",
						       "i2c1_scl_d";
						function = "i2c1";
						drive-strength-microamp = <3000>;
						bias-disable;
					};
				};

				i2c1_pins3: i2c1-pins3 {
					mux {
						groups = "i2c1_sda_h",
						       "i2c1_scl_h";
						function = "i2c1";
						drive-strength-microamp = <3000>;
						bias-disable;
					};
				};

				i2c1_pins4: i2c1-pins4 {
					mux {
						groups = "i2c1_sda_x",
						       "i2c1_scl_x";
						function = "i2c1";
						drive-strength-microamp = <3000>;
						bias-disable;
					};
				};

				i2c2_pins1: i2c2-pins1 {
					mux {
						groups = "i2c2_sda_d",
						       "i2c2_scl_d";
						function = "i2c2";
						drive-strength-microamp = <3000>;
						bias-disable;
					};
				};

				i2c2_pins2: i2c2-pins2 {
					mux {
						groups = "i2c2_sda_h8",
						       "i2c2_scl_h9";
						function = "i2c2";
						drive-strength-microamp = <3000>;
						bias-disable;
					};
				};

				i2c2_pins3: i2c2-pins3 {
					mux {
						groups = "i2c2_sda_h0",
						       "i2c2_scl_h1";
						function = "i2c2";
						drive-strength-microamp = <3000>;
						bias-disable;
					};
				};

				i2c3_pins1: i2c3-pins1 {
					mux {
						groups = "i2c3_sda_x",
						       "i2c3_scl_x";
						function = "i2c3";
						drive-strength-microamp = <3000>;
						bias-disable;
					};
				};

				i2c3_pins2: i2c3-pins2 {
					mux {
						groups = "i2c3_sda_z",
						       "i2c3_scl_z";
						function = "i2c3";
						drive-strength-microamp = <3000>;
						bias-disable;
					};
				};

				i2c4_pins1: i2c4-pins1 {
					mux {
						groups = "i2c4_sda_c",
						       "i2c4_scl_c";
						function = "i2c4";
						drive-strength-microamp = <3000>;
						bias-disable;
					};
				};

				i2c4_pins2: i2c4-pins2 {
					mux {
						groups = "i2c4_sda_d",
						       "i2c4_scl_d";
						function = "i2c4";
						drive-strength-microamp = <3000>;
						bias-disable;
					};
				};

				i2c4_pins3: i2c4-pins3 {
					mux {
						groups = "i2c4_sda_z",
						       "i2c4_scl_z";
						function = "i2c4";
						drive-strength-microamp = <3000>;
						bias-disable;
					};
				};

				nand_pins: nand-pins {
					mux {
						groups = "emmc_nand_d0",
						       "emmc_nand_d1",
						       "emmc_nand_d2",
						       "emmc_nand_d3",
						       "emmc_nand_d4",
						       "emmc_nand_d5",
						       "emmc_nand_d6",
						       "emmc_nand_d7",
						       "nand_ce0",
						       "nand_ale",
						       "nand_cle",
						       "nand_wen_clk",
						       "nand_ren_wr";
						function = "nand";
						input-enable;
					};
				};

				spicc0_pins_x: spicc0-pins_x {
					mux {
						groups = "spi_a_mosi_x",
						       "spi_a_miso_x",
						       "spi_a_clk_x";
						function = "spi_a";
						drive-strength-microamp = <3000>;
					};
				};

				spicc0_pins_h: spicc0-pins-h {
					mux {
						groups = "spi_a_mosi_h",
						       "spi_a_miso_h",
						       "spi_a_clk_h";
						function = "spi_a";
						drive-strength-microamp = <3000>;
					};
				};

				spicc0_pins_z: spicc0-pins-z {
					mux {
						groups = "spi_a_mosi_z",
						       "spi_a_miso_z",
						       "spi_a_clk_z";
						function = "spi_a";
						drive-strength-microamp = <3000>;
					};
				};

			};

			gpio_intc: interrupt-controller@4080 {
				compatible = "amlogic,meson-s4-gpio-intc",
					     "amlogic,meson-gpio-intc";
				reg = <0x0 0x4080 0x0 0x20>;
				interrupt-controller;
				#interrupt-cells = <2>;
				amlogic,channel-interrupts =
					<10 11 12 13 14 15 16 17 18 19 20 21>;
			};

			eth_phy: mdio-multiplexer@28000 {
				compatible = "amlogic,g12a-mdio-mux";
				reg = <0x0 0x28000 0x0 0xa4>;

				#address-cells = <1>;
				#size-cells = <0>;
				clocks = <&clkc_periphs CLKID_ETHPHY>,
					 <&xtal>,
					 <&clkc_pll CLKID_MPLL_50M>;
				clock-names = "pclk", "clkin0", "clkin1";
				mdio-parent-bus = <&mdio0>;

				ext_mdio: mdio@0 {
					reg = <0>;
					#address-cells = <1>;
					#size-cells = <0>;
				};

				int_mdio: mdio@1 {
					reg = <1>;
					#address-cells = <1>;
					#size-cells = <0>;

					internal_ephy: ethernet-phy@8 {
						compatible = "ethernet-phy-id0180.3301",
							     "ethernet-phy-ieee802.3-c22";
						interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
						reg = <8>;
						max-speed = <100>;
					};
				};
			};

			spicc0: spi@50000 {
				compatible = "amlogic,meson-g12a-spicc";
				reg = <0x0 0x50000 0x0 0x44>;
				interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clkc_periphs CLKID_SPICC0>,
					 <&clkc_periphs CLKID_SPICC0_EN>;
				clock-names = "core", "pclk";
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};

			i2c0: i2c@66000 {
				compatible = "amlogic,meson-axg-i2c";
				reg = <0x0 0x66000 0x0 0x20>;
				interrupts = <GIC_SPI 160 IRQ_TYPE_EDGE_RISING>;
				clocks = <&clkc_periphs CLKID_I2C_M_A>;
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};

			i2c1: i2c@68000 {
				compatible = "amlogic,meson-axg-i2c";
				reg = <0x0 0x68000 0x0 0x20>;
				interrupts = <GIC_SPI 161 IRQ_TYPE_EDGE_RISING>;
				clocks = <&clkc_periphs CLKID_I2C_M_B>;
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};

			i2c2: i2c@6a000 {
				compatible = "amlogic,meson-axg-i2c";
				reg = <0x0 0x6a000 0x0 0x20>;
				interrupts = <GIC_SPI 162 IRQ_TYPE_EDGE_RISING>;
				clocks = <&clkc_periphs CLKID_I2C_M_C>;
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};

			i2c3: i2c@6c000 {
				compatible = "amlogic,meson-axg-i2c";
				reg = <0x0 0x6c000 0x0 0x20>;
				interrupts = <GIC_SPI 163 IRQ_TYPE_EDGE_RISING>;
				clocks = <&clkc_periphs CLKID_I2C_M_D>;
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};

			i2c4: i2c@6e000 {
				compatible = "amlogic,meson-axg-i2c";
				reg = <0x0 0x6e000 0x0 0x20>;
				interrupts = <GIC_SPI 164 IRQ_TYPE_EDGE_RISING>;
				clocks = <&clkc_periphs CLKID_I2C_M_E>;
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};

			nand: nand-controller@8c800 {
				compatible = "amlogic,meson-axg-nfc";
				reg = <0x0 0x8c800 0x0 0x100>, <0x0 0x8c000 0x0 0x4>;
				reg-names = "nfc", "emmc";
				interrupts = <GIC_SPI 175 IRQ_TYPE_EDGE_RISING>;
				clocks = <&clkc_periphs CLKID_SD_EMMC_C>,
					<&clkc_pll CLKID_FCLK_DIV2>;
				clock-names = "core", "device";
				status = "disabled";
			};

			uart_b: serial@7a000 {
				compatible = "amlogic,meson-s4-uart",
					     "amlogic,meson-ao-uart";
				reg = <0x0 0x7a000 0x0 0x18>;
				interrupts = <GIC_SPI 169 IRQ_TYPE_EDGE_RISING>;
				clocks = <&xtal>, <&clkc_periphs CLKID_UART_B>, <&xtal>;
				clock-names = "xtal", "pclk", "baud";
				status = "disabled";
			};

			reset: reset-controller@2000 {
				compatible = "amlogic,meson-s4-reset";
				reg = <0x0 0x2000 0x0 0x98>;
				#reset-cells = <1>;
			};

			ir: ir@84040 {
				compatible = "amlogic,meson-s4-ir";
				reg = <0x0 0x84040 0x0 0x30>;
				interrupts = <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
				status = "disabled";
			};

			hwrng: rng@440788 {
				compatible = "amlogic,meson-s4-rng";
				reg = <0x0 0x440788 0x0 0x0c>;
			};
		};

		ethmac: ethernet@fdc00000 {
			compatible = "amlogic,meson-axg-dwmac",
				     "snps,dwmac-3.70a",
				     "snps,dwmac";
			reg = <0x0 0xfdc00000 0x0 0x10000>,
			      <0x0 0xfe024000 0x0 0x8>;

			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "macirq";
			power-domains = <&pwrc PWRC_S4_ETH_ID>;
			clocks = <&clkc_periphs CLKID_ETH>,
				 <&clkc_pll CLKID_FCLK_DIV2>,
				 <&clkc_pll CLKID_MPLL2>;
			clock-names = "stmmaceth", "clkin0", "clkin1";
			rx-fifo-depth = <4096>;
			tx-fifo-depth = <2048>;
			status = "disabled";

			mdio0: mdio {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "snps,dwmac-mdio";
			};
		};
	};
};
Commit	Line	Data
ac4dfd0d XZ	1	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
	2	/*
	3	* Copyright (c) 2021 Amlogic, Inc. All rights reserved.
	4	*/
	5
	6	#include <dt-bindings/interrupt-controller/irq.h>
	7	#include <dt-bindings/interrupt-controller/arm-gic.h>
6383f5a2	8	#include <dt-bindings/gpio/gpio.h>
40ae6729 XZ	9	#include <dt-bindings/gpio/meson-s4-gpio.h>
	10	#include <dt-bindings/clock/amlogic,s4-pll-clkc.h>
	11	#include <dt-bindings/clock/amlogic,s4-peripherals-clkc.h>
	12	#include <dt-bindings/power/meson-s4-power.h>
ac4dfd0d XZ	13
	14	/ {
	15	cpus {
	16	#address-cells = <2>;
	17	#size-cells = <0>;
	18
	19	cpu0: cpu@0 {
	20	device_type = "cpu";
9af9c58a	21	compatible = "arm,cortex-a35";
ac4dfd0d XZ	22	reg = <0x0 0x0>;
	23	enable-method = "psci";
	24	};
	25
	26	cpu1: cpu@1 {
	27	device_type = "cpu";
9af9c58a	28	compatible = "arm,cortex-a35";
ac4dfd0d XZ	29	reg = <0x0 0x1>;
	30	enable-method = "psci";
	31	};
	32
	33	cpu2: cpu@2 {
	34	device_type = "cpu";
9af9c58a	35	compatible = "arm,cortex-a35";
ac4dfd0d XZ	36	reg = <0x0 0x2>;
	37	enable-method = "psci";
	38	};
	39
	40	cpu3: cpu@3 {
	41	device_type = "cpu";
9af9c58a	42	compatible = "arm,cortex-a35";
ac4dfd0d XZ	43	reg = <0x0 0x3>;
	44	enable-method = "psci";
	45	};
	46	};
	47
	48	timer {
	49	compatible = "arm,armv8-timer";
	50	interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
	51	<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
	52	<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
	53	<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>;
	54	};
	55
	56	psci {
	57	compatible = "arm,psci-1.0";
	58	method = "smc";
	59	};
	60
	61	xtal: xtal-clk {
	62	compatible = "fixed-clock";
	63	clock-frequency = <24000000>;
	64	clock-output-names = "xtal";
	65	#clock-cells = <0>;
	66	};
	67
72907de9 XZ	68	firmware {
	69	sm: secure-monitor {
	70	compatible = "amlogic,meson-gxbb-sm";
	71
	72	pwrc: power-controller {
	73	compatible = "amlogic,meson-s4-pwrc";
	74	#power-domain-cells = <1>;
	75	};
	76	};
085f7a29 SJ	77	};
085f7a29 SJ	78
ac4dfd0d XZ	79	soc {
	80	compatible = "simple-bus";
	81	#address-cells = <2>;
	82	#size-cells = <2>;
	83	ranges;
	84
	85	gic: interrupt-controller@fff01000 {
	86	compatible = "arm,gic-400";
	87	#interrupt-cells = <3>;
	88	#address-cells = <0>;
	89	interrupt-controller;
	90	reg = <0x0 0xfff01000 0 0x1000>,
	91	<0x0 0xfff02000 0 0x2000>,
	92	<0x0 0xfff04000 0 0x2000>,
	93	<0x0 0xfff06000 0 0x2000>;
	94	interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_HIGH)>;
	95	};
	96
d1e336ee	97	apb4: bus@fe000000 {
ac4dfd0d XZ	98	compatible = "simple-bus";
	99	reg = <0x0 0xfe000000 0x0 0x480000>;
	100	#address-cells = <2>;
	101	#size-cells = <2>;
	102	ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x480000>;
	103
40ae6729 XZ	104	clkc_periphs: clock-controller@0 {
	105	compatible = "amlogic,s4-peripherals-clkc";
	106	reg = <0x0 0x0 0x0 0x49c>;
	107	clocks = <&clkc_pll CLKID_FCLK_DIV2>,
	108	<&clkc_pll CLKID_FCLK_DIV2P5>,
	109	<&clkc_pll CLKID_FCLK_DIV3>,
	110	<&clkc_pll CLKID_FCLK_DIV4>,
	111	<&clkc_pll CLKID_FCLK_DIV5>,
	112	<&clkc_pll CLKID_FCLK_DIV7>,
	113	<&clkc_pll CLKID_HIFI_PLL>,
	114	<&clkc_pll CLKID_GP0_PLL>,
	115	<&clkc_pll CLKID_MPLL0>,
	116	<&clkc_pll CLKID_MPLL1>,
	117	<&clkc_pll CLKID_MPLL2>,
	118	<&clkc_pll CLKID_MPLL3>,
	119	<&clkc_pll CLKID_HDMI_PLL>,
	120	<&xtal>;
	121	clock-names = "fclk_div2", "fclk_div2p5", "fclk_div3",
	122	"fclk_div4", "fclk_div5", "fclk_div7",
	123	"hifi_pll", "gp0_pll", "mpll0", "mpll1",
	124	"mpll2", "mpll3", "hdmi_pll", "xtal";
	125	#clock-cells = <1>;
	126	};
	127
	128	clkc_pll: clock-controller@8000 {
	129	compatible = "amlogic,s4-pll-clkc";
	130	reg = <0x0 0x8000 0x0 0x1e8>;
	131	clocks = <&xtal>;
	132	clock-names = "xtal";
	133	#clock-cells = <1>;
	134	};
	135
2d66f912 HQ	136	watchdog@2100 {
	137	compatible = "amlogic,s4-wdt", "amlogic,t7-wdt";
	138	reg = <0x0 0x2100 0x0 0x10>;
	139	clocks = <&xtal>;
	140	};
	141
6383f5a2 QS	142	periphs_pinctrl: pinctrl@4000 {
	143	compatible = "amlogic,meson-s4-periphs-pinctrl";
	144	#address-cells = <2>;
	145	#size-cells = <2>;
	146	ranges;
	147
	148	gpio: bank@4000 {
	149	reg = <0x0 0x4000 0x0 0x004c>,
	150	<0x0 0x40c0 0x0 0x0220>;
	151	reg-names = "mux", "gpio";
	152	gpio-controller;
	153	#gpio-cells = <2>;
	154	gpio-ranges = <&periphs_pinctrl 0 0 82>;
	155	};
dc8bc779 ZD	156
	157	remote_pins: remote-pin {
	158	mux {
	159	groups = "remote_in";
	160	function = "remote_in";
	161	bias-disable;
	162	};
	163	};
40ae6729 XZ	164
	165	i2c0_pins1: i2c0-pins1 {
	166	mux {
	167	groups = "i2c0_sda",
	168	"i2c0_scl";
	169	function = "i2c0";
	170	drive-strength-microamp = <3000>;
	171	bias-disable;
	172	};
	173	};
	174
	175	i2c1_pins1: i2c1-pins1 {
	176	mux {
	177	groups = "i2c1_sda_c",
	178	"i2c1_scl_c";
	179	function = "i2c1";
	180	drive-strength-microamp = <3000>;
	181	bias-disable;
	182	};
	183	};
	184
	185	i2c1_pins2: i2c1-pins2 {
	186	mux {
	187	groups = "i2c1_sda_d",
	188	"i2c1_scl_d";
	189	function = "i2c1";
	190	drive-strength-microamp = <3000>;
	191	bias-disable;
	192	};
	193	};
	194
	195	i2c1_pins3: i2c1-pins3 {
	196	mux {
	197	groups = "i2c1_sda_h",
	198	"i2c1_scl_h";
	199	function = "i2c1";
	200	drive-strength-microamp = <3000>;
	201	bias-disable;
	202	};
	203	};
	204
	205	i2c1_pins4: i2c1-pins4 {
	206	mux {
	207	groups = "i2c1_sda_x",
	208	"i2c1_scl_x";
	209	function = "i2c1";
	210	drive-strength-microamp = <3000>;
	211	bias-disable;
	212	};
	213	};
	214
	215	i2c2_pins1: i2c2-pins1 {
	216	mux {
	217	groups = "i2c2_sda_d",
	218	"i2c2_scl_d";
	219	function = "i2c2";
	220	drive-strength-microamp = <3000>;
	221	bias-disable;
	222	};
	223	};
	224
	225	i2c2_pins2: i2c2-pins2 {
	226	mux {
	227	groups = "i2c2_sda_h8",
228	"i2c2_scl_h9";
229	function = "i2c2";
230	drive-strength-microamp = <3000>;
231	bias-disable;
232	};
233	};
234
235	i2c2_pins3: i2c2-pins3 {
236	mux {
237	groups = "i2c2_sda_h0",
238	"i2c2_scl_h1";
239	function = "i2c2";
240	drive-strength-microamp = <3000>;
241	bias-disable;
242	};
243	};
244
245	i2c3_pins1: i2c3-pins1 {
246	mux {
247	groups = "i2c3_sda_x",
248	"i2c3_scl_x";
249	function = "i2c3";
250	drive-strength-microamp = <3000>;
251	bias-disable;
252	};
253	};
254
255	i2c3_pins2: i2c3-pins2 {
256	mux {
257	groups = "i2c3_sda_z",
258	"i2c3_scl_z";
259	function = "i2c3";
260	drive-strength-microamp = <3000>;
261	bias-disable;
262	};
263	};
264
265	i2c4_pins1: i2c4-pins1 {
266	mux {
267	groups = "i2c4_sda_c",
268	"i2c4_scl_c";
269	function = "i2c4";
270	drive-strength-microamp = <3000>;
271	bias-disable;
272	};
273	};
274
275	i2c4_pins2: i2c4-pins2 {
276	mux {
277	groups = "i2c4_sda_d",
278	"i2c4_scl_d";
279	function = "i2c4";
280	drive-strength-microamp = <3000>;
281	bias-disable;
282	};
283	};
284
285	i2c4_pins3: i2c4-pins3 {
286	mux {
287	groups = "i2c4_sda_z",
288	"i2c4_scl_z";
289	function = "i2c4";
290	drive-strength-microamp = <3000>;
291	bias-disable;
292	};
293	};
294
295	nand_pins: nand-pins {
296	mux {
297	groups = "emmc_nand_d0",
298	"emmc_nand_d1",
299	"emmc_nand_d2",
300	"emmc_nand_d3",
301	"emmc_nand_d4",
302	"emmc_nand_d5",
303	"emmc_nand_d6",
304	"emmc_nand_d7",
305	"nand_ce0",
306	"nand_ale",
307	"nand_cle",
308	"nand_wen_clk",
309	"nand_ren_wr";
310	function = "nand";
311	input-enable;
312	};
313	};
314
315	spicc0_pins_x: spicc0-pins_x {
316	mux {
317	groups = "spi_a_mosi_x",
318	"spi_a_miso_x",
319	"spi_a_clk_x";
320	function = "spi_a";
321	drive-strength-microamp = <3000>;
322	};
323	};
324
325	spicc0_pins_h: spicc0-pins-h {
326	mux {
327	groups = "spi_a_mosi_h",
328	"spi_a_miso_h",
329	"spi_a_clk_h";
330	function = "spi_a";
331	drive-strength-microamp = <3000>;
332	};
333	};
334
335	spicc0_pins_z: spicc0-pins-z {
336	mux {
337	groups = "spi_a_mosi_z",
338	"spi_a_miso_z",
339	"spi_a_clk_z";
340	function = "spi_a";
341	drive-strength-microamp = <3000>;
342	};
343	};
344
6383f5a2 QS	345	};
6383f5a2 QS	346
39363393 QS	347	gpio_intc: interrupt-controller@4080 {
	348	compatible = "amlogic,meson-s4-gpio-intc",
	349	"amlogic,meson-gpio-intc";
	350	reg = <0x0 0x4080 0x0 0x20>;
	351	interrupt-controller;
	352	#interrupt-cells = <2>;
	353	amlogic,channel-interrupts =
	354	<10 11 12 13 14 15 16 17 18 19 20 21>;
	355	};
	356
40ae6729 XZ	357	eth_phy: mdio-multiplexer@28000 {
	358	compatible = "amlogic,g12a-mdio-mux";
	359	reg = <0x0 0x28000 0x0 0xa4>;
	360
	361	#address-cells = <1>;
	362	#size-cells = <0>;
	363	clocks = <&clkc_periphs CLKID_ETHPHY>,
	364	<&xtal>,
	365	<&clkc_pll CLKID_MPLL_50M>;
	366	clock-names = "pclk", "clkin0", "clkin1";
	367	mdio-parent-bus = <&mdio0>;
	368
	369	ext_mdio: mdio@0 {
	370	reg = <0>;
	371	#address-cells = <1>;
	372	#size-cells = <0>;
	373	};
	374
	375	int_mdio: mdio@1 {
	376	reg = <1>;
	377	#address-cells = <1>;
	378	#size-cells = <0>;
	379
	380	internal_ephy: ethernet-phy@8 {
	381	compatible = "ethernet-phy-id0180.3301",
	382	"ethernet-phy-ieee802.3-c22";
	383	interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
	384	reg = <8>;
	385	max-speed = <100>;
	386	};
	387	};
	388	};
	389
	390	spicc0: spi@50000 {
	391	compatible = "amlogic,meson-g12a-spicc";
	392	reg = <0x0 0x50000 0x0 0x44>;
	393	interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
	394	clocks = <&clkc_periphs CLKID_SPICC0>,
	395	<&clkc_periphs CLKID_SPICC0_EN>;
	396	clock-names = "core", "pclk";
	397	#address-cells = <1>;
	398	#size-cells = <0>;
	399	status = "disabled";
	400	};
	401
	402	i2c0: i2c@66000 {
	403	compatible = "amlogic,meson-axg-i2c";
	404	reg = <0x0 0x66000 0x0 0x20>;
	405	interrupts = <GIC_SPI 160 IRQ_TYPE_EDGE_RISING>;
	406	clocks = <&clkc_periphs CLKID_I2C_M_A>;
	407	#address-cells = <1>;
	408	#size-cells = <0>;
	409	status = "disabled";
	410	};
	411
	412	i2c1: i2c@68000 {
	413	compatible = "amlogic,meson-axg-i2c";
	414	reg = <0x0 0x68000 0x0 0x20>;
	415	interrupts = <GIC_SPI 161 IRQ_TYPE_EDGE_RISING>;
	416	clocks = <&clkc_periphs CLKID_I2C_M_B>;
	417	#address-cells = <1>;
	418	#size-cells = <0>;
	419	status = "disabled";
	420	};
421
422	i2c2: i2c@6a000 {
423	compatible = "amlogic,meson-axg-i2c";
424	reg = <0x0 0x6a000 0x0 0x20>;
425	interrupts = <GIC_SPI 162 IRQ_TYPE_EDGE_RISING>;
426	clocks = <&clkc_periphs CLKID_I2C_M_C>;
427	#address-cells = <1>;
428	#size-cells = <0>;
429	status = "disabled";
430	};
431
432	i2c3: i2c@6c000 {
433	compatible = "amlogic,meson-axg-i2c";
434	reg = <0x0 0x6c000 0x0 0x20>;
435	interrupts = <GIC_SPI 163 IRQ_TYPE_EDGE_RISING>;
436	clocks = <&clkc_periphs CLKID_I2C_M_D>;
437	#address-cells = <1>;
438	#size-cells = <0>;
439	status = "disabled";
440	};
441
442	i2c4: i2c@6e000 {
443	compatible = "amlogic,meson-axg-i2c";
444	reg = <0x0 0x6e000 0x0 0x20>;
445	interrupts = <GIC_SPI 164 IRQ_TYPE_EDGE_RISING>;
446	clocks = <&clkc_periphs CLKID_I2C_M_E>;
447	#address-cells = <1>;
448	#size-cells = <0>;
449	status = "disabled";
450	};
451
452	nand: nand-controller@8c800 {
453	compatible = "amlogic,meson-axg-nfc";
454	reg = <0x0 0x8c800 0x0 0x100>, <0x0 0x8c000 0x0 0x4>;
455	reg-names = "nfc", "emmc";
456	interrupts = <GIC_SPI 175 IRQ_TYPE_EDGE_RISING>;
457	clocks = <&clkc_periphs CLKID_SD_EMMC_C>,
458	<&clkc_pll CLKID_FCLK_DIV2>;
459	clock-names = "core", "device";
460	status = "disabled";
461	};
462
eb54ef36	463	uart_b: serial@7a000 {
ac4dfd0d XZ	464	compatible = "amlogic,meson-s4-uart",
	465	"amlogic,meson-ao-uart";
	466	reg = <0x0 0x7a000 0x0 0x18>;
	467	interrupts = <GIC_SPI 169 IRQ_TYPE_EDGE_RISING>;
40ae6729	468	clocks = <&xtal>, <&clkc_periphs CLKID_UART_B>, <&xtal>;
ac4dfd0d	469	clock-names = "xtal", "pclk", "baud";
eb54ef36	470	status = "disabled";
ac4dfd0d	471	};
c46952d2 ZD	472
	473	reset: reset-controller@2000 {
	474	compatible = "amlogic,meson-s4-reset";
	475	reg = <0x0 0x2000 0x0 0x98>;
	476	#reset-cells = <1>;
	477	};
dc8bc779 ZD	478
	479	ir: ir@84040 {
	480	compatible = "amlogic,meson-s4-ir";
	481	reg = <0x0 0x84040 0x0 0x30>;
	482	interrupts = <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
	483	status = "disabled";
	484	};
1e3dbe80 AR	485
	486	hwrng: rng@440788 {
	487	compatible = "amlogic,meson-s4-rng";
	488	reg = <0x0 0x440788 0x0 0x0c>;
	489	};
ac4dfd0d	490	};
40ae6729 XZ	491
	492	ethmac: ethernet@fdc00000 {
	493	compatible = "amlogic,meson-axg-dwmac",
	494	"snps,dwmac-3.70a",
	495	"snps,dwmac";
	496	reg = <0x0 0xfdc00000 0x0 0x10000>,
	497	<0x0 0xfe024000 0x0 0x8>;
	498
	499	interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
	500	interrupt-names = "macirq";
	501	power-domains = <&pwrc PWRC_S4_ETH_ID>;
	502	clocks = <&clkc_periphs CLKID_ETH>,
	503	<&clkc_pll CLKID_FCLK_DIV2>,
	504	<&clkc_pll CLKID_MPLL2>;
	505	clock-names = "stmmaceth", "clkin0", "clkin1";
	506	rx-fifo-depth = <4096>;
	507	tx-fifo-depth = <2048>;
	508	status = "disabled";
	509
	510	mdio0: mdio {
	511	#address-cells = <1>;
	512	#size-cells = <0>;
	513	compatible = "snps,dwmac-mdio";
	514	};
	515	};
ac4dfd0d XZ	516	};
ac4dfd0d XZ	517	};