[linux-2.6-block.git] / arch / arm64 / boot / dts / amlogic / meson-gxl.dtsi

/*
 * Copyright (c) 2016 Endless Computers, Inc.
 * Author: Carlo Caione <carlo@endlessm.com>
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This library is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License as
 *     published by the Free Software Foundation; either version 2 of the
 *     License, or (at your option) any later version.
 *
 *     This library is distributed in the hope that it will be useful,
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 * Or, alternatively,
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use,
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
 */

#include "meson-gx.dtsi"
#include <dt-bindings/clock/gxbb-clkc.h>
#include <dt-bindings/gpio/meson-gxl-gpio.h>

/ {
	compatible = "amlogic,meson-gxl";
};

&ethmac {
	reg = <0x0 0xc9410000 0x0 0x10000
	       0x0 0xc8834540 0x0 0x4>;

	clocks = <&clkc CLKID_ETH>,
		 <&clkc CLKID_FCLK_DIV2>,
		 <&clkc CLKID_MPLL2>;
	clock-names = "stmmaceth", "clkin0", "clkin1";

	mdio0: mdio {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "snps,dwmac-mdio";
	};
};

&aobus {
	pinctrl_aobus: pinctrl@14 {
		compatible = "amlogic,meson-gxl-aobus-pinctrl";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		gpio_ao: bank@14 {
			reg = <0x0 0x00014 0x0 0x8>,
			      <0x0 0x0002c 0x0 0x4>,
			      <0x0 0x00024 0x0 0x8>;
			reg-names = "mux", "pull", "gpio";
			gpio-controller;
			#gpio-cells = <2>;
		};

		uart_ao_a_pins: uart_ao_a {
			mux {
				groups = "uart_tx_ao_a", "uart_rx_ao_a";
				function = "uart_ao";
			};
		};

		uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts {
			mux {
				groups = "uart_cts_ao_a",
				       "uart_rts_ao_a";
				function = "uart_ao";
			};
		};

		uart_ao_b_pins: uart_ao_b {
			mux {
				groups = "uart_tx_ao_b", "uart_rx_ao_b";
				function = "uart_ao_b";
			};
		};

		uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts {
			mux {
				groups = "uart_cts_ao_b",
				       "uart_rts_ao_b";
				function = "uart_ao_b";
			};
		};

		remote_input_ao_pins: remote_input_ao {
			mux {
				groups = "remote_input_ao";
				function = "remote_input_ao";
			};
		};

		pwm_ao_a_3_pins: pwm_ao_a_3 {
			mux {
				groups = "pwm_ao_a_3";
				function = "pwm_ao_a";
			};
		};

		pwm_ao_a_8_pins: pwm_ao_a_8 {
			mux {
				groups = "pwm_ao_a_8";
				function = "pwm_ao_a";
			};
		};

		pwm_ao_b_pins: pwm_ao_b {
			mux {
				groups = "pwm_ao_b";
				function = "pwm_ao_b";
			};
		};
	};
};

&periphs {
	pinctrl_periphs: pinctrl@4b0 {
		compatible = "amlogic,meson-gxl-periphs-pinctrl";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		gpio: bank@4b0 {
			reg = <0x0 0x004b0 0x0 0x28>,
			      <0x0 0x004e8 0x0 0x14>,
			      <0x0 0x00120 0x0 0x14>,
			      <0x0 0x00430 0x0 0x40>;
			reg-names = "mux", "pull", "pull-enable", "gpio";
			gpio-controller;
			#gpio-cells = <2>;
		};

		emmc_pins: emmc {
			mux {
				groups = "emmc_nand_d07",
				       "emmc_cmd",
				       "emmc_clk",
				       "emmc_ds";
				function = "emmc";
			};
		};

		sdcard_pins: sdcard {
			mux {
				groups = "sdcard_d0",
				       "sdcard_d1",
				       "sdcard_d2",
				       "sdcard_d3",
				       "sdcard_cmd",
				       "sdcard_clk";
				function = "sdcard";
			};
		};

		sdio_pins: sdio {
			mux {
				groups = "sdio_d0",
				       "sdio_d1",
				       "sdio_d2",
				       "sdio_d3",
				       "sdio_cmd",
				       "sdio_clk";
				function = "sdio";
			};
		};

		sdio_irq_pins: sdio_irq {
			mux {
				groups = "sdio_irq";
				function = "sdio";
			};
		};

		uart_a_pins: uart_a {
			mux {
				groups = "uart_tx_a",
				       "uart_rx_a";
				function = "uart_a";
			};
		};

		uart_a_cts_rts_pins: uart_a_cts_rts {
			mux {
				groups = "uart_cts_a",
				       "uart_rts_a";
				function = "uart_a";
			};
		};

		uart_b_pins: uart_b {
			mux {
				groups = "uart_tx_b",
				       "uart_rx_b";
				function = "uart_b";
			};
		};

		uart_b_cts_rts_pins: uart_b_cts_rts {
			mux {
				groups = "uart_cts_b",
				       "uart_rts_b";
				function = "uart_b";
			};
		};

		uart_c_pins: uart_c {
			mux {
				groups = "uart_tx_c",
				       "uart_rx_c";
				function = "uart_c";
			};
		};

		uart_c_cts_rts_pins: uart_c_cts_rts {
			mux {
				groups = "uart_cts_c",
				       "uart_rts_c";
				function = "uart_c";
			};
		};

		i2c_a_pins: i2c_a {
			mux {
				groups = "i2c_sck_a",
				     "i2c_sda_a";
				function = "i2c_a";
			};
		};

		i2c_b_pins: i2c_b {
			mux {
				groups = "i2c_sck_b",
				      "i2c_sda_b";
				function = "i2c_b";
			};
		};

		i2c_c_pins: i2c_c {
			mux {
				groups = "i2c_sck_c",
				      "i2c_sda_c";
				function = "i2c_c";
			};
		};

		eth_pins: eth_c {
			mux {
				groups = "eth_mdio",
				       "eth_mdc",
				       "eth_clk_rx_clk",
				       "eth_rx_dv",
				       "eth_rxd0",
				       "eth_rxd1",
				       "eth_rxd2",
				       "eth_rxd3",
				       "eth_rgmii_tx_clk",
				       "eth_tx_en",
				       "eth_txd0",
				       "eth_txd1",
				       "eth_txd2",
				       "eth_txd3";
				function = "eth";
			};
		};

		pwm_a_pins: pwm_a {
			mux {
				groups = "pwm_a";
				function = "pwm_a";
			};
		};

		pwm_b_pins: pwm_b {
			mux {
				groups = "pwm_b";
				function = "pwm_b";
			};
		};

		pwm_c_pins: pwm_c {
			mux {
				groups = "pwm_c";
				function = "pwm_c";
			};
		};

		pwm_d_pins: pwm_d {
			mux {
				groups = "pwm_d";
				function = "pwm_d";
			};
		};

		pwm_e_pins: pwm_e {
			mux {
				groups = "pwm_e";
				function = "pwm_e";
			};
		};

		pwm_f_clk_pins: pwm_f_clk {
			mux {
				groups = "pwm_f_clk";
				function = "pwm_f";
			};
		};

		pwm_f_x_pins: pwm_f_x {
			mux {
				groups = "pwm_f_x";
				function = "pwm_f";
			};
		};

		hdmi_hpd_pins: hdmi_hpd {
			mux {
				groups = "hdmi_hpd";
				function = "hdmi_hpd";
			};
		};

		hdmi_i2c_pins: hdmi_i2c {
			mux {
				groups = "hdmi_sda", "hdmi_scl";
				function = "hdmi_i2c";
			};
		};
	};

	eth-phy-mux {
		compatible = "mdio-mux-mmioreg", "mdio-mux";
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0x0 0x55c 0x0 0x4>;
		mux-mask = <0xffffffff>;
		mdio-parent-bus = <&mdio0>;

		internal_mdio: mdio@e40908ff {
			reg = <0xe40908ff>;
			#address-cells = <1>;
			#size-cells = <0>;

			internal_phy: ethernet-phy@8 {
				compatible = "ethernet-phy-id0181.4400", "ethernet-phy-ieee802.3-c22";
				reg = <8>;
				max-speed = <100>;
			};
		};

		external_mdio: mdio@2009087f {
			reg = <0x2009087f>;
			#address-cells = <1>;
			#size-cells = <0>;
		};
	};
};

&hiubus {
	clkc: clock-controller@0 {
		compatible = "amlogic,gxl-clkc", "amlogic,gxbb-clkc";
		#clock-cells = <1>;
		reg = <0x0 0x0 0x0 0x3db>;
	};
};

&i2c_A {
	clocks = <&clkc CLKID_I2C>;
};

&i2c_AO {
	clocks = <&clkc CLKID_AO_I2C>;
};

&i2c_B {
	clocks = <&clkc CLKID_I2C>;
};

&i2c_C {
	clocks = <&clkc CLKID_I2C>;
};

&saradc {
	compatible = "amlogic,meson-gxl-saradc", "amlogic,meson-saradc";
	clocks = <&xtal>,
		 <&clkc CLKID_SAR_ADC>,
		 <&clkc CLKID_SANA>,
		 <&clkc CLKID_SAR_ADC_CLK>,
		 <&clkc CLKID_SAR_ADC_SEL>;
	clock-names = "clkin", "core", "sana", "adc_clk", "adc_sel";
};

&sd_emmc_a {
	clocks = <&clkc CLKID_SD_EMMC_A>,
		 <&xtal>,
		 <&clkc CLKID_FCLK_DIV2>;
	clock-names = "core", "clkin0", "clkin1";
};

&sd_emmc_b {
	clocks = <&clkc CLKID_SD_EMMC_B>,
		 <&xtal>,
		 <&clkc CLKID_FCLK_DIV2>;
       clock-names = "core", "clkin0", "clkin1";
};

&sd_emmc_c {
	clocks = <&clkc CLKID_SD_EMMC_C>,
		 <&xtal>,
		 <&clkc CLKID_FCLK_DIV2>;
	clock-names = "core", "clkin0", "clkin1";
};

&spifc {
	clocks = <&clkc CLKID_SPI>;
};

&vpu {
	compatible = "amlogic,meson-gxl-vpu", "amlogic,meson-gx-vpu";
};
Commit	Line	Data
15abee8a CC	1	/*
	2	* Copyright (c) 2016 Endless Computers, Inc.
	3	* Author: Carlo Caione <carlo@endlessm.com>
	4	*
	5	* This file is dual-licensed: you can use it either under the terms
	6	* of the GPL or the X11 license, at your option. Note that this dual
	7	* licensing only applies to this file, and not this project as a
	8	* whole.
	9	*
	10	* a) This library is free software; you can redistribute it and/or
	11	* modify it under the terms of the GNU General Public License as
	12	* published by the Free Software Foundation; either version 2 of the
	13	* License, or (at your option) any later version.
	14	*
	15	* This library is distributed in the hope that it will be useful,
	16	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	18	* GNU General Public License for more details.
	19	*
	20	* Or, alternatively,
	21	*
	22	* b) Permission is hereby granted, free of charge, to any person
	23	* obtaining a copy of this software and associated documentation
	24	* files (the "Software"), to deal in the Software without
	25	* restriction, including without limitation the rights to use,
	26	* copy, modify, merge, publish, distribute, sublicense, and/or
	27	* sell copies of the Software, and to permit persons to whom the
	28	* Software is furnished to do so, subject to the following
	29	* conditions:
	30	*
	31	* The above copyright notice and this permission notice shall be
	32	* included in all copies or substantial portions of the Software.
	33	*
	34	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	35	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
	36	* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	37	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
	38	* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
	39	* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	40	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	41	* OTHER DEALINGS IN THE SOFTWARE.
	42	*/
	43
	44	#include "meson-gx.dtsi"
973fbd55	45	#include <dt-bindings/clock/gxbb-clkc.h>
1cf3df8a	46	#include <dt-bindings/gpio/meson-gxl-gpio.h>
15abee8a CC	47
	48	/ {
	49	compatible = "amlogic,meson-gxl";
	50	};
fb0fe922	51
e9e27c64 NA	52	&ethmac {
	53	reg = <0x0 0xc9410000 0x0 0x10000
	54	0x0 0xc8834540 0x0 0x4>;
	55
	56	clocks = <&clkc CLKID_ETH>,
	57	<&clkc CLKID_FCLK_DIV2>,
	58	<&clkc CLKID_MPLL2>;
	59	clock-names = "stmmaceth", "clkin0", "clkin1";
	60
	61	mdio0: mdio {
	62	#address-cells = <1>;
	63	#size-cells = <0>;
	64	compatible = "snps,dwmac-mdio";
	65	};
	66	};
	67
fb0fe922 NA	68	&aobus {
	69	pinctrl_aobus: pinctrl@14 {
	70	compatible = "amlogic,meson-gxl-aobus-pinctrl";
	71	#address-cells = <2>;
	72	#size-cells = <2>;
	73	ranges;
	74
	75	gpio_ao: bank@14 {
	76	reg = <0x0 0x00014 0x0 0x8>,
	77	<0x0 0x0002c 0x0 0x4>,
	78	<0x0 0x00024 0x0 0x8>;
	79	reg-names = "mux", "pull", "gpio";
	80	gpio-controller;
	81	#gpio-cells = <2>;
	82	};
	83
	84	uart_ao_a_pins: uart_ao_a {
	85	mux {
	86	groups = "uart_tx_ao_a", "uart_rx_ao_a";
	87	function = "uart_ao";
	88	};
	89	};
	90
261e1d5c MB	91	uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts {
	92	mux {
	93	groups = "uart_cts_ao_a",
	94	"uart_rts_ao_a";
	95	function = "uart_ao";
	96	};
	97	};
	98
890a96a2 MB	99	uart_ao_b_pins: uart_ao_b {
	100	mux {
	101	groups = "uart_tx_ao_b", "uart_rx_ao_b";
	102	function = "uart_ao_b";
	103	};
	104	};
	105
261e1d5c MB	106	uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts {
	107	mux {
	108	groups = "uart_cts_ao_b",
	109	"uart_rts_ao_b";
	110	function = "uart_ao_b";
	111	};
	112	};
	113
fb0fe922 NA	114	remote_input_ao_pins: remote_input_ao {
	115	mux {
	116	groups = "remote_input_ao";
	117	function = "remote_input_ao";
	118	};
	119	};
249a2243	120
e98fd134 MB	121	pwm_ao_a_3_pins: pwm_ao_a_3 {
	122	mux {
	123	groups = "pwm_ao_a_3";
	124	function = "pwm_ao_a";
	125	};
	126	};
	127
	128	pwm_ao_a_8_pins: pwm_ao_a_8 {
	129	mux {
	130	groups = "pwm_ao_a_8";
	131	function = "pwm_ao_a";
	132	};
	133	};
	134
249a2243 MB	135	pwm_ao_b_pins: pwm_ao_b {
	136	mux {
	137	groups = "pwm_ao_b";
	138	function = "pwm_ao_b";
	139	};
	140	};
fb0fe922 NA	141	};
	142	};
	143
	144	&periphs {
	145	pinctrl_periphs: pinctrl@4b0 {
	146	compatible = "amlogic,meson-gxl-periphs-pinctrl";
	147	#address-cells = <2>;
	148	#size-cells = <2>;
	149	ranges;
	150
	151	gpio: bank@4b0 {
	152	reg = <0x0 0x004b0 0x0 0x28>,
	153	<0x0 0x004e8 0x0 0x14>,
	154	<0x0 0x00120 0x0 0x14>,
	155	<0x0 0x00430 0x0 0x40>;
	156	reg-names = "mux", "pull", "pull-enable", "gpio";
	157	gpio-controller;
	158	#gpio-cells = <2>;
	159	};
	160
	161	emmc_pins: emmc {
	162	mux {
	163	groups = "emmc_nand_d07",
	164	"emmc_cmd",
	165	"emmc_clk",
	166	"emmc_ds";
	167	function = "emmc";
	168	};
	169	};
	170
	171	sdcard_pins: sdcard {
	172	mux {
	173	groups = "sdcard_d0",
	174	"sdcard_d1",
	175	"sdcard_d2",
	176	"sdcard_d3",
	177	"sdcard_cmd",
	178	"sdcard_clk";
	179	function = "sdcard";
	180	};
	181	};
	182
	183	sdio_pins: sdio {
	184	mux {
	185	groups = "sdio_d0",
	186	"sdio_d1",
	187	"sdio_d2",
	188	"sdio_d3",
	189	"sdio_cmd",
	190	"sdio_clk";
	191	function = "sdio";
	192	};
	193	};
	194
	195	sdio_irq_pins: sdio_irq {
	196	mux {
	197	groups = "sdio_irq";
	198	function = "sdio";
	199	};
	200	};
	201
	202	uart_a_pins: uart_a {
	203	mux {
	204	groups = "uart_tx_a",
205	"uart_rx_a";
206	function = "uart_a";
207	};
208	};
209
261e1d5c MB	210	uart_a_cts_rts_pins: uart_a_cts_rts {
	211	mux {
	212	groups = "uart_cts_a",
	213	"uart_rts_a";
	214	function = "uart_a";
	215	};
	216	};
	217
fb0fe922 NA	218	uart_b_pins: uart_b {
	219	mux {
	220	groups = "uart_tx_b",
	221	"uart_rx_b";
	222	function = "uart_b";
	223	};
	224	};
	225
261e1d5c MB	226	uart_b_cts_rts_pins: uart_b_cts_rts {
	227	mux {
	228	groups = "uart_cts_b",
	229	"uart_rts_b";
	230	function = "uart_b";
	231	};
	232	};
	233
fb0fe922 NA	234	uart_c_pins: uart_c {
	235	mux {
	236	groups = "uart_tx_c",
	237	"uart_rx_c";
	238	function = "uart_c";
	239	};
	240	};
	241
261e1d5c MB	242	uart_c_cts_rts_pins: uart_c_cts_rts {
	243	mux {
	244	groups = "uart_cts_c",
	245	"uart_rts_c";
	246	function = "uart_c";
	247	};
	248	};
	249
fb0fe922 NA	250	i2c_a_pins: i2c_a {
	251	mux {
	252	groups = "i2c_sck_a",
	253	"i2c_sda_a";
	254	function = "i2c_a";
	255	};
	256	};
	257
	258	i2c_b_pins: i2c_b {
	259	mux {
	260	groups = "i2c_sck_b",
	261	"i2c_sda_b";
	262	function = "i2c_b";
	263	};
	264	};
	265
	266	i2c_c_pins: i2c_c {
	267	mux {
	268	groups = "i2c_sck_c",
	269	"i2c_sda_c";
	270	function = "i2c_c";
	271	};
	272	};
	273
	274	eth_pins: eth_c {
	275	mux {
	276	groups = "eth_mdio",
	277	"eth_mdc",
	278	"eth_clk_rx_clk",
	279	"eth_rx_dv",
	280	"eth_rxd0",
	281	"eth_rxd1",
	282	"eth_rxd2",
	283	"eth_rxd3",
	284	"eth_rgmii_tx_clk",
	285	"eth_tx_en",
	286	"eth_txd0",
	287	"eth_txd1",
	288	"eth_txd2",
	289	"eth_txd3";
	290	function = "eth";
	291	};
	292	};
	293
e98fd134 MB	294	pwm_a_pins: pwm_a {
	295	mux {
	296	groups = "pwm_a";
	297	function = "pwm_a";
	298	};
	299	};
	300
	301	pwm_b_pins: pwm_b {
	302	mux {
	303	groups = "pwm_b";
	304	function = "pwm_b";
	305	};
	306	};
	307
	308	pwm_c_pins: pwm_c {
	309	mux {
	310	groups = "pwm_c";
	311	function = "pwm_c";
	312	};
	313	};
	314
	315	pwm_d_pins: pwm_d {
	316	mux {
	317	groups = "pwm_d";
	318	function = "pwm_d";
	319	};
	320	};
	321
fb0fe922 NA	322	pwm_e_pins: pwm_e {
	323	mux {
	324	groups = "pwm_e";
	325	function = "pwm_e";
	326	};
	327	};
b949165c	328
e98fd134 MB	329	pwm_f_clk_pins: pwm_f_clk {
	330	mux {
	331	groups = "pwm_f_clk";
	332	function = "pwm_f";
	333	};
	334	};
	335
	336	pwm_f_x_pins: pwm_f_x {
	337	mux {
	338	groups = "pwm_f_x";
	339	function = "pwm_f";
	340	};
	341	};
	342
b949165c NA	343	hdmi_hpd_pins: hdmi_hpd {
	344	mux {
	345	groups = "hdmi_hpd";
	346	function = "hdmi_hpd";
	347	};
	348	};
	349
	350	hdmi_i2c_pins: hdmi_i2c {
	351	mux {
	352	groups = "hdmi_sda", "hdmi_scl";
	353	function = "hdmi_i2c";
	354	};
	355	};
fb0fe922	356	};
e9e27c64 NA	357
	358	eth-phy-mux {
	359	compatible = "mdio-mux-mmioreg", "mdio-mux";
	360	#address-cells = <1>;
	361	#size-cells = <0>;
	362	reg = <0x0 0x55c 0x0 0x4>;
	363	mux-mask = <0xffffffff>;
	364	mdio-parent-bus = <&mdio0>;
	365
	366	internal_mdio: mdio@e40908ff {
	367	reg = <0xe40908ff>;
	368	#address-cells = <1>;
	369	#size-cells = <0>;
	370
	371	internal_phy: ethernet-phy@8 {
	372	compatible = "ethernet-phy-id0181.4400", "ethernet-phy-ieee802.3-c22";
	373	reg = <8>;
	374	max-speed = <100>;
	375	};
	376	};
	377
	378	external_mdio: mdio@2009087f {
	379	reg = <0x2009087f>;
	380	#address-cells = <1>;
	381	#size-cells = <0>;
	382	};
	383	};
fb0fe922	384	};
973fbd55 NA	385
	386	&hiubus {
	387	clkc: clock-controller@0 {
	388	compatible = "amlogic,gxl-clkc", "amlogic,gxbb-clkc";
	389	#clock-cells = <1>;
	390	reg = <0x0 0x0 0x0 0x3db>;
	391	};
	392	};
5d28bb01 NA	393
	394	&i2c_A {
	395	clocks = <&clkc CLKID_I2C>;
	396	};
	397
04b36df4 NA	398	&i2c_AO {
	399	clocks = <&clkc CLKID_AO_I2C>;
	400	};
	401
5d28bb01 NA	402	&i2c_B {
	403	clocks = <&clkc CLKID_I2C>;
	404	};
	405
	406	&i2c_C {
	407	clocks = <&clkc CLKID_I2C>;
	408	};
6d489dc8	409
bd80ef5e MB	410	&saradc {
	411	compatible = "amlogic,meson-gxl-saradc", "amlogic,meson-saradc";
	412	clocks = <&xtal>,
	413	<&clkc CLKID_SAR_ADC>,
	414	<&clkc CLKID_SANA>,
	415	<&clkc CLKID_SAR_ADC_CLK>,
	416	<&clkc CLKID_SAR_ADC_SEL>;
	417	clock-names = "clkin", "core", "sana", "adc_clk", "adc_sel";
	418	};
	419
6d489dc8 NA	420	&sd_emmc_a {
	421	clocks = <&clkc CLKID_SD_EMMC_A>,
	422	<&xtal>,
	423	<&clkc CLKID_FCLK_DIV2>;
	424	clock-names = "core", "clkin0", "clkin1";
	425	};
	426
	427	&sd_emmc_b {
	428	clocks = <&clkc CLKID_SD_EMMC_B>,
	429	<&xtal>,
	430	<&clkc CLKID_FCLK_DIV2>;
	431	clock-names = "core", "clkin0", "clkin1";
	432	};
	433
	434	&sd_emmc_c {
	435	clocks = <&clkc CLKID_SD_EMMC_C>,
	436	<&xtal>,
	437	<&clkc CLKID_FCLK_DIV2>;
	438	clock-names = "core", "clkin0", "clkin1";
	439	};
fafdbdf7	440
04b36df4 NA	441	&spifc {
	442	clocks = <&clkc CLKID_SPI>;
	443	};
	444
fafdbdf7 NA	445	&vpu {
	446	compatible = "amlogic,meson-gxl-vpu", "amlogic,meson-gx-vpu";
	447	};