Commit | Line | Data |
---|---|---|
15abee8a CC |
1 | /* |
2 | * Copyright (c) 2016 Endless Computers, Inc. | |
3 | * Author: Carlo Caione <carlo@endlessm.com> | |
4 | * | |
5 | * This file is dual-licensed: you can use it either under the terms | |
6 | * of the GPL or the X11 license, at your option. Note that this dual | |
7 | * licensing only applies to this file, and not this project as a | |
8 | * whole. | |
9 | * | |
10 | * a) This library is free software; you can redistribute it and/or | |
11 | * modify it under the terms of the GNU General Public License as | |
12 | * published by the Free Software Foundation; either version 2 of the | |
13 | * License, or (at your option) any later version. | |
14 | * | |
15 | * This library is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | * GNU General Public License for more details. | |
19 | * | |
20 | * Or, alternatively, | |
21 | * | |
22 | * b) Permission is hereby granted, free of charge, to any person | |
23 | * obtaining a copy of this software and associated documentation | |
24 | * files (the "Software"), to deal in the Software without | |
25 | * restriction, including without limitation the rights to use, | |
26 | * copy, modify, merge, publish, distribute, sublicense, and/or | |
27 | * sell copies of the Software, and to permit persons to whom the | |
28 | * Software is furnished to do so, subject to the following | |
29 | * conditions: | |
30 | * | |
31 | * The above copyright notice and this permission notice shall be | |
32 | * included in all copies or substantial portions of the Software. | |
33 | * | |
34 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
35 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES | |
36 | * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
37 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT | |
38 | * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, | |
39 | * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
40 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
41 | * OTHER DEALINGS IN THE SOFTWARE. | |
42 | */ | |
43 | ||
44 | #include "meson-gx.dtsi" | |
973fbd55 | 45 | #include <dt-bindings/clock/gxbb-clkc.h> |
1cf3df8a | 46 | #include <dt-bindings/gpio/meson-gxl-gpio.h> |
6939db7e | 47 | #include <dt-bindings/reset/amlogic,meson-gxbb-reset.h> |
15abee8a CC |
48 | |
49 | / { | |
50 | compatible = "amlogic,meson-gxl"; | |
51 | }; | |
fb0fe922 | 52 | |
e9e27c64 NA |
53 | ðmac { |
54 | reg = <0x0 0xc9410000 0x0 0x10000 | |
55 | 0x0 0xc8834540 0x0 0x4>; | |
56 | ||
57 | clocks = <&clkc CLKID_ETH>, | |
58 | <&clkc CLKID_FCLK_DIV2>, | |
59 | <&clkc CLKID_MPLL2>; | |
60 | clock-names = "stmmaceth", "clkin0", "clkin1"; | |
61 | ||
62 | mdio0: mdio { | |
63 | #address-cells = <1>; | |
64 | #size-cells = <0>; | |
65 | compatible = "snps,dwmac-mdio"; | |
66 | }; | |
67 | }; | |
68 | ||
fb0fe922 NA |
69 | &aobus { |
70 | pinctrl_aobus: pinctrl@14 { | |
71 | compatible = "amlogic,meson-gxl-aobus-pinctrl"; | |
72 | #address-cells = <2>; | |
73 | #size-cells = <2>; | |
74 | ranges; | |
75 | ||
76 | gpio_ao: bank@14 { | |
77 | reg = <0x0 0x00014 0x0 0x8>, | |
78 | <0x0 0x0002c 0x0 0x4>, | |
79 | <0x0 0x00024 0x0 0x8>; | |
80 | reg-names = "mux", "pull", "gpio"; | |
81 | gpio-controller; | |
82 | #gpio-cells = <2>; | |
84412e4e | 83 | gpio-ranges = <&pinctrl_aobus 0 0 14>; |
fb0fe922 NA |
84 | }; |
85 | ||
86 | uart_ao_a_pins: uart_ao_a { | |
87 | mux { | |
88 | groups = "uart_tx_ao_a", "uart_rx_ao_a"; | |
89 | function = "uart_ao"; | |
90 | }; | |
91 | }; | |
92 | ||
261e1d5c MB |
93 | uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts { |
94 | mux { | |
95 | groups = "uart_cts_ao_a", | |
96 | "uart_rts_ao_a"; | |
97 | function = "uart_ao"; | |
98 | }; | |
99 | }; | |
100 | ||
890a96a2 MB |
101 | uart_ao_b_pins: uart_ao_b { |
102 | mux { | |
103 | groups = "uart_tx_ao_b", "uart_rx_ao_b"; | |
104 | function = "uart_ao_b"; | |
105 | }; | |
106 | }; | |
107 | ||
ca02e3f9 NA |
108 | uart_ao_b_0_1_pins: uart_ao_b_0_1 { |
109 | mux { | |
110 | groups = "uart_tx_ao_b_0", "uart_rx_ao_b_1"; | |
111 | function = "uart_ao_b"; | |
112 | }; | |
113 | }; | |
114 | ||
261e1d5c MB |
115 | uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts { |
116 | mux { | |
117 | groups = "uart_cts_ao_b", | |
118 | "uart_rts_ao_b"; | |
119 | function = "uart_ao_b"; | |
120 | }; | |
121 | }; | |
122 | ||
fb0fe922 NA |
123 | remote_input_ao_pins: remote_input_ao { |
124 | mux { | |
125 | groups = "remote_input_ao"; | |
126 | function = "remote_input_ao"; | |
127 | }; | |
128 | }; | |
249a2243 | 129 | |
ca02e3f9 NA |
130 | i2c_ao_pins: i2c_ao { |
131 | mux { | |
132 | groups = "i2c_sck_ao", | |
133 | "i2c_sda_ao"; | |
134 | function = "i2c_ao"; | |
135 | }; | |
136 | }; | |
137 | ||
e98fd134 MB |
138 | pwm_ao_a_3_pins: pwm_ao_a_3 { |
139 | mux { | |
140 | groups = "pwm_ao_a_3"; | |
141 | function = "pwm_ao_a"; | |
142 | }; | |
143 | }; | |
144 | ||
145 | pwm_ao_a_8_pins: pwm_ao_a_8 { | |
146 | mux { | |
147 | groups = "pwm_ao_a_8"; | |
148 | function = "pwm_ao_a"; | |
149 | }; | |
150 | }; | |
151 | ||
249a2243 MB |
152 | pwm_ao_b_pins: pwm_ao_b { |
153 | mux { | |
154 | groups = "pwm_ao_b"; | |
155 | function = "pwm_ao_b"; | |
156 | }; | |
157 | }; | |
ca02e3f9 NA |
158 | |
159 | pwm_ao_b_6_pins: pwm_ao_b_6 { | |
160 | mux { | |
161 | groups = "pwm_ao_b_6"; | |
162 | function = "pwm_ao_b"; | |
163 | }; | |
164 | }; | |
c16fe9a1 | 165 | |
166 | i2s_out_ch23_ao_pins: i2s_out_ch23_ao { | |
167 | mux { | |
168 | groups = "i2s_out_ch23_ao"; | |
169 | function = "i2s_out_ao"; | |
170 | }; | |
171 | }; | |
172 | ||
173 | i2s_out_ch45_ao_pins: i2s_out_ch45_ao { | |
174 | mux { | |
175 | groups = "i2s_out_ch45_ao"; | |
176 | function = "i2s_out_ao"; | |
177 | }; | |
178 | }; | |
9503062d | 179 | |
180 | spdif_out_ao_6_pins: spdif_out_ao_6 { | |
181 | mux { | |
182 | groups = "spdif_out_ao_6"; | |
183 | function = "spdif_out_ao"; | |
184 | }; | |
185 | }; | |
186 | ||
187 | spdif_out_ao_9_pins: spdif_out_ao_9 { | |
188 | mux { | |
189 | groups = "spdif_out_ao_9"; | |
190 | function = "spdif_out_ao"; | |
191 | }; | |
192 | }; | |
6d717619 NA |
193 | |
194 | ao_cec_pins: ao_cec { | |
195 | mux { | |
196 | groups = "ao_cec"; | |
197 | function = "cec_ao"; | |
198 | }; | |
199 | }; | |
200 | ||
201 | ee_cec_pins: ee_cec { | |
202 | mux { | |
203 | groups = "ee_cec"; | |
204 | function = "cec_ao"; | |
205 | }; | |
206 | }; | |
fb0fe922 NA |
207 | }; |
208 | }; | |
209 | ||
6a573c4e AF |
210 | &hdmi_tx { |
211 | compatible = "amlogic,meson-gxl-dw-hdmi", "amlogic,meson-gx-dw-hdmi"; | |
212 | resets = <&reset RESET_HDMITX_CAPB3>, | |
213 | <&reset RESET_HDMI_SYSTEM_RESET>, | |
214 | <&reset RESET_HDMI_TX>; | |
215 | reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy"; | |
216 | clocks = <&clkc CLKID_HDMI_PCLK>, | |
217 | <&clkc CLKID_CLK81>, | |
218 | <&clkc CLKID_GCLK_VENCI_INT0>; | |
219 | clock-names = "isfr", "iahb", "venci"; | |
220 | }; | |
221 | ||
222 | &hiubus { | |
223 | clkc: clock-controller@0 { | |
224 | compatible = "amlogic,gxl-clkc", "amlogic,gxbb-clkc"; | |
225 | #clock-cells = <1>; | |
226 | reg = <0x0 0x0 0x0 0x3db>; | |
227 | }; | |
228 | }; | |
229 | ||
230 | &i2c_A { | |
231 | clocks = <&clkc CLKID_I2C>; | |
232 | }; | |
233 | ||
234 | &i2c_AO { | |
235 | clocks = <&clkc CLKID_AO_I2C>; | |
236 | }; | |
237 | ||
238 | &i2c_B { | |
239 | clocks = <&clkc CLKID_I2C>; | |
240 | }; | |
241 | ||
242 | &i2c_C { | |
243 | clocks = <&clkc CLKID_I2C>; | |
244 | }; | |
245 | ||
fb0fe922 NA |
246 | &periphs { |
247 | pinctrl_periphs: pinctrl@4b0 { | |
248 | compatible = "amlogic,meson-gxl-periphs-pinctrl"; | |
249 | #address-cells = <2>; | |
250 | #size-cells = <2>; | |
251 | ranges; | |
252 | ||
253 | gpio: bank@4b0 { | |
254 | reg = <0x0 0x004b0 0x0 0x28>, | |
255 | <0x0 0x004e8 0x0 0x14>, | |
f4c406d5 | 256 | <0x0 0x00520 0x0 0x14>, |
fb0fe922 NA |
257 | <0x0 0x00430 0x0 0x40>; |
258 | reg-names = "mux", "pull", "pull-enable", "gpio"; | |
259 | gpio-controller; | |
260 | #gpio-cells = <2>; | |
d79a079c | 261 | gpio-ranges = <&pinctrl_periphs 0 10 101>; |
fb0fe922 NA |
262 | }; |
263 | ||
264 | emmc_pins: emmc { | |
265 | mux { | |
266 | groups = "emmc_nand_d07", | |
267 | "emmc_cmd", | |
268 | "emmc_clk", | |
269 | "emmc_ds"; | |
270 | function = "emmc"; | |
271 | }; | |
272 | }; | |
273 | ||
ca02e3f9 NA |
274 | nor_pins: nor { |
275 | mux { | |
276 | groups = "nor_d", | |
277 | "nor_q", | |
278 | "nor_c", | |
279 | "nor_cs"; | |
280 | function = "nor"; | |
281 | }; | |
282 | }; | |
283 | ||
85b2e743 NA |
284 | spi_pins: spi { |
285 | mux { | |
286 | groups = "spi_miso", | |
287 | "spi_mosi", | |
288 | "spi_sclk"; | |
289 | function = "spi"; | |
290 | }; | |
291 | }; | |
292 | ||
293 | spi_ss0_pins: spi-ss0 { | |
294 | mux { | |
295 | groups = "spi_ss0"; | |
296 | function = "spi"; | |
297 | }; | |
298 | }; | |
299 | ||
fb0fe922 NA |
300 | sdcard_pins: sdcard { |
301 | mux { | |
302 | groups = "sdcard_d0", | |
303 | "sdcard_d1", | |
304 | "sdcard_d2", | |
305 | "sdcard_d3", | |
306 | "sdcard_cmd", | |
307 | "sdcard_clk"; | |
308 | function = "sdcard"; | |
309 | }; | |
310 | }; | |
311 | ||
312 | sdio_pins: sdio { | |
313 | mux { | |
314 | groups = "sdio_d0", | |
315 | "sdio_d1", | |
316 | "sdio_d2", | |
317 | "sdio_d3", | |
318 | "sdio_cmd", | |
319 | "sdio_clk"; | |
320 | function = "sdio"; | |
321 | }; | |
322 | }; | |
323 | ||
324 | sdio_irq_pins: sdio_irq { | |
325 | mux { | |
326 | groups = "sdio_irq"; | |
327 | function = "sdio"; | |
328 | }; | |
329 | }; | |
330 | ||
331 | uart_a_pins: uart_a { | |
332 | mux { | |
333 | groups = "uart_tx_a", | |
334 | "uart_rx_a"; | |
335 | function = "uart_a"; | |
336 | }; | |
337 | }; | |
338 | ||
261e1d5c MB |
339 | uart_a_cts_rts_pins: uart_a_cts_rts { |
340 | mux { | |
341 | groups = "uart_cts_a", | |
342 | "uart_rts_a"; | |
343 | function = "uart_a"; | |
344 | }; | |
345 | }; | |
346 | ||
fb0fe922 NA |
347 | uart_b_pins: uart_b { |
348 | mux { | |
349 | groups = "uart_tx_b", | |
350 | "uart_rx_b"; | |
351 | function = "uart_b"; | |
352 | }; | |
353 | }; | |
354 | ||
261e1d5c MB |
355 | uart_b_cts_rts_pins: uart_b_cts_rts { |
356 | mux { | |
357 | groups = "uart_cts_b", | |
358 | "uart_rts_b"; | |
359 | function = "uart_b"; | |
360 | }; | |
361 | }; | |
362 | ||
fb0fe922 NA |
363 | uart_c_pins: uart_c { |
364 | mux { | |
365 | groups = "uart_tx_c", | |
366 | "uart_rx_c"; | |
367 | function = "uart_c"; | |
368 | }; | |
369 | }; | |
370 | ||
261e1d5c MB |
371 | uart_c_cts_rts_pins: uart_c_cts_rts { |
372 | mux { | |
373 | groups = "uart_cts_c", | |
374 | "uart_rts_c"; | |
375 | function = "uart_c"; | |
376 | }; | |
377 | }; | |
378 | ||
fb0fe922 NA |
379 | i2c_a_pins: i2c_a { |
380 | mux { | |
381 | groups = "i2c_sck_a", | |
382 | "i2c_sda_a"; | |
383 | function = "i2c_a"; | |
384 | }; | |
385 | }; | |
386 | ||
387 | i2c_b_pins: i2c_b { | |
388 | mux { | |
389 | groups = "i2c_sck_b", | |
390 | "i2c_sda_b"; | |
391 | function = "i2c_b"; | |
392 | }; | |
393 | }; | |
394 | ||
395 | i2c_c_pins: i2c_c { | |
396 | mux { | |
397 | groups = "i2c_sck_c", | |
398 | "i2c_sda_c"; | |
399 | function = "i2c_c"; | |
400 | }; | |
401 | }; | |
402 | ||
403 | eth_pins: eth_c { | |
404 | mux { | |
405 | groups = "eth_mdio", | |
406 | "eth_mdc", | |
407 | "eth_clk_rx_clk", | |
408 | "eth_rx_dv", | |
409 | "eth_rxd0", | |
410 | "eth_rxd1", | |
411 | "eth_rxd2", | |
412 | "eth_rxd3", | |
413 | "eth_rgmii_tx_clk", | |
414 | "eth_tx_en", | |
415 | "eth_txd0", | |
416 | "eth_txd1", | |
417 | "eth_txd2", | |
418 | "eth_txd3"; | |
419 | function = "eth"; | |
420 | }; | |
421 | }; | |
422 | ||
44ddadc3 NA |
423 | eth_link_led_pins: eth_link_led { |
424 | mux { | |
425 | groups = "eth_link_led"; | |
426 | function = "eth_led"; | |
427 | }; | |
428 | }; | |
429 | ||
430 | eth_act_led_pins: eth_act_led { | |
431 | mux { | |
432 | groups = "eth_act_led"; | |
433 | function = "eth_led"; | |
434 | }; | |
435 | }; | |
436 | ||
e98fd134 MB |
437 | pwm_a_pins: pwm_a { |
438 | mux { | |
439 | groups = "pwm_a"; | |
440 | function = "pwm_a"; | |
441 | }; | |
442 | }; | |
443 | ||
444 | pwm_b_pins: pwm_b { | |
445 | mux { | |
446 | groups = "pwm_b"; | |
447 | function = "pwm_b"; | |
448 | }; | |
449 | }; | |
450 | ||
451 | pwm_c_pins: pwm_c { | |
452 | mux { | |
453 | groups = "pwm_c"; | |
454 | function = "pwm_c"; | |
455 | }; | |
456 | }; | |
457 | ||
458 | pwm_d_pins: pwm_d { | |
459 | mux { | |
460 | groups = "pwm_d"; | |
461 | function = "pwm_d"; | |
462 | }; | |
463 | }; | |
464 | ||
fb0fe922 NA |
465 | pwm_e_pins: pwm_e { |
466 | mux { | |
467 | groups = "pwm_e"; | |
468 | function = "pwm_e"; | |
469 | }; | |
470 | }; | |
b949165c | 471 | |
e98fd134 MB |
472 | pwm_f_clk_pins: pwm_f_clk { |
473 | mux { | |
474 | groups = "pwm_f_clk"; | |
475 | function = "pwm_f"; | |
476 | }; | |
477 | }; | |
478 | ||
479 | pwm_f_x_pins: pwm_f_x { | |
480 | mux { | |
481 | groups = "pwm_f_x"; | |
482 | function = "pwm_f"; | |
483 | }; | |
484 | }; | |
485 | ||
b949165c NA |
486 | hdmi_hpd_pins: hdmi_hpd { |
487 | mux { | |
488 | groups = "hdmi_hpd"; | |
489 | function = "hdmi_hpd"; | |
490 | }; | |
491 | }; | |
492 | ||
493 | hdmi_i2c_pins: hdmi_i2c { | |
494 | mux { | |
495 | groups = "hdmi_sda", "hdmi_scl"; | |
496 | function = "hdmi_i2c"; | |
497 | }; | |
498 | }; | |
c16fe9a1 | 499 | |
500 | i2s_am_clk_pins: i2s_am_clk { | |
501 | mux { | |
502 | groups = "i2s_am_clk"; | |
503 | function = "i2s_out"; | |
504 | }; | |
505 | }; | |
506 | ||
507 | i2s_out_ao_clk_pins: i2s_out_ao_clk { | |
508 | mux { | |
509 | groups = "i2s_out_ao_clk"; | |
510 | function = "i2s_out"; | |
511 | }; | |
512 | }; | |
513 | ||
514 | i2s_out_lr_clk_pins: i2s_out_lr_clk { | |
515 | mux { | |
516 | groups = "i2s_out_lr_clk"; | |
517 | function = "i2s_out"; | |
518 | }; | |
519 | }; | |
520 | ||
521 | i2s_out_ch01_pins: i2s_out_ch01 { | |
522 | mux { | |
523 | groups = "i2s_out_ch01"; | |
524 | function = "i2s_out"; | |
525 | }; | |
526 | }; | |
527 | i2sout_ch23_z_pins: i2sout_ch23_z { | |
528 | mux { | |
529 | groups = "i2sout_ch23_z"; | |
530 | function = "i2s_out"; | |
531 | }; | |
532 | }; | |
533 | ||
534 | i2sout_ch45_z_pins: i2sout_ch45_z { | |
535 | mux { | |
536 | groups = "i2sout_ch45_z"; | |
537 | function = "i2s_out"; | |
538 | }; | |
539 | }; | |
540 | ||
541 | i2sout_ch67_z_pins: i2sout_ch67_z { | |
542 | mux { | |
543 | groups = "i2sout_ch67_z"; | |
544 | function = "i2s_out"; | |
545 | }; | |
546 | }; | |
9503062d | 547 | |
548 | spdif_out_h_pins: spdif_out_ao_h { | |
549 | mux { | |
550 | groups = "spdif_out_h"; | |
551 | function = "spdif_out"; | |
552 | }; | |
553 | }; | |
fb0fe922 | 554 | }; |
e9e27c64 NA |
555 | |
556 | eth-phy-mux { | |
557 | compatible = "mdio-mux-mmioreg", "mdio-mux"; | |
558 | #address-cells = <1>; | |
559 | #size-cells = <0>; | |
560 | reg = <0x0 0x55c 0x0 0x4>; | |
561 | mux-mask = <0xffffffff>; | |
562 | mdio-parent-bus = <&mdio0>; | |
563 | ||
564 | internal_mdio: mdio@e40908ff { | |
565 | reg = <0xe40908ff>; | |
566 | #address-cells = <1>; | |
567 | #size-cells = <0>; | |
568 | ||
569 | internal_phy: ethernet-phy@8 { | |
570 | compatible = "ethernet-phy-id0181.4400", "ethernet-phy-ieee802.3-c22"; | |
571 | reg = <8>; | |
572 | max-speed = <100>; | |
573 | }; | |
574 | }; | |
575 | ||
576 | external_mdio: mdio@2009087f { | |
577 | reg = <0x2009087f>; | |
578 | #address-cells = <1>; | |
579 | #size-cells = <0>; | |
580 | }; | |
581 | }; | |
fb0fe922 | 582 | }; |
973fbd55 | 583 | |
bd80ef5e MB |
584 | &saradc { |
585 | compatible = "amlogic,meson-gxl-saradc", "amlogic,meson-saradc"; | |
586 | clocks = <&xtal>, | |
587 | <&clkc CLKID_SAR_ADC>, | |
588 | <&clkc CLKID_SANA>, | |
589 | <&clkc CLKID_SAR_ADC_CLK>, | |
590 | <&clkc CLKID_SAR_ADC_SEL>; | |
591 | clock-names = "clkin", "core", "sana", "adc_clk", "adc_sel"; | |
592 | }; | |
593 | ||
6d489dc8 NA |
594 | &sd_emmc_a { |
595 | clocks = <&clkc CLKID_SD_EMMC_A>, | |
596 | <&xtal>, | |
597 | <&clkc CLKID_FCLK_DIV2>; | |
598 | clock-names = "core", "clkin0", "clkin1"; | |
599 | }; | |
600 | ||
601 | &sd_emmc_b { | |
602 | clocks = <&clkc CLKID_SD_EMMC_B>, | |
603 | <&xtal>, | |
604 | <&clkc CLKID_FCLK_DIV2>; | |
605 | clock-names = "core", "clkin0", "clkin1"; | |
606 | }; | |
607 | ||
608 | &sd_emmc_c { | |
609 | clocks = <&clkc CLKID_SD_EMMC_C>, | |
610 | <&xtal>, | |
611 | <&clkc CLKID_FCLK_DIV2>; | |
612 | clock-names = "core", "clkin0", "clkin1"; | |
613 | }; | |
fafdbdf7 | 614 | |
fa808631 NA |
615 | &spicc { |
616 | clocks = <&clkc CLKID_SPICC>; | |
617 | clock-names = "core"; | |
618 | resets = <&reset RESET_PERIPHS_SPICC>; | |
619 | num-cs = <1>; | |
620 | }; | |
621 | ||
04b36df4 NA |
622 | &spifc { |
623 | clocks = <&clkc CLKID_SPI>; | |
624 | }; | |
625 | ||
f72d6f60 HK |
626 | &uart_A { |
627 | clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>; | |
628 | clock-names = "xtal", "core", "baud"; | |
629 | }; | |
630 | ||
631 | &uart_AO { | |
632 | clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>; | |
633 | clock-names = "xtal", "pclk", "baud"; | |
634 | }; | |
635 | ||
636 | &uart_AO_B { | |
637 | clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>; | |
638 | clock-names = "xtal", "pclk", "baud"; | |
639 | }; | |
640 | ||
641 | &uart_B { | |
642 | clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>; | |
643 | clock-names = "xtal", "core", "baud"; | |
644 | }; | |
645 | ||
646 | &uart_C { | |
647 | clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>; | |
648 | clock-names = "xtal", "core", "baud"; | |
649 | }; | |
650 | ||
fafdbdf7 NA |
651 | &vpu { |
652 | compatible = "amlogic,meson-gxl-vpu", "amlogic,meson-gx-vpu"; | |
653 | }; |