[linux-2.6-block.git] / arch / arm64 / boot / dts / amlogic / meson-gxbb.dtsi

/*
 * Copyright (c) 2016 Andreas Färber
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This library is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License as
 *     published by the Free Software Foundation; either version 2 of the
 *     License, or (at your option) any later version.
 *
 *     This library is distributed in the hope that it will be useful,
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 * Or, alternatively,
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use,
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
 */

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/gpio/meson-gxbb-gpio.h>
#include <dt-bindings/reset/amlogic,meson-gxbb-reset.h>
#include <dt-bindings/clock/gxbb-clkc.h>

/ {
	compatible = "amlogic,meson-gxbb";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	cpus {
		#address-cells = <0x2>;
		#size-cells = <0x0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a53", "arm,armv8";
			reg = <0x0 0x0>;
			enable-method = "psci";
		};

		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a53", "arm,armv8";
			reg = <0x0 0x1>;
			enable-method = "psci";
		};

		cpu2: cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a53", "arm,armv8";
			reg = <0x0 0x2>;
			enable-method = "psci";
		};

		cpu3: cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a53", "arm,armv8";
			reg = <0x0 0x3>;
			enable-method = "psci";
		};
	};

	arm-pmu {
		compatible = "arm,cortex-a53-pmu";
		interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
	};

	psci {
		compatible = "arm,psci-0.2";
		method = "smc";
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13
			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_EDGE_RISING)>,
			     <GIC_PPI 14
			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_EDGE_RISING)>,
			     <GIC_PPI 11
			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_EDGE_RISING)>,
			     <GIC_PPI 10
			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_EDGE_RISING)>;
	};

	xtal: xtal-clk {
		compatible = "fixed-clock";
		clock-frequency = <24000000>;
		clock-output-names = "xtal";
		#clock-cells = <0>;
	};

	soc {
		compatible = "simple-bus";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		cbus: cbus@c1100000 {
			compatible = "simple-bus";
			reg = <0x0 0xc1100000 0x0 0x100000>;
			#address-cells = <2>;
			#size-cells = <2>;
			ranges = <0x0 0x0 0x0 0xc1100000 0x0 0x100000>;

			reset: reset-controller@4404 {
				compatible = "amlogic,meson-gxbb-reset";
				reg = <0x0 0x04404 0x0 0x20>;
				#reset-cells = <1>;
			};

			uart_A: serial@84c0 {
				compatible = "amlogic,meson-uart";
				reg = <0x0 0x84c0 0x0 0x14>;
				interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
				clocks = <&xtal>;
				status = "disabled";
			};

			uart_B: serial@84dc {
				compatible = "amlogic,meson-uart";
				reg = <0x0 0x84dc 0x0 0x14>;
				interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
				clocks = <&xtal>;
				status = "disabled";
			};

			uart_C: serial@8700 {
				compatible = "amlogic,meson-uart";
				reg = <0x0 0x8700 0x0 0x14>;
				interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>;
				clocks = <&xtal>;
				status = "disabled";
			};

			watchdog@98d0 {
				compatible = "amlogic,meson-gxbb-wdt";
				reg = <0x0 0x098d0 0x0 0x10>;
				clocks = <&xtal>;
			};
		};

		gic: interrupt-controller@c4301000 {
			compatible = "arm,gic-400";
			reg = <0x0 0xc4301000 0 0x1000>,
			      <0x0 0xc4302000 0 0x2000>,
			      <0x0 0xc4304000 0 0x2000>,
			      <0x0 0xc4306000 0 0x2000>;
			interrupt-controller;
			interrupts = <GIC_PPI 9
				(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
			#interrupt-cells = <3>;
			#address-cells = <0>;
		};

		aobus: aobus@c8100000 {
			compatible = "simple-bus";
			reg = <0x0 0xc8100000 0x0 0x100000>;
			#address-cells = <2>;
			#size-cells = <2>;
			ranges = <0x0 0x0 0x0 0xc8100000 0x0 0x100000>;

			pinctrl_aobus: pinctrl@14 {
				compatible = "amlogic,meson-gxbb-aobus-pinctrl";
				#address-cells = <2>;
				#size-cells = <2>;
				ranges;

				gpio_ao: bank@14 {
					reg = <0x0 0x00014 0x0 0x8>,
					      <0x0 0x0002c 0x0 0x4>,
					      <0x0 0x00024 0x0 0x8>;
					reg-names = "mux", "pull", "gpio";
					gpio-controller;
					#gpio-cells = <2>;
				};

				uart_ao_a_pins: uart_ao_a {
					mux {
						groups = "uart_tx_ao_a", "uart_rx_ao_a";
						function = "uart_ao";
					};
				};
			};

			uart_AO: serial@4c0 {
				compatible = "amlogic,meson-uart";
				reg = <0x0 0x004c0 0x0 0x14>;
				interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
				clocks = <&xtal>;
				status = "disabled";
			};
		};

		periphs: periphs@c8834000 {
			compatible = "simple-bus";
			reg = <0x0 0xc8834000 0x0 0x2000>;
			#address-cells = <2>;
			#size-cells = <2>;
			ranges = <0x0 0x0 0x0 0xc8834000 0x0 0x2000>;

			rng {
				compatible = "amlogic,meson-rng";
				reg = <0x0 0x0 0x0 0x4>;
			};

			pinctrl_periphs: pinctrl@4b0 {
				compatible = "amlogic,meson-gxbb-periphs-pinctrl";
				#address-cells = <2>;
				#size-cells = <2>;
				ranges;

				gpio: bank@4b0 {
					reg = <0x0 0x004b0 0x0 0x28>,
					      <0x0 0x004e8 0x0 0x14>,
					      <0x0 0x00120 0x0 0x14>,
					      <0x0 0x00430 0x0 0x40>;
					reg-names = "mux", "pull", "pull-enable", "gpio";
					gpio-controller;
					#gpio-cells = <2>;
				};

				emmc_pins: emmc {
					mux {
						groups = "emmc_nand_d07",
						       "emmc_cmd",
						       "emmc_clk";
						function = "emmc";
					};
				};

				sdcard_pins: sdcard {
					mux {
						groups = "sdcard_d0",
						       "sdcard_d1",
						       "sdcard_d2",
						       "sdcard_d3",
						       "sdcard_cmd",
						       "sdcard_clk";
						function = "sdcard";
					};
				};

				uart_a_pins: uart_a {
					mux {
						groups = "uart_tx_a",
						       "uart_rx_a";
						function = "uart_a";
					};
				};

				uart_b_pins: uart_b {
					mux {
						groups = "uart_tx_b",
						       "uart_rx_b";
						function = "uart_b";
					};
				};

				uart_c_pins: uart_c {
					mux {
						groups = "uart_tx_c",
						       "uart_rx_c";
						function = "uart_c";
					};
				};

				eth_pins: eth_c {
					mux {
						groups = "eth_mdio",
						       "eth_mdc",
						       "eth_clk_rx_clk",
						       "eth_rx_dv",
						       "eth_rxd0",
						       "eth_rxd1",
						       "eth_rxd2",
						       "eth_rxd3",
						       "eth_rgmii_tx_clk",
						       "eth_tx_en",
						       "eth_txd0",
						       "eth_txd1",
						       "eth_txd2",
						       "eth_txd3";
						function = "eth";
					};
				};
			};
		};

		hiubus: hiubus@c883c000 {
			compatible = "simple-bus";
			reg = <0x0 0xc883c000 0x0 0x2000>;
			#address-cells = <2>;
			#size-cells = <2>;
			ranges = <0x0 0x0 0x0 0xc883c000 0x0 0x2000>;

			clkc: clock-controller@0 {
				compatible = "amlogic,gxbb-clkc";
				#clock-cells = <1>;
				reg = <0x0 0x0 0x0 0x3db>;
			};
		};

		apb: apb@d0000000 {
			compatible = "simple-bus";
			reg = <0x0 0xd0000000 0x0 0x200000>;
			#address-cells = <2>;
			#size-cells = <2>;
			ranges = <0x0 0x0 0x0 0xd0000000 0x0 0x200000>;
		};

		ethmac: ethernet@c9410000 {
			compatible = "amlogic,meson6-dwmac", "snps,dwmac";
			reg = <0x0 0xc9410000 0x0 0x10000
			       0x0 0xc8834540 0x0 0x4>;
			interrupts = <0 8 1>;
			interrupt-names = "macirq";
			clocks = <&clkc CLKID_ETH>;
			clock-names = "stmmaceth";
			phy-mode = "rgmii";
			status = "disabled";
		};
	};
};
Commit	Line	Data
4f24eda8 AF	1	/*
	2	* Copyright (c) 2016 Andreas Färber
	3	*
	4	* This file is dual-licensed: you can use it either under the terms
	5	* of the GPL or the X11 license, at your option. Note that this dual
	6	* licensing only applies to this file, and not this project as a
	7	* whole.
	8	*
	9	* a) This library is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License as
	11	* published by the Free Software Foundation; either version 2 of the
	12	* License, or (at your option) any later version.
	13	*
	14	* This library is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* Or, alternatively,
	20	*
	21	* b) Permission is hereby granted, free of charge, to any person
	22	* obtaining a copy of this software and associated documentation
	23	* files (the "Software"), to deal in the Software without
	24	* restriction, including without limitation the rights to use,
	25	* copy, modify, merge, publish, distribute, sublicense, and/or
	26	* sell copies of the Software, and to permit persons to whom the
	27	* Software is furnished to do so, subject to the following
	28	* conditions:
	29	*
	30	* The above copyright notice and this permission notice shall be
	31	* included in all copies or substantial portions of the Software.
	32	*
	33	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	34	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
	35	* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	36	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
	37	* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
	38	* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	39	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	40	* OTHER DEALINGS IN THE SOFTWARE.
	41	*/
	42
	43	#include <dt-bindings/gpio/gpio.h>
	44	#include <dt-bindings/interrupt-controller/irq.h>
	45	#include <dt-bindings/interrupt-controller/arm-gic.h>
f40d437f	46	#include <dt-bindings/gpio/meson-gxbb-gpio.h>
6d1a5c93	47	#include <dt-bindings/reset/amlogic,meson-gxbb-reset.h>
c3929b72	48	#include <dt-bindings/clock/gxbb-clkc.h>
4f24eda8 AF	49
	50	/ {
	51	compatible = "amlogic,meson-gxbb";
	52	interrupt-parent = <&gic>;
	53	#address-cells = <2>;
	54	#size-cells = <2>;
	55
4f24eda8 AF	56	cpus {
	57	#address-cells = <0x2>;
	58	#size-cells = <0x0>;
	59
	60	cpu0: cpu@0 {
	61	device_type = "cpu";
	62	compatible = "arm,cortex-a53", "arm,armv8";
	63	reg = <0x0 0x0>;
	64	enable-method = "psci";
	65	};
	66
	67	cpu1: cpu@1 {
	68	device_type = "cpu";
	69	compatible = "arm,cortex-a53", "arm,armv8";
	70	reg = <0x0 0x1>;
	71	enable-method = "psci";
	72	};
	73
	74	cpu2: cpu@2 {
	75	device_type = "cpu";
	76	compatible = "arm,cortex-a53", "arm,armv8";
	77	reg = <0x0 0x2>;
	78	enable-method = "psci";
	79	};
	80
	81	cpu3: cpu@3 {
	82	device_type = "cpu";
	83	compatible = "arm,cortex-a53", "arm,armv8";
	84	reg = <0x0 0x3>;
	85	enable-method = "psci";
	86	};
	87	};
	88
	89	arm-pmu {
	90	compatible = "arm,cortex-a53-pmu";
	91	interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
	92	<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
	93	<GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
	94	<GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
	95	interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
	96	};
	97
	98	psci {
	99	compatible = "arm,psci-0.2";
	100	method = "smc";
	101	};
	102
	103	timer {
	104	compatible = "arm,armv8-timer";
	105	interrupts = <GIC_PPI 13
	106	(GIC_CPU_MASK_RAW(0xff) \| IRQ_TYPE_EDGE_RISING)>,
	107	<GIC_PPI 14
	108	(GIC_CPU_MASK_RAW(0xff) \| IRQ_TYPE_EDGE_RISING)>,
	109	<GIC_PPI 11
	110	(GIC_CPU_MASK_RAW(0xff) \| IRQ_TYPE_EDGE_RISING)>,
	111	<GIC_PPI 10
	112	(GIC_CPU_MASK_RAW(0xff) \| IRQ_TYPE_EDGE_RISING)>;
	113	};
	114
	115	xtal: xtal-clk {
	116	compatible = "fixed-clock";
	117	clock-frequency = <24000000>;
	118	clock-output-names = "xtal";
	119	#clock-cells = <0>;
120	};
121
122	soc {
123	compatible = "simple-bus";
124	#address-cells = <2>;
125	#size-cells = <2>;
126	ranges;
127
128	cbus: cbus@c1100000 {
129	compatible = "simple-bus";
130	reg = <0x0 0xc1100000 0x0 0x100000>;
131	#address-cells = <2>;
132	#size-cells = <2>;
133	ranges = <0x0 0x0 0x0 0xc1100000 0x0 0x100000>;
134
6d1a5c93 NA	135	reset: reset-controller@4404 {
	136	compatible = "amlogic,meson-gxbb-reset";
	137	reg = <0x0 0x04404 0x0 0x20>;
	138	#reset-cells = <1>;
	139	};
	140
4f24eda8 AF	141	uart_A: serial@84c0 {
4f24eda8 AF	142	compatible = "amlogic,meson-uart";
8e6320dd	143	reg = <0x0 0x84c0 0x0 0x14>;
4f24eda8 AF	144	interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
	145	clocks = <&xtal>;
	146	status = "disabled";
	147	};
8e6320dd KH	148
	149	uart_B: serial@84dc {
	150	compatible = "amlogic,meson-uart";
	151	reg = <0x0 0x84dc 0x0 0x14>;
	152	interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
	153	clocks = <&xtal>;
	154	status = "disabled";
	155	};
	156
	157	uart_C: serial@8700 {
	158	compatible = "amlogic,meson-uart";
	159	reg = <0x0 0x8700 0x0 0x14>;
	160	interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>;
	161	clocks = <&xtal>;
	162	status = "disabled";
	163	};
f759b640 NA	164
	165	watchdog@98d0 {
	166	compatible = "amlogic,meson-gxbb-wdt";
	167	reg = <0x0 0x098d0 0x0 0x10>;
	168	clocks = <&xtal>;
	169	};
4f24eda8 AF	170	};
	171
	172	gic: interrupt-controller@c4301000 {
	173	compatible = "arm,gic-400";
	174	reg = <0x0 0xc4301000 0 0x1000>,
	175	<0x0 0xc4302000 0 0x2000>,
	176	<0x0 0xc4304000 0 0x2000>,
	177	<0x0 0xc4306000 0 0x2000>;
	178	interrupt-controller;
	179	interrupts = <GIC_PPI 9
	180	(GIC_CPU_MASK_SIMPLE(8) \| IRQ_TYPE_LEVEL_HIGH)>;
	181	#interrupt-cells = <3>;
	182	#address-cells = <0>;
	183	};
	184
	185	aobus: aobus@c8100000 {
	186	compatible = "simple-bus";
	187	reg = <0x0 0xc8100000 0x0 0x100000>;
	188	#address-cells = <2>;
	189	#size-cells = <2>;
	190	ranges = <0x0 0x0 0x0 0xc8100000 0x0 0x100000>;
	191
f40d437f CC	192	pinctrl_aobus: pinctrl@14 {
	193	compatible = "amlogic,meson-gxbb-aobus-pinctrl";
	194	#address-cells = <2>;
	195	#size-cells = <2>;
	196	ranges;
	197
	198	gpio_ao: bank@14 {
	199	reg = <0x0 0x00014 0x0 0x8>,
	200	<0x0 0x0002c 0x0 0x4>,
	201	<0x0 0x00024 0x0 0x8>;
	202	reg-names = "mux", "pull", "gpio";
	203	gpio-controller;
	204	#gpio-cells = <2>;
	205	};
	206
	207	uart_ao_a_pins: uart_ao_a {
	208	mux {
	209	groups = "uart_tx_ao_a", "uart_rx_ao_a";
	210	function = "uart_ao";
	211	};
	212	};
	213	};
	214
4f24eda8 AF	215	uart_AO: serial@4c0 {
	216	compatible = "amlogic,meson-uart";
	217	reg = <0x0 0x004c0 0x0 0x14>;
	218	interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
	219	clocks = <&xtal>;
	220	status = "disabled";
	221	};
	222	};
	223
fab6b48c CC	224	periphs: periphs@c8834000 {
	225	compatible = "simple-bus";
	226	reg = <0x0 0xc8834000 0x0 0x2000>;
	227	#address-cells = <2>;
	228	#size-cells = <2>;
	229	ranges = <0x0 0x0 0x0 0xc8834000 0x0 0x2000>;
f40d437f	230
4b7bed38 NA	231	rng {
	232	compatible = "amlogic,meson-rng";
	233	reg = <0x0 0x0 0x0 0x4>;
	234	};
	235
f40d437f CC	236	pinctrl_periphs: pinctrl@4b0 {
	237	compatible = "amlogic,meson-gxbb-periphs-pinctrl";
	238	#address-cells = <2>;
	239	#size-cells = <2>;
	240	ranges;
	241
	242	gpio: bank@4b0 {
	243	reg = <0x0 0x004b0 0x0 0x28>,
	244	<0x0 0x004e8 0x0 0x14>,
	245	<0x0 0x00120 0x0 0x14>,
	246	<0x0 0x00430 0x0 0x40>;
	247	reg-names = "mux", "pull", "pull-enable", "gpio";
	248	gpio-controller;
	249	#gpio-cells = <2>;
	250	};
a8025ed6 KH	251
	252	emmc_pins: emmc {
	253	mux {
	254	groups = "emmc_nand_d07",
	255	"emmc_cmd",
	256	"emmc_clk";
	257	function = "emmc";
	258	};
	259	};
	260
	261	sdcard_pins: sdcard {
	262	mux {
	263	groups = "sdcard_d0",
	264	"sdcard_d1",
	265	"sdcard_d2",
	266	"sdcard_d3",
	267	"sdcard_cmd",
	268	"sdcard_clk";
	269	function = "sdcard";
	270	};
	271	};
8e6320dd KH	272
	273	uart_a_pins: uart_a {
	274	mux {
	275	groups = "uart_tx_a",
	276	"uart_rx_a";
	277	function = "uart_a";
	278	};
	279	};
	280
	281	uart_b_pins: uart_b {
	282	mux {
	283	groups = "uart_tx_b",
	284	"uart_rx_b";
	285	function = "uart_b";
	286	};
	287	};
	288
	289	uart_c_pins: uart_c {
	290	mux {
	291	groups = "uart_tx_c",
	292	"uart_rx_c";
	293	function = "uart_c";
	294	};
	295	};
8c5509f0 KH	296
	297	eth_pins: eth_c {
	298	mux {
	299	groups = "eth_mdio",
	300	"eth_mdc",
	301	"eth_clk_rx_clk",
	302	"eth_rx_dv",
	303	"eth_rxd0",
	304	"eth_rxd1",
	305	"eth_rxd2",
	306	"eth_rxd3",
	307	"eth_rgmii_tx_clk",
	308	"eth_tx_en",
	309	"eth_txd0",
	310	"eth_txd1",
	311	"eth_txd2",
	312	"eth_txd3";
	313	function = "eth";
	314	};
	315	};
f40d437f	316	};
fab6b48c CC	317	};
	318
	319	hiubus: hiubus@c883c000 {
	320	compatible = "simple-bus";
	321	reg = <0x0 0xc883c000 0x0 0x2000>;
	322	#address-cells = <2>;
	323	#size-cells = <2>;
	324	ranges = <0x0 0x0 0x0 0xc883c000 0x0 0x2000>;
ba6a6c7f MT	325
	326	clkc: clock-controller@0 {
	327	compatible = "amlogic,gxbb-clkc";
	328	#clock-cells = <1>;
	329	reg = <0x0 0x0 0x0 0x3db>;
	330	};
fab6b48c CC	331	};
fab6b48c CC	332
4f24eda8 AF	333	apb: apb@d0000000 {
	334	compatible = "simple-bus";
	335	reg = <0x0 0xd0000000 0x0 0x200000>;
	336	#address-cells = <2>;
	337	#size-cells = <2>;
	338	ranges = <0x0 0x0 0x0 0xd0000000 0x0 0x200000>;
	339	};
8c5509f0 KH	340
	341	ethmac: ethernet@c9410000 {
	342	compatible = "amlogic,meson6-dwmac", "snps,dwmac";
	343	reg = <0x0 0xc9410000 0x0 0x10000
	344	0x0 0xc8834540 0x0 0x4>;
	345	interrupts = <0 8 1>;
	346	interrupt-names = "macirq";
c3929b72	347	clocks = <&clkc CLKID_ETH>;
8c5509f0 KH	348	clock-names = "stmmaceth";
	349	phy-mode = "rgmii";
	350	status = "disabled";
	351	};
4f24eda8 AF	352	};
4f24eda8 AF	353	};