[linux-2.6-block.git] / arch / arm64 / boot / dts / amlogic / meson-gxbb.dtsi

/*
 * Copyright (c) 2016 Andreas Färber
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This library is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License as
 *     published by the Free Software Foundation; either version 2 of the
 *     License, or (at your option) any later version.
 *
 *     This library is distributed in the hope that it will be useful,
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 * Or, alternatively,
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use,
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
 */

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/gpio/meson-gxbb-gpio.h>
#include <dt-bindings/reset/amlogic,meson-gxbb-reset.h>
#include <dt-bindings/clock/gxbb-clkc.h>
#include <dt-bindings/clock/gxbb-aoclkc.h>
#include <dt-bindings/reset/gxbb-aoclkc.h>

/ {
	compatible = "amlogic,meson-gxbb";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	cpus {
		#address-cells = <0x2>;
		#size-cells = <0x0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a53", "arm,armv8";
			reg = <0x0 0x0>;
			enable-method = "psci";
		};

		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a53", "arm,armv8";
			reg = <0x0 0x1>;
			enable-method = "psci";
		};

		cpu2: cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a53", "arm,armv8";
			reg = <0x0 0x2>;
			enable-method = "psci";
		};

		cpu3: cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a53", "arm,armv8";
			reg = <0x0 0x3>;
			enable-method = "psci";
		};
	};

	arm-pmu {
		compatible = "arm,cortex-a53-pmu";
		interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
	};

	psci {
		compatible = "arm,psci-0.2";
		method = "smc";
	};

	firmware {
		sm: secure-monitor {
			compatible = "amlogic,meson-gxbb-sm";
		};
	};

	efuse: efuse {
		compatible = "amlogic,meson-gxbb-efuse";
		#address-cells = <1>;
		#size-cells = <1>;

		sn: sn@14 {
			reg = <0x14 0x10>;
		};

		eth_mac: eth_mac@34 {
			reg = <0x34 0x10>;
		};

		bid: bid@46 {
			reg = <0x46 0x30>;
		};
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13
			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_EDGE_RISING)>,
			     <GIC_PPI 14
			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_EDGE_RISING)>,
			     <GIC_PPI 11
			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_EDGE_RISING)>,
			     <GIC_PPI 10
			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_EDGE_RISING)>;
	};

	xtal: xtal-clk {
		compatible = "fixed-clock";
		clock-frequency = <24000000>;
		clock-output-names = "xtal";
		#clock-cells = <0>;
	};

	soc {
		compatible = "simple-bus";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		cbus: cbus@c1100000 {
			compatible = "simple-bus";
			reg = <0x0 0xc1100000 0x0 0x100000>;
			#address-cells = <2>;
			#size-cells = <2>;
			ranges = <0x0 0x0 0x0 0xc1100000 0x0 0x100000>;

			reset: reset-controller@4404 {
				compatible = "amlogic,meson-gxbb-reset";
				reg = <0x0 0x04404 0x0 0x20>;
				#reset-cells = <1>;
			};

			uart_A: serial@84c0 {
				compatible = "amlogic,meson-uart";
				reg = <0x0 0x84c0 0x0 0x14>;
				interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
				clocks = <&xtal>;
				status = "disabled";
			};

			uart_B: serial@84dc {
				compatible = "amlogic,meson-uart";
				reg = <0x0 0x84dc 0x0 0x14>;
				interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
				clocks = <&xtal>;
				status = "disabled";
			};

			uart_C: serial@8700 {
				compatible = "amlogic,meson-uart";
				reg = <0x0 0x8700 0x0 0x14>;
				interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>;
				clocks = <&xtal>;
				status = "disabled";
			};

			watchdog@98d0 {
				compatible = "amlogic,meson-gxbb-wdt";
				reg = <0x0 0x098d0 0x0 0x10>;
				clocks = <&xtal>;
			};
		};

		gic: interrupt-controller@c4301000 {
			compatible = "arm,gic-400";
			reg = <0x0 0xc4301000 0 0x1000>,
			      <0x0 0xc4302000 0 0x2000>,
			      <0x0 0xc4304000 0 0x2000>,
			      <0x0 0xc4306000 0 0x2000>;
			interrupt-controller;
			interrupts = <GIC_PPI 9
				(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
			#interrupt-cells = <3>;
			#address-cells = <0>;
		};

		aobus: aobus@c8100000 {
			compatible = "simple-bus";
			reg = <0x0 0xc8100000 0x0 0x100000>;
			#address-cells = <2>;
			#size-cells = <2>;
			ranges = <0x0 0x0 0x0 0xc8100000 0x0 0x100000>;

			pinctrl_aobus: pinctrl@14 {
				compatible = "amlogic,meson-gxbb-aobus-pinctrl";
				#address-cells = <2>;
				#size-cells = <2>;
				ranges;

				gpio_ao: bank@14 {
					reg = <0x0 0x00014 0x0 0x8>,
					      <0x0 0x0002c 0x0 0x4>,
					      <0x0 0x00024 0x0 0x8>;
					reg-names = "mux", "pull", "gpio";
					gpio-controller;
					#gpio-cells = <2>;
				};

				uart_ao_a_pins: uart_ao_a {
					mux {
						groups = "uart_tx_ao_a", "uart_rx_ao_a";
						function = "uart_ao";
					};
				};

				remote_input_ao_pins: remote_input_ao {
					mux {
						groups = "remote_input_ao";
						function = "remote_input_ao";
					};
				};

				pwm_ao_a_3_pins: pwm_ao_a_3 {
					mux {
						groups = "pwm_ao_a_3";
						function = "pwm_ao_a_3";
					};
				};

				pwm_ao_a_6_pins: pwm_ao_a_6 {
					mux {
						groups = "pwm_ao_a_6";
						function = "pwm_ao_a_6";
					};
				};

				pwm_ao_a_12_pins: pwm_ao_a_12 {
					mux {
						groups = "pwm_ao_a_12";
						function = "pwm_ao_a_12";
					};
				};

				pwm_ao_b_pins: pwm_ao_b {
					mux {
						groups = "pwm_ao_b";
						function = "pwm_ao_b";
					};
				};
			};

			clkc_AO: clock-controller@040 {
				compatible = "amlogic,gxbb-aoclkc";
				reg = <0x0 0x00040 0x0 0x4>;
				#clock-cells = <1>;
				#reset-cells = <1>;
			};

			uart_AO: serial@4c0 {
				compatible = "amlogic,meson-uart";
				reg = <0x0 0x004c0 0x0 0x14>;
				interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
				clocks = <&xtal>;
				status = "disabled";
			};

			ir: ir@580 {
				compatible = "amlogic,meson-gxbb-ir";
				reg = <0x0 0x00580 0x0 0x40>;
				interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>;
				status = "disabled";
			};
		};

		periphs: periphs@c8834000 {
			compatible = "simple-bus";
			reg = <0x0 0xc8834000 0x0 0x2000>;
			#address-cells = <2>;
			#size-cells = <2>;
			ranges = <0x0 0x0 0x0 0xc8834000 0x0 0x2000>;

			rng {
				compatible = "amlogic,meson-rng";
				reg = <0x0 0x0 0x0 0x4>;
			};

			pinctrl_periphs: pinctrl@4b0 {
				compatible = "amlogic,meson-gxbb-periphs-pinctrl";
				#address-cells = <2>;
				#size-cells = <2>;
				ranges;

				gpio: bank@4b0 {
					reg = <0x0 0x004b0 0x0 0x28>,
					      <0x0 0x004e8 0x0 0x14>,
					      <0x0 0x00120 0x0 0x14>,
					      <0x0 0x00430 0x0 0x40>;
					reg-names = "mux", "pull", "pull-enable", "gpio";
					gpio-controller;
					#gpio-cells = <2>;
				};

				emmc_pins: emmc {
					mux {
						groups = "emmc_nand_d07",
						       "emmc_cmd",
						       "emmc_clk";
						function = "emmc";
					};
				};

				sdcard_pins: sdcard {
					mux {
						groups = "sdcard_d0",
						       "sdcard_d1",
						       "sdcard_d2",
						       "sdcard_d3",
						       "sdcard_cmd",
						       "sdcard_clk";
						function = "sdcard";
					};
				};

				uart_a_pins: uart_a {
					mux {
						groups = "uart_tx_a",
						       "uart_rx_a";
						function = "uart_a";
					};
				};

				uart_b_pins: uart_b {
					mux {
						groups = "uart_tx_b",
						       "uart_rx_b";
						function = "uart_b";
					};
				};

				uart_c_pins: uart_c {
					mux {
						groups = "uart_tx_c",
						       "uart_rx_c";
						function = "uart_c";
					};
				};

				eth_pins: eth_c {
					mux {
						groups = "eth_mdio",
						       "eth_mdc",
						       "eth_clk_rx_clk",
						       "eth_rx_dv",
						       "eth_rxd0",
						       "eth_rxd1",
						       "eth_rxd2",
						       "eth_rxd3",
						       "eth_rgmii_tx_clk",
						       "eth_tx_en",
						       "eth_txd0",
						       "eth_txd1",
						       "eth_txd2",
						       "eth_txd3";
						function = "eth";
					};
				};

				pwm_a_x_pins: pwm_a_x {
					mux {
						groups = "pwm_a_x";
						function = "pwm_a_x";
					};
				};

				pwm_a_y_pins: pwm_a_y {
					mux {
						groups = "pwm_a_y";
						function = "pwm_a_y";
					};
				};

				pwm_b_pins: pwm_b {
					mux {
						groups = "pwm_b";
						function = "pwm_b";
					};
				};

				pwm_d_pins: pwm_d {
					mux {
						groups = "pwm_d";
						function = "pwm_d";
					};
				};

				pwm_e_pins: pwm_e {
					mux {
						groups = "pwm_e";
						function = "pwm_e";
					};
				};

				pwm_f_x_pins: pwm_f_x {
					mux {
						groups = "pwm_f_x";
						function = "pwm_f_x";
					};
				};

				pwm_f_y_pins: pwm_f_y {
					mux {
						groups = "pwm_f_y";
						function = "pwm_f_y";
					};
				};
			};
		};

		hiubus: hiubus@c883c000 {
			compatible = "simple-bus";
			reg = <0x0 0xc883c000 0x0 0x2000>;
			#address-cells = <2>;
			#size-cells = <2>;
			ranges = <0x0 0x0 0x0 0xc883c000 0x0 0x2000>;

			clkc: clock-controller@0 {
				compatible = "amlogic,gxbb-clkc";
				#clock-cells = <1>;
				reg = <0x0 0x0 0x0 0x3db>;
			};

			mailbox: mailbox@404 {
				compatible = "amlogic,meson-gxbb-mhu";
				reg = <0 0x404 0 0x4c>;
				interrupts = <0 208 IRQ_TYPE_EDGE_RISING>,
					     <0 209 IRQ_TYPE_EDGE_RISING>,
					     <0 210 IRQ_TYPE_EDGE_RISING>;
				#mbox-cells = <1>;
			};
		};

		apb: apb@d0000000 {
			compatible = "simple-bus";
			reg = <0x0 0xd0000000 0x0 0x200000>;
			#address-cells = <2>;
			#size-cells = <2>;
			ranges = <0x0 0x0 0x0 0xd0000000 0x0 0x200000>;
		};

		ethmac: ethernet@c9410000 {
			compatible = "amlogic,meson6-dwmac", "snps,dwmac";
			reg = <0x0 0xc9410000 0x0 0x10000
			       0x0 0xc8834540 0x0 0x4>;
			interrupts = <0 8 1>;
			interrupt-names = "macirq";
			clocks = <&clkc CLKID_ETH>;
			clock-names = "stmmaceth";
			phy-mode = "rgmii";
			status = "disabled";
		};
	};
};
Commit	Line	Data
4f24eda8 AF	1	/*
	2	* Copyright (c) 2016 Andreas Färber
	3	*
	4	* This file is dual-licensed: you can use it either under the terms
	5	* of the GPL or the X11 license, at your option. Note that this dual
	6	* licensing only applies to this file, and not this project as a
	7	* whole.
	8	*
	9	* a) This library is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License as
	11	* published by the Free Software Foundation; either version 2 of the
	12	* License, or (at your option) any later version.
	13	*
	14	* This library is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* Or, alternatively,
	20	*
	21	* b) Permission is hereby granted, free of charge, to any person
	22	* obtaining a copy of this software and associated documentation
	23	* files (the "Software"), to deal in the Software without
	24	* restriction, including without limitation the rights to use,
	25	* copy, modify, merge, publish, distribute, sublicense, and/or
	26	* sell copies of the Software, and to permit persons to whom the
	27	* Software is furnished to do so, subject to the following
	28	* conditions:
	29	*
	30	* The above copyright notice and this permission notice shall be
	31	* included in all copies or substantial portions of the Software.
	32	*
	33	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	34	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
	35	* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	36	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
	37	* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
	38	* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	39	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	40	* OTHER DEALINGS IN THE SOFTWARE.
	41	*/
	42
	43	#include <dt-bindings/gpio/gpio.h>
	44	#include <dt-bindings/interrupt-controller/irq.h>
	45	#include <dt-bindings/interrupt-controller/arm-gic.h>
f40d437f	46	#include <dt-bindings/gpio/meson-gxbb-gpio.h>
6d1a5c93	47	#include <dt-bindings/reset/amlogic,meson-gxbb-reset.h>
c3929b72	48	#include <dt-bindings/clock/gxbb-clkc.h>
8d298f5b NA	49	#include <dt-bindings/clock/gxbb-aoclkc.h>
8d298f5b NA	50	#include <dt-bindings/reset/gxbb-aoclkc.h>
4f24eda8 AF	51
	52	/ {
	53	compatible = "amlogic,meson-gxbb";
	54	interrupt-parent = <&gic>;
	55	#address-cells = <2>;
	56	#size-cells = <2>;
	57
4f24eda8 AF	58	cpus {
	59	#address-cells = <0x2>;
	60	#size-cells = <0x0>;
	61
	62	cpu0: cpu@0 {
	63	device_type = "cpu";
	64	compatible = "arm,cortex-a53", "arm,armv8";
	65	reg = <0x0 0x0>;
	66	enable-method = "psci";
	67	};
	68
	69	cpu1: cpu@1 {
	70	device_type = "cpu";
	71	compatible = "arm,cortex-a53", "arm,armv8";
	72	reg = <0x0 0x1>;
	73	enable-method = "psci";
	74	};
	75
	76	cpu2: cpu@2 {
	77	device_type = "cpu";
	78	compatible = "arm,cortex-a53", "arm,armv8";
	79	reg = <0x0 0x2>;
	80	enable-method = "psci";
	81	};
	82
	83	cpu3: cpu@3 {
	84	device_type = "cpu";
	85	compatible = "arm,cortex-a53", "arm,armv8";
	86	reg = <0x0 0x3>;
	87	enable-method = "psci";
	88	};
	89	};
	90
	91	arm-pmu {
	92	compatible = "arm,cortex-a53-pmu";
	93	interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
	94	<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
	95	<GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
	96	<GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
	97	interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
	98	};
	99
	100	psci {
	101	compatible = "arm,psci-0.2";
	102	method = "smc";
	103	};
	104
f1a095b9 CC	105	firmware {
	106	sm: secure-monitor {
	107	compatible = "amlogic,meson-gxbb-sm";
	108	};
	109	};
	110
bfe59f92 CC	111	efuse: efuse {
	112	compatible = "amlogic,meson-gxbb-efuse";
	113	#address-cells = <1>;
	114	#size-cells = <1>;
	115
	116	sn: sn@14 {
	117	reg = <0x14 0x10>;
	118	};
	119
	120	eth_mac: eth_mac@34 {
	121	reg = <0x34 0x10>;
	122	};
	123
	124	bid: bid@46 {
	125	reg = <0x46 0x30>;
	126	};
	127	};
	128
4f24eda8 AF	129	timer {
	130	compatible = "arm,armv8-timer";
	131	interrupts = <GIC_PPI 13
	132	(GIC_CPU_MASK_RAW(0xff) \| IRQ_TYPE_EDGE_RISING)>,
	133	<GIC_PPI 14
	134	(GIC_CPU_MASK_RAW(0xff) \| IRQ_TYPE_EDGE_RISING)>,
	135	<GIC_PPI 11
	136	(GIC_CPU_MASK_RAW(0xff) \| IRQ_TYPE_EDGE_RISING)>,
	137	<GIC_PPI 10
	138	(GIC_CPU_MASK_RAW(0xff) \| IRQ_TYPE_EDGE_RISING)>;
	139	};
	140
	141	xtal: xtal-clk {
	142	compatible = "fixed-clock";
	143	clock-frequency = <24000000>;
	144	clock-output-names = "xtal";
	145	#clock-cells = <0>;
	146	};
	147
	148	soc {
	149	compatible = "simple-bus";
	150	#address-cells = <2>;
	151	#size-cells = <2>;
	152	ranges;
	153
	154	cbus: cbus@c1100000 {
	155	compatible = "simple-bus";
	156	reg = <0x0 0xc1100000 0x0 0x100000>;
	157	#address-cells = <2>;
	158	#size-cells = <2>;
	159	ranges = <0x0 0x0 0x0 0xc1100000 0x0 0x100000>;
	160
6d1a5c93 NA	161	reset: reset-controller@4404 {
	162	compatible = "amlogic,meson-gxbb-reset";
	163	reg = <0x0 0x04404 0x0 0x20>;
	164	#reset-cells = <1>;
	165	};
	166
4f24eda8 AF	167	uart_A: serial@84c0 {
4f24eda8 AF	168	compatible = "amlogic,meson-uart";
8e6320dd	169	reg = <0x0 0x84c0 0x0 0x14>;
4f24eda8 AF	170	interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
	171	clocks = <&xtal>;
	172	status = "disabled";
	173	};
8e6320dd KH	174
	175	uart_B: serial@84dc {
	176	compatible = "amlogic,meson-uart";
	177	reg = <0x0 0x84dc 0x0 0x14>;
	178	interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
	179	clocks = <&xtal>;
	180	status = "disabled";
	181	};
	182
	183	uart_C: serial@8700 {
	184	compatible = "amlogic,meson-uart";
	185	reg = <0x0 0x8700 0x0 0x14>;
	186	interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>;
	187	clocks = <&xtal>;
	188	status = "disabled";
	189	};
f759b640 NA	190
	191	watchdog@98d0 {
	192	compatible = "amlogic,meson-gxbb-wdt";
	193	reg = <0x0 0x098d0 0x0 0x10>;
	194	clocks = <&xtal>;
	195	};
4f24eda8 AF	196	};
	197
	198	gic: interrupt-controller@c4301000 {
	199	compatible = "arm,gic-400";
	200	reg = <0x0 0xc4301000 0 0x1000>,
	201	<0x0 0xc4302000 0 0x2000>,
	202	<0x0 0xc4304000 0 0x2000>,
	203	<0x0 0xc4306000 0 0x2000>;
	204	interrupt-controller;
	205	interrupts = <GIC_PPI 9
	206	(GIC_CPU_MASK_SIMPLE(8) \| IRQ_TYPE_LEVEL_HIGH)>;
	207	#interrupt-cells = <3>;
	208	#address-cells = <0>;
	209	};
	210
	211	aobus: aobus@c8100000 {
	212	compatible = "simple-bus";
	213	reg = <0x0 0xc8100000 0x0 0x100000>;
	214	#address-cells = <2>;
	215	#size-cells = <2>;
	216	ranges = <0x0 0x0 0x0 0xc8100000 0x0 0x100000>;
	217
f40d437f CC	218	pinctrl_aobus: pinctrl@14 {
	219	compatible = "amlogic,meson-gxbb-aobus-pinctrl";
	220	#address-cells = <2>;
	221	#size-cells = <2>;
	222	ranges;
	223
	224	gpio_ao: bank@14 {
	225	reg = <0x0 0x00014 0x0 0x8>,
	226	<0x0 0x0002c 0x0 0x4>,
	227	<0x0 0x00024 0x0 0x8>;
	228	reg-names = "mux", "pull", "gpio";
	229	gpio-controller;
	230	#gpio-cells = <2>;
	231	};
	232
	233	uart_ao_a_pins: uart_ao_a {
	234	mux {
	235	groups = "uart_tx_ao_a", "uart_rx_ao_a";
	236	function = "uart_ao";
	237	};
	238	};
9bfd6329 KH	239
	240	remote_input_ao_pins: remote_input_ao {
	241	mux {
	242	groups = "remote_input_ao";
	243	function = "remote_input_ao";
	244	};
	245	};
f03faf31 KH	246
	247	pwm_ao_a_3_pins: pwm_ao_a_3 {
	248	mux {
	249	groups = "pwm_ao_a_3";
	250	function = "pwm_ao_a_3";
	251	};
	252	};
	253
	254	pwm_ao_a_6_pins: pwm_ao_a_6 {
	255	mux {
	256	groups = "pwm_ao_a_6";
	257	function = "pwm_ao_a_6";
	258	};
	259	};
	260
	261	pwm_ao_a_12_pins: pwm_ao_a_12 {
	262	mux {
	263	groups = "pwm_ao_a_12";
	264	function = "pwm_ao_a_12";
	265	};
	266	};
	267
	268	pwm_ao_b_pins: pwm_ao_b {
	269	mux {
	270	groups = "pwm_ao_b";
	271	function = "pwm_ao_b";
	272	};
	273	};
f40d437f CC	274	};
f40d437f CC	275
8d298f5b NA	276	clkc_AO: clock-controller@040 {
	277	compatible = "amlogic,gxbb-aoclkc";
	278	reg = <0x0 0x00040 0x0 0x4>;
	279	#clock-cells = <1>;
	280	#reset-cells = <1>;
	281	};
	282
4f24eda8 AF	283	uart_AO: serial@4c0 {
	284	compatible = "amlogic,meson-uart";
	285	reg = <0x0 0x004c0 0x0 0x14>;
	286	interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
	287	clocks = <&xtal>;
	288	status = "disabled";
	289	};
c58d7785 NA	290
	291	ir: ir@580 {
	292	compatible = "amlogic,meson-gxbb-ir";
	293	reg = <0x0 0x00580 0x0 0x40>;
	294	interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>;
	295	status = "disabled";
	296	};
4f24eda8 AF	297	};
4f24eda8 AF	298
fab6b48c CC	299	periphs: periphs@c8834000 {
	300	compatible = "simple-bus";
	301	reg = <0x0 0xc8834000 0x0 0x2000>;
	302	#address-cells = <2>;
	303	#size-cells = <2>;
	304	ranges = <0x0 0x0 0x0 0xc8834000 0x0 0x2000>;
f40d437f	305
4b7bed38 NA	306	rng {
	307	compatible = "amlogic,meson-rng";
	308	reg = <0x0 0x0 0x0 0x4>;
	309	};
	310
f40d437f CC	311	pinctrl_periphs: pinctrl@4b0 {
	312	compatible = "amlogic,meson-gxbb-periphs-pinctrl";
	313	#address-cells = <2>;
	314	#size-cells = <2>;
	315	ranges;
	316
	317	gpio: bank@4b0 {
	318	reg = <0x0 0x004b0 0x0 0x28>,
	319	<0x0 0x004e8 0x0 0x14>,
	320	<0x0 0x00120 0x0 0x14>,
	321	<0x0 0x00430 0x0 0x40>;
	322	reg-names = "mux", "pull", "pull-enable", "gpio";
	323	gpio-controller;
	324	#gpio-cells = <2>;
	325	};
a8025ed6 KH	326
	327	emmc_pins: emmc {
	328	mux {
	329	groups = "emmc_nand_d07",
	330	"emmc_cmd",
	331	"emmc_clk";
	332	function = "emmc";
	333	};
	334	};
	335
	336	sdcard_pins: sdcard {
	337	mux {
	338	groups = "sdcard_d0",
	339	"sdcard_d1",
	340	"sdcard_d2",
	341	"sdcard_d3",
	342	"sdcard_cmd",
	343	"sdcard_clk";
	344	function = "sdcard";
	345	};
	346	};
8e6320dd KH	347
	348	uart_a_pins: uart_a {
	349	mux {
	350	groups = "uart_tx_a",
	351	"uart_rx_a";
	352	function = "uart_a";
	353	};
	354	};
	355
	356	uart_b_pins: uart_b {
	357	mux {
	358	groups = "uart_tx_b",
	359	"uart_rx_b";
	360	function = "uart_b";
	361	};
	362	};
	363
	364	uart_c_pins: uart_c {
	365	mux {
	366	groups = "uart_tx_c",
	367	"uart_rx_c";
	368	function = "uart_c";
	369	};
	370	};
8c5509f0 KH	371
	372	eth_pins: eth_c {
	373	mux {
	374	groups = "eth_mdio",
	375	"eth_mdc",
	376	"eth_clk_rx_clk",
	377	"eth_rx_dv",
	378	"eth_rxd0",
	379	"eth_rxd1",
	380	"eth_rxd2",
	381	"eth_rxd3",
	382	"eth_rgmii_tx_clk",
	383	"eth_tx_en",
	384	"eth_txd0",
	385	"eth_txd1",
	386	"eth_txd2",
	387	"eth_txd3";
	388	function = "eth";
	389	};
	390	};
f03faf31 KH	391
	392	pwm_a_x_pins: pwm_a_x {
	393	mux {
	394	groups = "pwm_a_x";
	395	function = "pwm_a_x";
	396	};
	397	};
	398
	399	pwm_a_y_pins: pwm_a_y {
	400	mux {
	401	groups = "pwm_a_y";
	402	function = "pwm_a_y";
	403	};
	404	};
	405
	406	pwm_b_pins: pwm_b {
	407	mux {
	408	groups = "pwm_b";
	409	function = "pwm_b";
	410	};
	411	};
	412
	413	pwm_d_pins: pwm_d {
	414	mux {
	415	groups = "pwm_d";
	416	function = "pwm_d";
	417	};
	418	};
	419
	420	pwm_e_pins: pwm_e {
	421	mux {
	422	groups = "pwm_e";
	423	function = "pwm_e";
	424	};
	425	};
	426
	427	pwm_f_x_pins: pwm_f_x {
	428	mux {
	429	groups = "pwm_f_x";
	430	function = "pwm_f_x";
	431	};
	432	};
	433
	434	pwm_f_y_pins: pwm_f_y {
	435	mux {
	436	groups = "pwm_f_y";
	437	function = "pwm_f_y";
	438	};
	439	};
f40d437f	440	};
fab6b48c CC	441	};
	442
	443	hiubus: hiubus@c883c000 {
	444	compatible = "simple-bus";
	445	reg = <0x0 0xc883c000 0x0 0x2000>;
	446	#address-cells = <2>;
	447	#size-cells = <2>;
	448	ranges = <0x0 0x0 0x0 0xc883c000 0x0 0x2000>;
ba6a6c7f MT	449
	450	clkc: clock-controller@0 {
	451	compatible = "amlogic,gxbb-clkc";
	452	#clock-cells = <1>;
	453	reg = <0x0 0x0 0x0 0x3db>;
	454	};
7b5682c6 NA	455
	456	mailbox: mailbox@404 {
	457	compatible = "amlogic,meson-gxbb-mhu";
	458	reg = <0 0x404 0 0x4c>;
	459	interrupts = <0 208 IRQ_TYPE_EDGE_RISING>,
	460	<0 209 IRQ_TYPE_EDGE_RISING>,
	461	<0 210 IRQ_TYPE_EDGE_RISING>;
	462	#mbox-cells = <1>;
	463	};
fab6b48c CC	464	};
fab6b48c CC	465
4f24eda8 AF	466	apb: apb@d0000000 {
	467	compatible = "simple-bus";
	468	reg = <0x0 0xd0000000 0x0 0x200000>;
	469	#address-cells = <2>;
	470	#size-cells = <2>;
	471	ranges = <0x0 0x0 0x0 0xd0000000 0x0 0x200000>;
	472	};
8c5509f0 KH	473
	474	ethmac: ethernet@c9410000 {
	475	compatible = "amlogic,meson6-dwmac", "snps,dwmac";
	476	reg = <0x0 0xc9410000 0x0 0x10000
	477	0x0 0xc8834540 0x0 0x4>;
	478	interrupts = <0 8 1>;
	479	interrupt-names = "macirq";
c3929b72	480	clocks = <&clkc CLKID_ETH>;
8c5509f0 KH	481	clock-names = "stmmaceth";
	482	phy-mode = "rgmii";
	483	status = "disabled";
	484	};
4f24eda8 AF	485	};
4f24eda8 AF	486	};