[linux-2.6-block.git] / arch / arm64 / boot / dts / altera / socfpga_stratix10.dtsi

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright Altera Corporation (C) 2015. All rights reserved.
 */

/dts-v1/;
#include <dt-bindings/reset/altr,rst-mgr-s10.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/clock/stratix10-clock.h>

/ {
	compatible = "altr,socfpga-stratix10";
	#address-cells = <2>;
	#size-cells = <2>;

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		service_reserved: svcbuffer@0 {
			compatible = "shared-dma-pool";
			reg = <0x0 0x0 0x0 0x1000000>;
			alignment = <0x1000>;
			no-map;
		};
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			compatible = "arm,cortex-a53";
			device_type = "cpu";
			enable-method = "psci";
			next-level-cache = <&l2_shared>;
			reg = <0x0>;
		};

		cpu1: cpu@1 {
			compatible = "arm,cortex-a53";
			device_type = "cpu";
			enable-method = "psci";
			next-level-cache = <&l2_shared>;
			reg = <0x1>;
		};

		cpu2: cpu@2 {
			compatible = "arm,cortex-a53";
			device_type = "cpu";
			enable-method = "psci";
			next-level-cache = <&l2_shared>;
			reg = <0x2>;
		};

		cpu3: cpu@3 {
			compatible = "arm,cortex-a53";
			device_type = "cpu";
			enable-method = "psci";
			next-level-cache = <&l2_shared>;
			reg = <0x3>;
		};

		l2_shared: cache {
			compatible = "cache";
			cache-level = <2>;
			cache-unified;
		};
	};

	firmware {
		svc {
			compatible = "intel,stratix10-svc";
			method = "smc";
			memory-region = <&service_reserved>;

			fpga_mgr: fpga-mgr {
				compatible = "intel,stratix10-soc-fpga-mgr";
			};
		};
	};

	fpga-region {
		compatible = "fpga-region";
		#address-cells = <0x2>;
		#size-cells = <0x2>;
		fpga-mgr = <&fpga_mgr>;
	};

	pmu {
		compatible = "arm,cortex-a53-pmu";
		interrupts = <0 170 4>,
			     <0 171 4>,
			     <0 172 4>,
			     <0 173 4>;
		interrupt-affinity = <&cpu0>,
				     <&cpu1>,
				     <&cpu2>,
				     <&cpu3>;
		interrupt-parent = <&intc>;
	};

	psci {
		compatible = "arm,psci-0.2";
		method = "smc";
	};

	/* Local timer */
	timer {
		compatible = "arm,armv8-timer";
		interrupts = <1 13 0xf08>,
			     <1 14 0xf08>,
			     <1 11 0xf08>,
			     <1 10 0xf08>;
		interrupt-parent = <&intc>;
	};

	intc: interrupt-controller@fffc1000 {
		compatible = "arm,gic-400", "arm,cortex-a15-gic";
		#interrupt-cells = <3>;
		interrupt-controller;
		reg = <0x0 0xfffc1000 0x0 0x1000>,
		      <0x0 0xfffc2000 0x0 0x2000>,
		      <0x0 0xfffc4000 0x0 0x2000>,
		      <0x0 0xfffc6000 0x0 0x2000>;
	};

	clocks {
		cb_intosc_hs_div2_clk: cb-intosc-hs-div2-clk {
			#clock-cells = <0>;
			compatible = "fixed-clock";
		};

		cb_intosc_ls_clk: cb-intosc-ls-clk {
			#clock-cells = <0>;
			compatible = "fixed-clock";
		};

		f2s_free_clk: f2s-free-clk {
			#clock-cells = <0>;
			compatible = "fixed-clock";
		};

		osc1: osc1 {
			#clock-cells = <0>;
			compatible = "fixed-clock";
		};

		qspi_clk: qspi-clk {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <200000000>;
		};
	};

	soc@0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "simple-bus";
		device_type = "soc";
		interrupt-parent = <&intc>;
		ranges = <0 0 0 0xffffffff>;

		clkmgr: clock-controller@ffd10000 {
			compatible = "intel,stratix10-clkmgr";
			reg = <0xffd10000 0x1000>;
			#clock-cells = <1>;
		};

		gmac0: ethernet@ff800000 {
			compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac";
			reg = <0xff800000 0x2000>;
			interrupts = <0 90 4>;
			interrupt-names = "macirq";
			mac-address = [00 00 00 00 00 00];
			resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>;
			reset-names = "stmmaceth", "ahb";
			clocks = <&clkmgr STRATIX10_EMAC0_CLK>, <&clkmgr STRATIX10_EMAC_PTP_CLK>;
			clock-names = "stmmaceth", "ptp_ref";
			tx-fifo-depth = <16384>;
			rx-fifo-depth = <16384>;
			snps,multicast-filter-bins = <256>;
			iommus = <&smmu 1>;
			altr,sysmgr-syscon = <&sysmgr 0x44 0>;
			status = "disabled";
		};

		gmac1: ethernet@ff802000 {
			compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac";
			reg = <0xff802000 0x2000>;
			interrupts = <0 91 4>;
			interrupt-names = "macirq";
			mac-address = [00 00 00 00 00 00];
			resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>;
			reset-names = "stmmaceth", "ahb";
			clocks = <&clkmgr STRATIX10_EMAC1_CLK>, <&clkmgr STRATIX10_EMAC_PTP_CLK>;
			clock-names = "stmmaceth", "ptp_ref";
			tx-fifo-depth = <16384>;
			rx-fifo-depth = <16384>;
			snps,multicast-filter-bins = <256>;
			iommus = <&smmu 2>;
			altr,sysmgr-syscon = <&sysmgr 0x48 8>;
			status = "disabled";
		};

		gmac2: ethernet@ff804000 {
			compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac";
			reg = <0xff804000 0x2000>;
			interrupts = <0 92 4>;
			interrupt-names = "macirq";
			mac-address = [00 00 00 00 00 00];
			resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>;
			reset-names = "stmmaceth", "ahb";
			clocks = <&clkmgr STRATIX10_EMAC2_CLK>, <&clkmgr STRATIX10_EMAC_PTP_CLK>;
			clock-names = "stmmaceth", "ptp_ref";
			tx-fifo-depth = <16384>;
			rx-fifo-depth = <16384>;
			snps,multicast-filter-bins = <256>;
			iommus = <&smmu 3>;
			altr,sysmgr-syscon = <&sysmgr 0x4c 16>;
			status = "disabled";
		};

		gpio0: gpio@ffc03200 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "snps,dw-apb-gpio";
			reg = <0xffc03200 0x100>;
			resets = <&rst GPIO0_RESET>;
			status = "disabled";

			porta: gpio-controller@0 {
				compatible = "snps,dw-apb-gpio-port";
				gpio-controller;
				#gpio-cells = <2>;
				ngpios = <24>;
				reg = <0>;
				interrupt-controller;
				#interrupt-cells = <2>;
				interrupts = <0 110 4>;
			};
		};

		gpio1: gpio@ffc03300 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "snps,dw-apb-gpio";
			reg = <0xffc03300 0x100>;
			resets = <&rst GPIO1_RESET>;
			status = "disabled";

			portb: gpio-controller@0 {
				compatible = "snps,dw-apb-gpio-port";
				gpio-controller;
				#gpio-cells = <2>;
				ngpios = <24>;
				reg = <0>;
				interrupt-controller;
				#interrupt-cells = <2>;
				interrupts = <0 111 4>;
			};
		};

		i2c0: i2c@ffc02800 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "snps,designware-i2c";
			reg = <0xffc02800 0x100>;
			interrupts = <0 103 4>;
			resets = <&rst I2C0_RESET>;
			clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
			status = "disabled";
		};

		i2c1: i2c@ffc02900 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "snps,designware-i2c";
			reg = <0xffc02900 0x100>;
			interrupts = <0 104 4>;
			resets = <&rst I2C1_RESET>;
			clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
			status = "disabled";
		};

		i2c2: i2c@ffc02a00 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "snps,designware-i2c";
			reg = <0xffc02a00 0x100>;
			interrupts = <0 105 4>;
			resets = <&rst I2C2_RESET>;
			clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
			status = "disabled";
		};

		i2c3: i2c@ffc02b00 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "snps,designware-i2c";
			reg = <0xffc02b00 0x100>;
			interrupts = <0 106 4>;
			resets = <&rst I2C3_RESET>;
			clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
			status = "disabled";
		};

		i2c4: i2c@ffc02c00 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "snps,designware-i2c";
			reg = <0xffc02c00 0x100>;
			interrupts = <0 107 4>;
			resets = <&rst I2C4_RESET>;
			clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
			status = "disabled";
		};

		mmc: mmc@ff808000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "altr,socfpga-dw-mshc";
			reg = <0xff808000 0x1000>;
			interrupts = <0 96 4>;
			fifo-depth = <0x400>;
			resets = <&rst SDMMC_RESET>;
			reset-names = "reset";
			clocks = <&clkmgr STRATIX10_L4_MP_CLK>,
				 <&clkmgr STRATIX10_SDMMC_CLK>;
			clock-names = "biu", "ciu";
			iommus = <&smmu 5>;
			altr,sysmgr-syscon = <&sysmgr 0x28 4>;
			status = "disabled";
		};

		nand: nand-controller@ffb90000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "altr,socfpga-denali-nand";
			reg = <0xffb90000 0x10000>,
			      <0xffb80000 0x1000>;
			reg-names = "nand_data", "denali_reg";
			interrupts = <0 97 4>;
			clocks = <&clkmgr STRATIX10_NAND_CLK>,
				 <&clkmgr STRATIX10_NAND_X_CLK>,
				 <&clkmgr STRATIX10_NAND_ECC_CLK>;
			clock-names = "nand", "nand_x", "ecc";
			resets = <&rst NAND_RESET>, <&rst NAND_OCP_RESET>;
			status = "disabled";
		};

		ocram: sram@ffe00000 {
			compatible = "mmio-sram";
			reg = <0xffe00000 0x100000>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 0xffe00000 0x100000>;
		};

		pdma: dma-controller@ffda0000 {
			compatible = "arm,pl330", "arm,primecell";
			reg = <0xffda0000 0x1000>;
			interrupts = <0 81 4>,
				     <0 82 4>,
				     <0 83 4>,
				     <0 84 4>,
				     <0 85 4>,
				     <0 86 4>,
				     <0 87 4>,
				     <0 88 4>,
				     <0 89 4>;
			#dma-cells = <1>;
			clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>;
			clock-names = "apb_pclk";
			resets = <&rst DMA_RESET>, <&rst DMA_OCP_RESET>;
			reset-names = "dma", "dma-ocp";
		};

		pinctrl0: pinctrl@ffd13000 {
			compatible = "pinctrl-single";
			reg = <0xffd13000 0xA0>;
			#pinctrl-cells = <1>;
			pinctrl-single,register-width = <32>;
			pinctrl-single,function-mask = <0x0000000f>;
		};

		pinctrl1: pinctrl@ffd13100 {
			compatible = "pinctrl-single";
			reg = <0xffd13100 0x20>;
			#pinctrl-cells = <1>;
			pinctrl-single,register-width = <32>;
			pinctrl-single,function-mask = <0x0000000f>;
		};

		rst: rstmgr@ffd11000 {
			#reset-cells = <1>;
			compatible = "altr,stratix10-rst-mgr";
			reg = <0xffd11000 0x1000>;
		};

		smmu: iommu@fa000000 {
			compatible = "arm,mmu-500", "arm,smmu-v2";
			reg = <0xfa000000 0x40000>;
			#global-interrupts = <2>;
			#iommu-cells = <1>;
			clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>;
			clock-names = "iommu";
			interrupt-parent = <&intc>;
			interrupts = <0 128 4>,	/* Global Secure Fault */
				<0 129 4>, /* Global Non-secure Fault */
				/* Non-secure Context Interrupts (32) */
				<0 138 4>, <0 139 4>, <0 140 4>, <0 141 4>,
				<0 142 4>, <0 143 4>, <0 144 4>, <0 145 4>,
				<0 146 4>, <0 147 4>, <0 148 4>, <0 149 4>,
				<0 150 4>, <0 151 4>, <0 152 4>, <0 153 4>,
				<0 154 4>, <0 155 4>, <0 156 4>, <0 157 4>,
				<0 158 4>, <0 159 4>, <0 160 4>, <0 161 4>,
				<0 162 4>, <0 163 4>, <0 164 4>, <0 165 4>,
				<0 166 4>, <0 167 4>, <0 168 4>, <0 169 4>;
			stream-match-mask = <0x7ff0>;
			status = "disabled";
		};

		spi0: spi@ffda4000 {
			compatible = "snps,dw-apb-ssi";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0xffda4000 0x1000>;
			interrupts = <0 99 4>;
			resets = <&rst SPIM0_RESET>;
			reset-names = "spi";
			reg-io-width = <4>;
			num-cs = <4>;
			clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>;
			status = "disabled";
		};

		spi1: spi@ffda5000 {
			compatible = "snps,dw-apb-ssi";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0xffda5000 0x1000>;
			interrupts = <0 100 4>;
			resets = <&rst SPIM1_RESET>;
			reset-names = "spi";
			reg-io-width = <4>;
			num-cs = <4>;
			clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>;
			status = "disabled";
		};

		sysmgr: sysmgr@ffd12000 {
			compatible = "altr,sys-mgr-s10","altr,sys-mgr";
			reg = <0xffd12000 0x228>;
		};

		timer0: timer0@ffc03000 {
			compatible = "snps,dw-apb-timer";
			interrupts = <0 113 4>;
			reg = <0xffc03000 0x100>;
			clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
			clock-names = "timer";
		};

		timer1: timer1@ffc03100 {
			compatible = "snps,dw-apb-timer";
			interrupts = <0 114 4>;
			reg = <0xffc03100 0x100>;
			clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
			clock-names = "timer";
		};

		timer2: timer2@ffd00000 {
			compatible = "snps,dw-apb-timer";
			interrupts = <0 115 4>;
			reg = <0xffd00000 0x100>;
			clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
			clock-names = "timer";
		};

		timer3: timer3@ffd00100 {
			compatible = "snps,dw-apb-timer";
			interrupts = <0 116 4>;
			reg = <0xffd00100 0x100>;
			clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
			clock-names = "timer";
		};

		uart0: serial@ffc02000 {
			compatible = "snps,dw-apb-uart";
			reg = <0xffc02000 0x100>;
			interrupts = <0 108 4>;
			reg-shift = <2>;
			reg-io-width = <4>;
			resets = <&rst UART0_RESET>;
			clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
			status = "disabled";
		};

		uart1: serial@ffc02100 {
			compatible = "snps,dw-apb-uart";
			reg = <0xffc02100 0x100>;
			interrupts = <0 109 4>;
			reg-shift = <2>;
			reg-io-width = <4>;
			resets = <&rst UART1_RESET>;
			clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
			status = "disabled";
		};

		usb0: usb@ffb00000 {
			compatible = "snps,dwc2";
			reg = <0xffb00000 0x40000>;
			interrupts = <0 93 4>;
			phys = <&usbphy0>;
			phy-names = "usb2-phy";
			resets = <&rst USB0_RESET>, <&rst USB0_OCP_RESET>;
			reset-names = "dwc2", "dwc2-ecc";
			clocks = <&clkmgr STRATIX10_USB_CLK>;
			clock-names = "otg";
			iommus = <&smmu 6>;
			status = "disabled";
		};

		usb1: usb@ffb40000 {
			compatible = "snps,dwc2";
			reg = <0xffb40000 0x40000>;
			interrupts = <0 94 4>;
			phys = <&usbphy0>;
			phy-names = "usb2-phy";
			resets = <&rst USB1_RESET>, <&rst USB1_OCP_RESET>;
			reset-names = "dwc2", "dwc2-ecc";
			clocks = <&clkmgr STRATIX10_USB_CLK>;
			clock-names = "otg";
			iommus = <&smmu 7>;
			status = "disabled";
		};

		watchdog0: watchdog@ffd00200 {
			compatible = "snps,dw-wdt";
			reg = <0xffd00200 0x100>;
			interrupts = <0 117 4>;
			resets = <&rst WATCHDOG0_RESET>;
			clocks = <&clkmgr STRATIX10_L4_SYS_FREE_CLK>;
			status = "disabled";
		};

		watchdog1: watchdog@ffd00300 {
			compatible = "snps,dw-wdt";
			reg = <0xffd00300 0x100>;
			interrupts = <0 118 4>;
			resets = <&rst WATCHDOG1_RESET>;
			clocks = <&clkmgr STRATIX10_L4_SYS_FREE_CLK>;
			status = "disabled";
		};

		watchdog2: watchdog@ffd00400 {
			compatible = "snps,dw-wdt";
			reg = <0xffd00400 0x100>;
			interrupts = <0 125 4>;
			resets = <&rst WATCHDOG2_RESET>;
			clocks = <&clkmgr STRATIX10_L4_SYS_FREE_CLK>;
			status = "disabled";
		};

		watchdog3: watchdog@ffd00500 {
			compatible = "snps,dw-wdt";
			reg = <0xffd00500 0x100>;
			interrupts = <0 126 4>;
			resets = <&rst WATCHDOG3_RESET>;
			clocks = <&clkmgr STRATIX10_L4_SYS_FREE_CLK>;
			status = "disabled";
		};

		sdr: sdr@f8011100 {
			compatible = "altr,sdr-ctl", "syscon";
			reg = <0xf8011100 0xc0>;
		};

		eccmgr {
			compatible = "altr,socfpga-s10-ecc-manager",
				     "altr,socfpga-a10-ecc-manager";
			altr,sysmgr-syscon = <&sysmgr>;
			#address-cells = <1>;
			#size-cells = <1>;
			interrupts = <0 15 4>;
			interrupt-controller;
			#interrupt-cells = <2>;
			ranges;

			sdramedac {
				compatible = "altr,sdram-edac-s10";
				altr,sdr-syscon = <&sdr>;
				interrupts = <16 4>;
			};

			ocram-ecc@ff8cc000 {
				compatible = "altr,socfpga-s10-ocram-ecc",
					     "altr,socfpga-a10-ocram-ecc";
				reg = <0xff8cc000 0x100>;
				altr,ecc-parent = <&ocram>;
				interrupts = <1 4>;
			};

			usb0-ecc@ff8c4000 {
				compatible = "altr,socfpga-s10-usb-ecc",
					     "altr,socfpga-usb-ecc";
				reg = <0xff8c4000 0x100>;
				altr,ecc-parent = <&usb0>;
				interrupts = <2 4>;
			};

			emac0-rx-ecc@ff8c0000 {
				compatible = "altr,socfpga-s10-eth-mac-ecc",
					     "altr,socfpga-eth-mac-ecc";
				reg = <0xff8c0000 0x100>;
				altr,ecc-parent = <&gmac0>;
				interrupts = <4 4>;
			};

			emac0-tx-ecc@ff8c0400 {
				compatible = "altr,socfpga-s10-eth-mac-ecc",
					     "altr,socfpga-eth-mac-ecc";
				reg = <0xff8c0400 0x100>;
				altr,ecc-parent = <&gmac0>;
				interrupts = <5 4>;
			};

		};

		qspi: spi@ff8d2000 {
			compatible = "intel,socfpga-qspi", "cdns,qspi-nor";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0xff8d2000 0x100>,
			      <0xff900000 0x100000>;
			interrupts = <0 3 4>;
			cdns,fifo-depth = <128>;
			cdns,fifo-width = <4>;
			cdns,trigger-address = <0x00000000>;
			clocks = <&qspi_clk>;

			status = "disabled";
		};
	};

	usbphy0: usbphy0 {
		compatible = "usb-nop-xceiv";
		#phy-cells = <0>;
	};
};
Commit	Line	Data
9952f691	1	// SPDX-License-Identifier: GPL-2.0-only
78cd6a9d DN	2	/*
78cd6a9d DN	3	* Copyright Altera Corporation (C) 2015. All rights reserved.
78cd6a9d DN	4	*/
	5
	6	/dts-v1/;
e519922e	7	#include <dt-bindings/reset/altr,rst-mgr-s10.h>
5a0e622e	8	#include <dt-bindings/gpio/gpio.h>
d93101ab	9	#include <dt-bindings/clock/stratix10-clock.h>
78cd6a9d DN	10
	11	/ {
	12	compatible = "altr,socfpga-stratix10";
	13	#address-cells = <2>;
	14	#size-cells = <2>;
	15
adb9e354 RG	16	reserved-memory {
	17	#address-cells = <2>;
	18	#size-cells = <2>;
	19	ranges;
	20
	21	service_reserved: svcbuffer@0 {
	22	compatible = "shared-dma-pool";
	23	reg = <0x0 0x0 0x0 0x1000000>;
	24	alignment = <0x1000>;
	25	no-map;
	26	};
	27	};
	28
78cd6a9d DN	29	cpus {
	30	#address-cells = <1>;
	31	#size-cells = <0>;
	32
	33	cpu0: cpu@0 {
31af04cd	34	compatible = "arm,cortex-a53";
78cd6a9d DN	35	device_type = "cpu";
78cd6a9d DN	36	enable-method = "psci";
1536dc8e	37	next-level-cache = <&l2_shared>;
78cd6a9d DN	38	reg = <0x0>;
	39	};
	40
	41	cpu1: cpu@1 {
31af04cd	42	compatible = "arm,cortex-a53";
78cd6a9d DN	43	device_type = "cpu";
78cd6a9d DN	44	enable-method = "psci";
1536dc8e	45	next-level-cache = <&l2_shared>;
78cd6a9d DN	46	reg = <0x1>;
	47	};
	48
	49	cpu2: cpu@2 {
31af04cd	50	compatible = "arm,cortex-a53";
78cd6a9d DN	51	device_type = "cpu";
78cd6a9d DN	52	enable-method = "psci";
1536dc8e	53	next-level-cache = <&l2_shared>;
78cd6a9d DN	54	reg = <0x2>;
	55	};
	56
	57	cpu3: cpu@3 {
31af04cd	58	compatible = "arm,cortex-a53";
78cd6a9d DN	59	device_type = "cpu";
78cd6a9d DN	60	enable-method = "psci";
1536dc8e	61	next-level-cache = <&l2_shared>;
78cd6a9d DN	62	reg = <0x3>;
78cd6a9d DN	63	};
1536dc8e BS	64
	65	l2_shared: cache {
	66	compatible = "cache";
	67	cache-level = <2>;
	68	cache-unified;
	69	};
78cd6a9d DN	70	};
78cd6a9d DN	71
9fc0511a KK	72	firmware {
	73	svc {
	74	compatible = "intel,stratix10-svc";
	75	method = "smc";
	76	memory-region = <&service_reserved>;
	77
	78	fpga_mgr: fpga-mgr {
	79	compatible = "intel,stratix10-soc-fpga-mgr";
	80	};
	81	};
	82	};
	83
5c8f036f KK	84	fpga-region {
	85	compatible = "fpga-region";
	86	#address-cells = <0x2>;
	87	#size-cells = <0x2>;
	88	fpga-mgr = <&fpga_mgr>;
	89	};
	90
78cd6a9d	91	pmu {
8b40a469	92	compatible = "arm,cortex-a53-pmu";
210de0e9 DN	93	interrupts = <0 170 4>,
	94	<0 171 4>,
	95	<0 172 4>,
	96	<0 173 4>;
78cd6a9d DN	97	interrupt-affinity = <&cpu0>,
	98	<&cpu1>,
	99	<&cpu2>,
	100	<&cpu3>;
69c4d8ed	101	interrupt-parent = <&intc>;
78cd6a9d DN	102	};
	103
	104	psci {
	105	compatible = "arm,psci-0.2";
	106	method = "smc";
	107	};
	108
79f1db27 KK	109	/* Local timer */
	110	timer {
	111	compatible = "arm,armv8-timer";
	112	interrupts = <1 13 0xf08>,
	113	<1 14 0xf08>,
	114	<1 11 0xf08>,
	115	<1 10 0xf08>;
	116	interrupt-parent = <&intc>;
	117	};
	118
681a5c71	119	intc: interrupt-controller@fffc1000 {
78cd6a9d DN	120	compatible = "arm,gic-400", "arm,cortex-a15-gic";
	121	#interrupt-cells = <3>;
	122	interrupt-controller;
f973bfa0 DN	123	reg = <0x0 0xfffc1000 0x0 0x1000>,
	124	<0x0 0xfffc2000 0x0 0x2000>,
	125	<0x0 0xfffc4000 0x0 0x2000>,
	126	<0x0 0xfffc6000 0x0 0x2000>;
78cd6a9d DN	127	};
78cd6a9d DN	128
357513c0 NR	129	clocks {
	130	cb_intosc_hs_div2_clk: cb-intosc-hs-div2-clk {
	131	#clock-cells = <0>;
	132	compatible = "fixed-clock";
	133	};
	134
	135	cb_intosc_ls_clk: cb-intosc-ls-clk {
	136	#clock-cells = <0>;
	137	compatible = "fixed-clock";
	138	};
	139
	140	f2s_free_clk: f2s-free-clk {
	141	#clock-cells = <0>;
	142	compatible = "fixed-clock";
	143	};
	144
	145	osc1: osc1 {
	146	#clock-cells = <0>;
	147	compatible = "fixed-clock";
	148	};
	149
	150	qspi_clk: qspi-clk {
	151	#clock-cells = <0>;
	152	compatible = "fixed-clock";
	153	clock-frequency = <200000000>;
	154	};
	155	};
	156
5e53525f	157	soc@0 {
78cd6a9d DN	158	#address-cells = <1>;
	159	#size-cells = <1>;
	160	compatible = "simple-bus";
	161	device_type = "soc";
	162	interrupt-parent = <&intc>;
	163	ranges = <0 0 0 0xffffffff>;
	164
d93101ab DN	165	clkmgr: clock-controller@ffd10000 {
d93101ab DN	166	compatible = "intel,stratix10-clkmgr";
78cd6a9d	167	reg = <0xffd10000 0x1000>;
d93101ab DN	168	#clock-cells = <1>;
	169	};
	170
78cd6a9d	171	gmac0: ethernet@ff800000 {
9aa0cae1	172	compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac";
78cd6a9d DN	173	reg = <0xff800000 0x2000>;
	174	interrupts = <0 90 4>;
	175	interrupt-names = "macirq";
	176	mac-address = [00 00 00 00 00 00];
05690e8a	177	resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>;
331085a4	178	reset-names = "stmmaceth", "ahb";
6e043c65 DN	179	clocks = <&clkmgr STRATIX10_EMAC0_CLK>, <&clkmgr STRATIX10_EMAC_PTP_CLK>;
6e043c65 DN	180	clock-names = "stmmaceth", "ptp_ref";
a27460c9 TT	181	tx-fifo-depth = <16384>;
a27460c9 TT	182	rx-fifo-depth = <16384>;
fd5ba6ee	183	snps,multicast-filter-bins = <256>;
ae3f46c8	184	iommus = <&smmu 1>;
8efd6365	185	altr,sysmgr-syscon = <&sysmgr 0x44 0>;
78cd6a9d DN	186	status = "disabled";
	187	};
	188
	189	gmac1: ethernet@ff802000 {
9aa0cae1	190	compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac";
78cd6a9d DN	191	reg = <0xff802000 0x2000>;
	192	interrupts = <0 91 4>;
	193	interrupt-names = "macirq";
	194	mac-address = [00 00 00 00 00 00];
05690e8a	195	resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>;
331085a4	196	reset-names = "stmmaceth", "ahb";
6e043c65 DN	197	clocks = <&clkmgr STRATIX10_EMAC1_CLK>, <&clkmgr STRATIX10_EMAC_PTP_CLK>;
6e043c65 DN	198	clock-names = "stmmaceth", "ptp_ref";
a27460c9 TT	199	tx-fifo-depth = <16384>;
a27460c9 TT	200	rx-fifo-depth = <16384>;
fd5ba6ee	201	snps,multicast-filter-bins = <256>;
ae3f46c8	202	iommus = <&smmu 2>;
9aa0cae1	203	altr,sysmgr-syscon = <&sysmgr 0x48 8>;
78cd6a9d DN	204	status = "disabled";
	205	};
	206
	207	gmac2: ethernet@ff804000 {
9aa0cae1	208	compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac";
78cd6a9d DN	209	reg = <0xff804000 0x2000>;
	210	interrupts = <0 92 4>;
	211	interrupt-names = "macirq";
	212	mac-address = [00 00 00 00 00 00];
05690e8a	213	resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>;
331085a4	214	reset-names = "stmmaceth", "ahb";
6e043c65 DN	215	clocks = <&clkmgr STRATIX10_EMAC2_CLK>, <&clkmgr STRATIX10_EMAC_PTP_CLK>;
6e043c65 DN	216	clock-names = "stmmaceth", "ptp_ref";
a27460c9 TT	217	tx-fifo-depth = <16384>;
a27460c9 TT	218	rx-fifo-depth = <16384>;
fd5ba6ee	219	snps,multicast-filter-bins = <256>;
ae3f46c8	220	iommus = <&smmu 3>;
9aa0cae1	221	altr,sysmgr-syscon = <&sysmgr 0x4c 16>;
78cd6a9d DN	222	status = "disabled";
	223	};
	224
	225	gpio0: gpio@ffc03200 {
	226	#address-cells = <1>;
	227	#size-cells = <0>;
	228	compatible = "snps,dw-apb-gpio";
	229	reg = <0xffc03200 0x100>;
788251fa	230	resets = <&rst GPIO0_RESET>;
78cd6a9d DN	231	status = "disabled";
	232
	233	porta: gpio-controller@0 {
	234	compatible = "snps,dw-apb-gpio-port";
	235	gpio-controller;
	236	#gpio-cells = <2>;
62b3c680	237	ngpios = <24>;
78cd6a9d DN	238	reg = <0>;
	239	interrupt-controller;
	240	#interrupt-cells = <2>;
	241	interrupts = <0 110 4>;
	242	};
	243	};
	244
	245	gpio1: gpio@ffc03300 {
	246	#address-cells = <1>;
	247	#size-cells = <0>;
	248	compatible = "snps,dw-apb-gpio";
	249	reg = <0xffc03300 0x100>;
788251fa	250	resets = <&rst GPIO1_RESET>;
78cd6a9d DN	251	status = "disabled";
	252
	253	portb: gpio-controller@0 {
	254	compatible = "snps,dw-apb-gpio-port";
	255	gpio-controller;
	256	#gpio-cells = <2>;
62b3c680	257	ngpios = <24>;
78cd6a9d DN	258	reg = <0>;
	259	interrupt-controller;
	260	#interrupt-cells = <2>;
a067fb42	261	interrupts = <0 111 4>;
78cd6a9d DN	262	};
	263	};
	264
	265	i2c0: i2c@ffc02800 {
	266	#address-cells = <1>;
	267	#size-cells = <0>;
	268	compatible = "snps,designware-i2c";
	269	reg = <0xffc02800 0x100>;
	270	interrupts = <0 103 4>;
788251fa	271	resets = <&rst I2C0_RESET>;
eebee19e	272	clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
78cd6a9d DN	273	status = "disabled";
	274	};
	275
	276	i2c1: i2c@ffc02900 {
	277	#address-cells = <1>;
	278	#size-cells = <0>;
	279	compatible = "snps,designware-i2c";
	280	reg = <0xffc02900 0x100>;
	281	interrupts = <0 104 4>;
788251fa	282	resets = <&rst I2C1_RESET>;
eebee19e	283	clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
78cd6a9d DN	284	status = "disabled";
	285	};
	286
	287	i2c2: i2c@ffc02a00 {
	288	#address-cells = <1>;
	289	#size-cells = <0>;
	290	compatible = "snps,designware-i2c";
	291	reg = <0xffc02a00 0x100>;
	292	interrupts = <0 105 4>;
788251fa	293	resets = <&rst I2C2_RESET>;
eebee19e	294	clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
78cd6a9d DN	295	status = "disabled";
	296	};
	297
	298	i2c3: i2c@ffc02b00 {
	299	#address-cells = <1>;
	300	#size-cells = <0>;
	301	compatible = "snps,designware-i2c";
	302	reg = <0xffc02b00 0x100>;
	303	interrupts = <0 106 4>;
788251fa	304	resets = <&rst I2C3_RESET>;
eebee19e	305	clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
78cd6a9d DN	306	status = "disabled";
	307	};
	308
	309	i2c4: i2c@ffc02c00 {
	310	#address-cells = <1>;
	311	#size-cells = <0>;
	312	compatible = "snps,designware-i2c";
	313	reg = <0xffc02c00 0x100>;
	314	interrupts = <0 107 4>;
788251fa	315	resets = <&rst I2C4_RESET>;
eebee19e	316	clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
78cd6a9d DN	317	status = "disabled";
	318	};
	319
8b794ab2	320	mmc: mmc@ff808000 {
78cd6a9d DN	321	#address-cells = <1>;
	322	#size-cells = <0>;
	323	compatible = "altr,socfpga-dw-mshc";
	324	reg = <0xff808000 0x1000>;
	325	interrupts = <0 96 4>;
	326	fifo-depth = <0x400>;
788251fa DN	327	resets = <&rst SDMMC_RESET>;
788251fa DN	328	reset-names = "reset";
d93101ab DN	329	clocks = <&clkmgr STRATIX10_L4_MP_CLK>,
	330	<&clkmgr STRATIX10_SDMMC_CLK>;
	331	clock-names = "biu", "ciu";
ae3f46c8	332	iommus = <&smmu 5>;
31354121	333	altr,sysmgr-syscon = <&sysmgr 0x28 4>;
78cd6a9d DN	334	status = "disabled";
	335	};
	336
681a5c71	337	nand: nand-controller@ffb90000 {
67c9fd2d DN	338	#address-cells = <1>;
	339	#size-cells = <0>;
	340	compatible = "altr,socfpga-denali-nand";
	341	reg = <0xffb90000 0x10000>,
	342	<0xffb80000 0x1000>;
	343	reg-names = "nand_data", "denali_reg";
	344	interrupts = <0 97 4>;
	345	clocks = <&clkmgr STRATIX10_NAND_CLK>,
	346	<&clkmgr STRATIX10_NAND_X_CLK>,
	347	<&clkmgr STRATIX10_NAND_ECC_CLK>;
	348	clock-names = "nand", "nand_x", "ecc";
	349	resets = <&rst NAND_RESET>, <&rst NAND_OCP_RESET>;
	350	status = "disabled";
	351	};
	352
78cd6a9d DN	353	ocram: sram@ffe00000 {
	354	compatible = "mmio-sram";
	355	reg = <0xffe00000 0x100000>;
6de298ff DN	356	#address-cells = <1>;
	357	#size-cells = <1>;
	358	ranges = <0 0xffe00000 0x100000>;
78cd6a9d DN	359	};
78cd6a9d DN	360
180be1b7	361	pdma: dma-controller@ffda0000 {
ab50a444 GM	362	compatible = "arm,pl330", "arm,primecell";
	363	reg = <0xffda0000 0x1000>;
	364	interrupts = <0 81 4>,
	365	<0 82 4>,
	366	<0 83 4>,
	367	<0 84 4>,
	368	<0 85 4>,
	369	<0 86 4>,
	370	<0 87 4>,
	371	<0 88 4>,
	372	<0 89 4>;
	373	#dma-cells = <1>;
ab50a444 GM	374	clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>;
ab50a444 GM	375	clock-names = "apb_pclk";
e10c1848 DN	376	resets = <&rst DMA_RESET>, <&rst DMA_OCP_RESET>;
e10c1848 DN	377	reset-names = "dma", "dma-ocp";
ab50a444 GM	378	};
ab50a444 GM	379
21ab7031 DN	380	pinctrl0: pinctrl@ffd13000 {
	381	compatible = "pinctrl-single";
	382	reg = <0xffd13000 0xA0>;
	383	#pinctrl-cells = <1>;
	384	pinctrl-single,register-width = <32>;
	385	pinctrl-single,function-mask = <0x0000000f>;
	386	};
	387
	388	pinctrl1: pinctrl@ffd13100 {
	389	compatible = "pinctrl-single";
	390	reg = <0xffd13100 0x20>;
	391	#pinctrl-cells = <1>;
	392	pinctrl-single,register-width = <32>;
	393	pinctrl-single,function-mask = <0x0000000f>;
	394	};
	395
78cd6a9d DN	396	rst: rstmgr@ffd11000 {
78cd6a9d DN	397	#reset-cells = <1>;
8bb4f3f5	398	compatible = "altr,stratix10-rst-mgr";
78cd6a9d DN	399	reg = <0xffd11000 0x1000>;
	400	};
	401
ae3f46c8 TT	402	smmu: iommu@fa000000 {
	403	compatible = "arm,mmu-500", "arm,smmu-v2";
	404	reg = <0xfa000000 0x40000>;
	405	#global-interrupts = <2>;
	406	#iommu-cells = <1>;
	407	clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>;
	408	clock-names = "iommu";
	409	interrupt-parent = <&intc>;
	410	interrupts = <0 128 4>, /* Global Secure Fault */
	411	<0 129 4>, /* Global Non-secure Fault */
	412	/* Non-secure Context Interrupts (32) */
	413	<0 138 4>, <0 139 4>, <0 140 4>, <0 141 4>,
	414	<0 142 4>, <0 143 4>, <0 144 4>, <0 145 4>,
	415	<0 146 4>, <0 147 4>, <0 148 4>, <0 149 4>,
	416	<0 150 4>, <0 151 4>, <0 152 4>, <0 153 4>,
	417	<0 154 4>, <0 155 4>, <0 156 4>, <0 157 4>,
	418	<0 158 4>, <0 159 4>, <0 160 4>, <0 161 4>,
	419	<0 162 4>, <0 163 4>, <0 164 4>, <0 165 4>,
	420	<0 166 4>, <0 167 4>, <0 168 4>, <0 169 4>;
	421	stream-match-mask = <0x7ff0>;
	422	status = "disabled";
	423	};
	424
78cd6a9d DN	425	spi0: spi@ffda4000 {
	426	compatible = "snps,dw-apb-ssi";
	427	#address-cells = <1>;
	428	#size-cells = <0>;
	429	reg = <0xffda4000 0x1000>;
889d1509 TT	430	interrupts = <0 99 4>;
889d1509 TT	431	resets = <&rst SPIM0_RESET>;
0ef91ccd	432	reset-names = "spi";
889d1509	433	reg-io-width = <4>;
4595299c	434	num-cs = <4>;
70455ac7	435	clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>;
78cd6a9d DN	436	status = "disabled";
	437	};
	438
	439	spi1: spi@ffda5000 {
	440	compatible = "snps,dw-apb-ssi";
	441	#address-cells = <1>;
	442	#size-cells = <0>;
	443	reg = <0xffda5000 0x1000>;
889d1509 TT	444	interrupts = <0 100 4>;
889d1509 TT	445	resets = <&rst SPIM1_RESET>;
0ef91ccd	446	reset-names = "spi";
889d1509	447	reg-io-width = <4>;
4595299c	448	num-cs = <4>;
70455ac7	449	clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>;
78cd6a9d DN	450	status = "disabled";
	451	};
	452
	453	sysmgr: sysmgr@ffd12000 {
8f4ebe9b	454	compatible = "altr,sys-mgr-s10","altr,sys-mgr";
74121b9a	455	reg = <0xffd12000 0x228>;
78cd6a9d DN	456	};
78cd6a9d DN	457
78cd6a9d DN	458	timer0: timer0@ffc03000 {
	459	compatible = "snps,dw-apb-timer";
	460	interrupts = <0 113 4>;
	461	reg = <0xffc03000 0x100>;
d93101ab DN	462	clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
d93101ab DN	463	clock-names = "timer";
78cd6a9d DN	464	};
	465
	466	timer1: timer1@ffc03100 {
	467	compatible = "snps,dw-apb-timer";
	468	interrupts = <0 114 4>;
	469	reg = <0xffc03100 0x100>;
d93101ab DN	470	clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
d93101ab DN	471	clock-names = "timer";
78cd6a9d DN	472	};
	473
	474	timer2: timer2@ffd00000 {
	475	compatible = "snps,dw-apb-timer";
	476	interrupts = <0 115 4>;
	477	reg = <0xffd00000 0x100>;
d93101ab DN	478	clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
d93101ab DN	479	clock-names = "timer";
78cd6a9d DN	480	};
	481
	482	timer3: timer3@ffd00100 {
	483	compatible = "snps,dw-apb-timer";
	484	interrupts = <0 116 4>;
	485	reg = <0xffd00100 0x100>;
d93101ab DN	486	clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
d93101ab DN	487	clock-names = "timer";
78cd6a9d DN	488	};
78cd6a9d DN	489
681a5c71	490	uart0: serial@ffc02000 {
78cd6a9d DN	491	compatible = "snps,dw-apb-uart";
	492	reg = <0xffc02000 0x100>;
	493	interrupts = <0 108 4>;
	494	reg-shift = <2>;
	495	reg-io-width = <4>;
788251fa	496	resets = <&rst UART0_RESET>;
d93101ab	497	clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
78cd6a9d DN	498	status = "disabled";
	499	};
	500
681a5c71	501	uart1: serial@ffc02100 {
78cd6a9d DN	502	compatible = "snps,dw-apb-uart";
	503	reg = <0xffc02100 0x100>;
	504	interrupts = <0 109 4>;
	505	reg-shift = <2>;
	506	reg-io-width = <4>;
788251fa	507	resets = <&rst UART1_RESET>;
d93101ab	508	clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
78cd6a9d DN	509	status = "disabled";
	510	};
	511
78cd6a9d DN	512	usb0: usb@ffb00000 {
	513	compatible = "snps,dwc2";
	514	reg = <0xffb00000 0x40000>;
	515	interrupts = <0 93 4>;
	516	phys = <&usbphy0>;
	517	phy-names = "usb2-phy";
33af8ca0 DN	518	resets = <&rst USB0_RESET>, <&rst USB0_OCP_RESET>;
33af8ca0 DN	519	reset-names = "dwc2", "dwc2-ecc";
03761ab1	520	clocks = <&clkmgr STRATIX10_USB_CLK>;
4b557e17	521	clock-names = "otg";
ae3f46c8	522	iommus = <&smmu 6>;
78cd6a9d DN	523	status = "disabled";
	524	};
	525
	526	usb1: usb@ffb40000 {
	527	compatible = "snps,dwc2";
	528	reg = <0xffb40000 0x40000>;
	529	interrupts = <0 94 4>;
	530	phys = <&usbphy0>;
	531	phy-names = "usb2-phy";
33af8ca0 DN	532	resets = <&rst USB1_RESET>, <&rst USB1_OCP_RESET>;
33af8ca0 DN	533	reset-names = "dwc2", "dwc2-ecc";
03761ab1	534	clocks = <&clkmgr STRATIX10_USB_CLK>;
91b491fd	535	clock-names = "otg";
ae3f46c8	536	iommus = <&smmu 7>;
78cd6a9d DN	537	status = "disabled";
	538	};
	539
	540	watchdog0: watchdog@ffd00200 {
	541	compatible = "snps,dw-wdt";
	542	reg = <0xffd00200 0x100>;
	543	interrupts = <0 117 4>;
788251fa	544	resets = <&rst WATCHDOG0_RESET>;
03761ab1	545	clocks = <&clkmgr STRATIX10_L4_SYS_FREE_CLK>;
78cd6a9d DN	546	status = "disabled";
	547	};
	548
	549	watchdog1: watchdog@ffd00300 {
	550	compatible = "snps,dw-wdt";
	551	reg = <0xffd00300 0x100>;
	552	interrupts = <0 118 4>;
788251fa	553	resets = <&rst WATCHDOG1_RESET>;
03761ab1	554	clocks = <&clkmgr STRATIX10_L4_SYS_FREE_CLK>;
78cd6a9d DN	555	status = "disabled";
	556	};
	557
	558	watchdog2: watchdog@ffd00400 {
	559	compatible = "snps,dw-wdt";
	560	reg = <0xffd00400 0x100>;
	561	interrupts = <0 125 4>;
788251fa	562	resets = <&rst WATCHDOG2_RESET>;
03761ab1	563	clocks = <&clkmgr STRATIX10_L4_SYS_FREE_CLK>;
78cd6a9d DN	564	status = "disabled";
	565	};
	566
	567	watchdog3: watchdog@ffd00500 {
	568	compatible = "snps,dw-wdt";
	569	reg = <0xffd00500 0x100>;
	570	interrupts = <0 126 4>;
788251fa	571	resets = <&rst WATCHDOG3_RESET>;
03761ab1	572	clocks = <&clkmgr STRATIX10_L4_SYS_FREE_CLK>;
78cd6a9d DN	573	status = "disabled";
78cd6a9d DN	574	};
91fdd827	575
446fd7af TT	576	sdr: sdr@f8011100 {
	577	compatible = "altr,sdr-ctl", "syscon";
	578	reg = <0xf8011100 0xc0>;
	579	};
	580
91fdd827	581	eccmgr {
74676a8e TT	582	compatible = "altr,socfpga-s10-ecc-manager",
74676a8e TT	583	"altr,socfpga-a10-ecc-manager";
3ce078ff TT	584	altr,sysmgr-syscon = <&sysmgr>;
	585	#address-cells = <1>;
	586	#size-cells = <1>;
74676a8e	587	interrupts = <0 15 4>;
91fdd827 TT	588	interrupt-controller;
91fdd827 TT	589	#interrupt-cells = <2>;
3ce078ff	590	ranges;
91fdd827 TT	591
	592	sdramedac {
	593	compatible = "altr,sdram-edac-s10";
446fd7af	594	altr,sdr-syscon = <&sdr>;
74676a8e	595	interrupts = <16 4>;
91fdd827	596	};
6b2da9ff	597
3c4fcb89 TT	598	ocram-ecc@ff8cc000 {
	599	compatible = "altr,socfpga-s10-ocram-ecc",
	600	"altr,socfpga-a10-ocram-ecc";
	601	reg = <0xff8cc000 0x100>;
	602	altr,ecc-parent = <&ocram>;
	603	interrupts = <1 4>;
	604	};
	605
6b2da9ff	606	usb0-ecc@ff8c4000 {
74676a8e TT	607	compatible = "altr,socfpga-s10-usb-ecc",
74676a8e TT	608	"altr,socfpga-usb-ecc";
6b2da9ff TT	609	reg = <0xff8c4000 0x100>;
6b2da9ff TT	610	altr,ecc-parent = <&usb0>;
74676a8e	611	interrupts = <2 4>;
6b2da9ff TT	612	};
	613
	614	emac0-rx-ecc@ff8c0000 {
74676a8e TT	615	compatible = "altr,socfpga-s10-eth-mac-ecc",
74676a8e TT	616	"altr,socfpga-eth-mac-ecc";
6b2da9ff TT	617	reg = <0xff8c0000 0x100>;
6b2da9ff TT	618	altr,ecc-parent = <&gmac0>;
74676a8e	619	interrupts = <4 4>;
6b2da9ff TT	620	};
	621
	622	emac0-tx-ecc@ff8c0400 {
74676a8e TT	623	compatible = "altr,socfpga-s10-eth-mac-ecc",
74676a8e TT	624	"altr,socfpga-eth-mac-ecc";
6b2da9ff TT	625	reg = <0xff8c0400 0x100>;
6b2da9ff TT	626	altr,ecc-parent = <&gmac0>;
74676a8e	627	interrupts = <5 4>;
6b2da9ff TT	628	};
6b2da9ff TT	629
91fdd827	630	};
0cb140d0 TT	631
0cb140d0 TT	632	qspi: spi@ff8d2000 {
85d616dd	633	compatible = "intel,socfpga-qspi", "cdns,qspi-nor";
0cb140d0 TT	634	#address-cells = <1>;
	635	#size-cells = <0>;
	636	reg = <0xff8d2000 0x100>,
	637	<0xff900000 0x100000>;
	638	interrupts = <0 3 4>;
	639	cdns,fifo-depth = <128>;
	640	cdns,fifo-width = <4>;
	641	cdns,trigger-address = <0x00000000>;
	642	clocks = <&qspi_clk>;
	643
	644	status = "disabled";
	645	};
78cd6a9d	646	};
5dad11fa DN	647
	648	usbphy0: usbphy0 {
	649	compatible = "usb-nop-xceiv";
	650	#phy-cells = <0>;
	651	};
78cd6a9d	652	};