Commit | Line | Data |
---|---|---|
e54be32d IZ |
1 | // SPDX-License-Identifier: (GPL-2.0+ or MIT) |
2 | /* | |
3 | * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io> | |
4 | */ | |
5 | ||
6 | #include <dt-bindings/interrupt-controller/arm-gic.h> | |
95beb93d | 7 | #include <dt-bindings/clock/sun50i-h6-ccu.h> |
de2b5552 | 8 | #include <dt-bindings/clock/sun50i-h6-r-ccu.h> |
95beb93d | 9 | #include <dt-bindings/reset/sun50i-h6-ccu.h> |
de2b5552 | 10 | #include <dt-bindings/reset/sun50i-h6-r-ccu.h> |
e54be32d IZ |
11 | |
12 | / { | |
13 | interrupt-parent = <&gic>; | |
14 | #address-cells = <1>; | |
15 | #size-cells = <1>; | |
16 | ||
17 | cpus { | |
18 | #address-cells = <1>; | |
19 | #size-cells = <0>; | |
20 | ||
21 | cpu0: cpu@0 { | |
22 | compatible = "arm,cortex-a53", "arm,armv8"; | |
23 | device_type = "cpu"; | |
24 | reg = <0>; | |
25 | enable-method = "psci"; | |
26 | }; | |
27 | ||
28 | cpu1: cpu@1 { | |
29 | compatible = "arm,cortex-a53", "arm,armv8"; | |
30 | device_type = "cpu"; | |
31 | reg = <1>; | |
32 | enable-method = "psci"; | |
33 | }; | |
34 | ||
35 | cpu2: cpu@2 { | |
36 | compatible = "arm,cortex-a53", "arm,armv8"; | |
37 | device_type = "cpu"; | |
38 | reg = <2>; | |
39 | enable-method = "psci"; | |
40 | }; | |
41 | ||
42 | cpu3: cpu@3 { | |
43 | compatible = "arm,cortex-a53", "arm,armv8"; | |
44 | device_type = "cpu"; | |
45 | reg = <3>; | |
46 | enable-method = "psci"; | |
47 | }; | |
48 | }; | |
49 | ||
50 | iosc: internal-osc-clk { | |
51 | #clock-cells = <0>; | |
52 | compatible = "fixed-clock"; | |
53 | clock-frequency = <16000000>; | |
54 | clock-accuracy = <300000000>; | |
55 | clock-output-names = "iosc"; | |
56 | }; | |
57 | ||
58 | osc24M: osc24M_clk { | |
59 | #clock-cells = <0>; | |
60 | compatible = "fixed-clock"; | |
61 | clock-frequency = <24000000>; | |
62 | clock-output-names = "osc24M"; | |
63 | }; | |
64 | ||
65 | osc32k: osc32k_clk { | |
66 | #clock-cells = <0>; | |
67 | compatible = "fixed-clock"; | |
68 | clock-frequency = <32768>; | |
69 | clock-output-names = "osc32k"; | |
70 | }; | |
71 | ||
72 | psci { | |
73 | compatible = "arm,psci-0.2"; | |
74 | method = "smc"; | |
75 | }; | |
76 | ||
77 | timer { | |
78 | compatible = "arm,armv8-timer"; | |
79 | interrupts = <GIC_PPI 13 | |
80 | (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, | |
81 | <GIC_PPI 14 | |
82 | (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, | |
83 | <GIC_PPI 11 | |
84 | (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, | |
85 | <GIC_PPI 10 | |
86 | (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; | |
87 | }; | |
88 | ||
89 | soc { | |
90 | compatible = "simple-bus"; | |
91 | #address-cells = <1>; | |
92 | #size-cells = <1>; | |
93 | ranges; | |
94 | ||
95 | ccu: clock@3001000 { | |
96 | compatible = "allwinner,sun50i-h6-ccu"; | |
97 | reg = <0x03001000 0x1000>; | |
98 | clocks = <&osc24M>, <&osc32k>, <&iosc>; | |
99 | clock-names = "hosc", "losc", "iosc"; | |
100 | #clock-cells = <1>; | |
101 | #reset-cells = <1>; | |
102 | }; | |
103 | ||
104 | gic: interrupt-controller@3021000 { | |
105 | compatible = "arm,gic-400"; | |
106 | reg = <0x03021000 0x1000>, | |
107 | <0x03022000 0x2000>, | |
108 | <0x03024000 0x2000>, | |
109 | <0x03026000 0x2000>; | |
110 | interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; | |
111 | interrupt-controller; | |
112 | #interrupt-cells = <3>; | |
113 | }; | |
114 | ||
115 | pio: pinctrl@300b000 { | |
116 | compatible = "allwinner,sun50i-h6-pinctrl"; | |
117 | reg = <0x0300b000 0x400>; | |
118 | interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, | |
119 | <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, | |
120 | <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, | |
121 | <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; | |
95beb93d | 122 | clocks = <&ccu CLK_APB1>, <&osc24M>, <&osc32k>; |
e54be32d IZ |
123 | clock-names = "apb", "hosc", "losc"; |
124 | gpio-controller; | |
125 | #gpio-cells = <3>; | |
126 | interrupt-controller; | |
127 | #interrupt-cells = <3>; | |
128 | ||
8f54bd15 IZ |
129 | mmc0_pins: mmc0-pins { |
130 | pins = "PF0", "PF1", "PF2", "PF3", | |
131 | "PF4", "PF5"; | |
132 | function = "mmc0"; | |
133 | drive-strength = <30>; | |
134 | bias-pull-up; | |
135 | }; | |
136 | ||
137 | mmc2_pins: mmc2-pins { | |
138 | pins = "PC1", "PC4", "PC5", "PC6", | |
139 | "PC7", "PC8", "PC9", "PC10", | |
140 | "PC11", "PC12", "PC13", "PC14"; | |
141 | function = "mmc2"; | |
142 | drive-strength = <30>; | |
143 | bias-pull-up; | |
144 | }; | |
145 | ||
e54be32d IZ |
146 | uart0_ph_pins: uart0-ph { |
147 | pins = "PH0", "PH1"; | |
148 | function = "uart0"; | |
149 | }; | |
150 | }; | |
151 | ||
8f54bd15 IZ |
152 | mmc0: mmc@4020000 { |
153 | compatible = "allwinner,sun50i-h6-mmc", | |
154 | "allwinner,sun50i-a64-mmc"; | |
155 | reg = <0x04020000 0x1000>; | |
156 | clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; | |
157 | clock-names = "ahb", "mmc"; | |
158 | resets = <&ccu RST_BUS_MMC0>; | |
159 | reset-names = "ahb"; | |
160 | interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; | |
161 | status = "disabled"; | |
162 | #address-cells = <1>; | |
163 | #size-cells = <0>; | |
164 | }; | |
165 | ||
166 | mmc1: mmc@4021000 { | |
167 | compatible = "allwinner,sun50i-h6-mmc", | |
168 | "allwinner,sun50i-a64-mmc"; | |
169 | reg = <0x04021000 0x1000>; | |
170 | clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; | |
171 | clock-names = "ahb", "mmc"; | |
172 | resets = <&ccu RST_BUS_MMC1>; | |
173 | reset-names = "ahb"; | |
174 | interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; | |
175 | status = "disabled"; | |
176 | #address-cells = <1>; | |
177 | #size-cells = <0>; | |
178 | }; | |
179 | ||
180 | mmc2: mmc@4022000 { | |
181 | compatible = "allwinner,sun50i-h6-emmc", | |
182 | "allwinner,sun50i-a64-emmc"; | |
183 | reg = <0x04022000 0x1000>; | |
184 | clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; | |
185 | clock-names = "ahb", "mmc"; | |
186 | resets = <&ccu RST_BUS_MMC2>; | |
187 | reset-names = "ahb"; | |
188 | interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; | |
189 | status = "disabled"; | |
190 | #address-cells = <1>; | |
191 | #size-cells = <0>; | |
192 | }; | |
193 | ||
e54be32d IZ |
194 | uart0: serial@5000000 { |
195 | compatible = "snps,dw-apb-uart"; | |
196 | reg = <0x05000000 0x400>; | |
197 | interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; | |
198 | reg-shift = <2>; | |
199 | reg-io-width = <4>; | |
95beb93d IZ |
200 | clocks = <&ccu CLK_BUS_UART0>; |
201 | resets = <&ccu RST_BUS_UART0>; | |
e54be32d IZ |
202 | status = "disabled"; |
203 | }; | |
204 | ||
205 | uart1: serial@5000400 { | |
206 | compatible = "snps,dw-apb-uart"; | |
207 | reg = <0x05000400 0x400>; | |
208 | interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; | |
209 | reg-shift = <2>; | |
210 | reg-io-width = <4>; | |
95beb93d IZ |
211 | clocks = <&ccu CLK_BUS_UART1>; |
212 | resets = <&ccu RST_BUS_UART1>; | |
e54be32d IZ |
213 | status = "disabled"; |
214 | }; | |
215 | ||
216 | uart2: serial@5000800 { | |
217 | compatible = "snps,dw-apb-uart"; | |
218 | reg = <0x05000800 0x400>; | |
219 | interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; | |
220 | reg-shift = <2>; | |
221 | reg-io-width = <4>; | |
95beb93d IZ |
222 | clocks = <&ccu CLK_BUS_UART2>; |
223 | resets = <&ccu RST_BUS_UART2>; | |
e54be32d IZ |
224 | status = "disabled"; |
225 | }; | |
226 | ||
227 | uart3: serial@5000c00 { | |
228 | compatible = "snps,dw-apb-uart"; | |
229 | reg = <0x05000c00 0x400>; | |
230 | interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; | |
231 | reg-shift = <2>; | |
232 | reg-io-width = <4>; | |
95beb93d IZ |
233 | clocks = <&ccu CLK_BUS_UART3>; |
234 | resets = <&ccu RST_BUS_UART3>; | |
e54be32d IZ |
235 | status = "disabled"; |
236 | }; | |
05bdee31 IZ |
237 | |
238 | r_ccu: clock@7010000 { | |
239 | compatible = "allwinner,sun50i-h6-r-ccu"; | |
240 | reg = <0x07010000 0x400>; | |
241 | clocks = <&osc24M>, <&osc32k>, <&iosc>, | |
242 | <&ccu CLK_PLL_PERIPH0>; | |
243 | clock-names = "hosc", "losc", "iosc", "pll-periph"; | |
244 | #clock-cells = <1>; | |
245 | #reset-cells = <1>; | |
246 | }; | |
71f9bdbd | 247 | |
1ecefb83 IZ |
248 | r_intc: interrupt-controller@7021000 { |
249 | compatible = "allwinner,sun50i-h6-r-intc", | |
250 | "allwinner,sun6i-a31-r-intc"; | |
251 | interrupt-controller; | |
252 | #interrupt-cells = <2>; | |
253 | reg = <0x07021000 0x400>; | |
254 | interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; | |
255 | }; | |
256 | ||
71f9bdbd IZ |
257 | r_pio: pinctrl@7022000 { |
258 | compatible = "allwinner,sun50i-h6-r-pinctrl"; | |
259 | reg = <0x07022000 0x400>; | |
260 | interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, | |
261 | <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; | |
de2b5552 | 262 | clocks = <&r_ccu CLK_R_APB1>, <&osc24M>, <&osc32k>; |
71f9bdbd IZ |
263 | clock-names = "apb", "hosc", "losc"; |
264 | gpio-controller; | |
265 | #gpio-cells = <3>; | |
266 | interrupt-controller; | |
267 | #interrupt-cells = <3>; | |
e9a23366 IZ |
268 | |
269 | r_i2c_pins: r-i2c { | |
270 | pins = "PL0", "PL1"; | |
271 | function = "s_i2c"; | |
272 | }; | |
273 | }; | |
274 | ||
275 | r_i2c: i2c@7081400 { | |
276 | compatible = "allwinner,sun6i-a31-i2c"; | |
277 | reg = <0x07081400 0x400>; | |
278 | interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; | |
de2b5552 CYT |
279 | clocks = <&r_ccu CLK_R_APB2_I2C>; |
280 | resets = <&r_ccu RST_R_APB2_I2C>; | |
e9a23366 IZ |
281 | pinctrl-names = "default"; |
282 | pinctrl-0 = <&r_i2c_pins>; | |
283 | status = "disabled"; | |
284 | #address-cells = <1>; | |
285 | #size-cells = <0>; | |
71f9bdbd | 286 | }; |
e54be32d IZ |
287 | }; |
288 | }; |