Commit | Line | Data |
---|---|---|
ec8f24b7 | 1 | # SPDX-License-Identifier: GPL-2.0-only |
eed6b3eb OJ |
2 | menu "Platform selection" |
3 | ||
c88cc3ee AF |
4 | config ARCH_ACTIONS |
5 | bool "Actions Semi Platforms" | |
6 | select OWL_TIMER | |
e0c27a10 | 7 | select PINCTRL |
c88cc3ee AF |
8 | help |
9 | This enables support for the Actions Semiconductor S900 SoC family. | |
10 | ||
4b36daf9 DN |
11 | config ARCH_AGILEX |
12 | bool "Intel's Agilex SoCFPGA Family" | |
13 | help | |
14 | This enables support for Intel's Agilex SoCFPGA Family. | |
15 | ||
a427485a DN |
16 | config ARCH_N5X |
17 | bool "Intel's eASIC N5X SoCFPGA Family" | |
18 | help | |
19 | This enables support for Intel's eASIC N5X SoCFPGA Family. | |
20 | ||
ce3dd55b AP |
21 | config ARCH_SUNXI |
22 | bool "Allwinner sunxi 64-bit SoC Family" | |
900a9020 | 23 | select ARCH_HAS_RESET_CONTROLLER |
23485482 | 24 | select GENERIC_IRQ_CHIP |
4e346146 SH |
25 | select IRQ_DOMAIN_HIERARCHY |
26 | select IRQ_FASTEOI_HIERARCHY_HANDLERS | |
d229d205 | 27 | select PINCTRL |
900a9020 | 28 | select RESET_CONTROLLER |
ce3dd55b AP |
29 | help |
30 | This enables support for Allwinner sunxi based SoCs like the A64. | |
31 | ||
e2f0abaf AT |
32 | config ARCH_ALPINE |
33 | bool "Annapurna Labs Alpine platform" | |
5a3f75a4 | 34 | select ALPINE_MSI if PCI |
e2f0abaf AT |
35 | help |
36 | This enables support for the Annapurna Labs Alpine | |
37 | Soc family. | |
38 | ||
628d30d1 EA |
39 | config ARCH_BCM2835 |
40 | bool "Broadcom BCM2835 family" | |
bb0eb050 | 41 | select TIMER_OF |
da9a1c67 | 42 | select GPIOLIB |
7a9b6be9 | 43 | select MFD_CORE |
628d30d1 EA |
44 | select PINCTRL |
45 | select PINCTRL_BCM2835 | |
46 | select ARM_AMBA | |
781fa0a9 | 47 | select ARM_GIC |
628d30d1 | 48 | select ARM_TIMER_SP804 |
5674e314 | 49 | select BRCMSTB_L2_IRQ |
628d30d1 | 50 | help |
781fa0a9 SW |
51 | This enables support for the Broadcom BCM2837 and BCM2711 SoC. |
52 | These SoCs are used in the Raspberry Pi 3 and 4 devices. | |
628d30d1 | 53 | |
dccb22d0 RM |
54 | config ARCH_BCM4908 |
55 | bool "Broadcom BCM4908 family" | |
56 | select GPIOLIB | |
57 | help | |
58 | This enables support for the Broadcom BCM4906, BCM4908 and | |
59 | BCM49408 SoCs. These SoCs use Brahma-B53 cores and can be | |
60 | found in home routers. | |
61 | ||
36b7c583 RJ |
62 | config ARCH_BCM_IPROC |
63 | bool "Broadcom iProc SoC Family" | |
382618bb | 64 | select COMMON_CLK_IPROC |
da9a1c67 | 65 | select GPIOLIB |
382618bb | 66 | select PINCTRL |
36b7c583 RJ |
67 | help |
68 | This enables support for Broadcom iProc based SoCs | |
69 | ||
dd40fd92 JZ |
70 | config ARCH_BERLIN |
71 | bool "Marvell Berlin SoC Family" | |
72 | select DW_APB_ICTL | |
b0fc70ce | 73 | select DW_APB_TIMER_OF |
da9a1c67 | 74 | select GPIOLIB |
75d8e1ba | 75 | select PINCTRL |
dd40fd92 JZ |
76 | help |
77 | This enables support for Marvell Berlin SoC Family | |
78 | ||
ea367d38 MS |
79 | config ARCH_BITMAIN |
80 | bool "Bitmain SoC Platforms" | |
81 | help | |
82 | This enables support for the Bitmain SoC Family. | |
83 | ||
37eb56dc FF |
84 | config ARCH_BRCMSTB |
85 | bool "Broadcom Set-Top-Box SoCs" | |
809eec69 | 86 | select ARCH_HAS_RESET_CONTROLLER |
bf0349df | 87 | select BCM7038_L1_IRQ |
37eb56dc FF |
88 | select BRCMSTB_L2_IRQ |
89 | select GENERIC_IRQ_CHIP | |
724cf0ae | 90 | select PINCTRL |
37eb56dc FF |
91 | help |
92 | This enables support for Broadcom's ARMv8 Set Top Box SoCs | |
93 | ||
eed6b3eb | 94 | config ARCH_EXYNOS |
c87b3e97 | 95 | bool "ARMv8 based Samsung Exynos SoC family" |
eed6b3eb | 96 | select COMMON_CLK_SAMSUNG |
a6fe8c77 | 97 | select EXYNOS_CHIPID |
caab3df9 KK |
98 | select EXYNOS_PM_DOMAINS if PM_GENERIC_DOMAINS |
99 | select EXYNOS_PMU | |
eed6b3eb OJ |
100 | select HAVE_S3C_RTC if RTC_CLASS |
101 | select PINCTRL | |
102 | select PINCTRL_EXYNOS | |
5220a73a | 103 | select PM_GENERIC_DOMAINS if PM |
3b3428e3 | 104 | select SOC_SAMSUNG |
eed6b3eb | 105 | help |
c87b3e97 | 106 | This enables support for ARMv8 based Samsung Exynos SoC family. |
eed6b3eb | 107 | |
31a91c87 LP |
108 | config ARCH_SPARX5 |
109 | bool "ARMv8 based Microchip Sparx5 SoC family" | |
110 | select PINCTRL | |
111 | select DW_APB_TIMER_OF | |
112 | help | |
113 | This enables support for the Microchip Sparx5 ARMv8-based | |
114 | SoC family of TSN-capable gigabit switches. | |
115 | ||
116 | The SparX-5 Ethernet switch family provides a rich set of | |
117 | switching features such as advanced TCAM-based VLAN and QoS | |
118 | processing enabling delivery of differentiated services, and | |
119 | security through TCAM-based frame processing using versatile | |
120 | content aware processor (VCAP). | |
121 | ||
c7724572 NM |
122 | config ARCH_K3 |
123 | bool "Texas Instruments Inc. K3 multicore SoC architecture" | |
124 | select PM_GENERIC_DOMAINS if PM | |
009669e7 | 125 | select MAILBOX |
a6b112b0 | 126 | select SOC_TI |
009669e7 LV |
127 | select TI_MESSAGE_MANAGER |
128 | select TI_SCI_PROTOCOL | |
129 | select TI_SCI_INTR_IRQCHIP | |
130 | select TI_SCI_INTA_IRQCHIP | |
ec792ecf | 131 | select TI_K3_SOCINFO |
c7724572 NM |
132 | help |
133 | This enables support for Texas Instruments' K3 multicore SoC | |
134 | architecture. | |
135 | ||
53a5fde0 BS |
136 | config ARCH_LAYERSCAPE |
137 | bool "ARMv8 based Freescale Layerscape SoC family" | |
eeb3d68b | 138 | select EDAC_SUPPORT |
eed6b3eb | 139 | help |
53a5fde0 | 140 | This enables support for the Freescale Layerscape SoC family. |
eed6b3eb | 141 | |
198ed962 CM |
142 | config ARCH_LG1K |
143 | bool "LG Electronics LG1K SoC Family" | |
144 | help | |
145 | This enables support for LG Electronics LG1K SoC Family | |
146 | ||
eed6b3eb OJ |
147 | config ARCH_HISI |
148 | bool "Hisilicon SoC Family" | |
2b905d3a | 149 | select ARM_TIMER_SP804 |
f9db43bc | 150 | select HISILICON_IRQ_MBIGEN if PCI |
21adc4d7 | 151 | select PINCTRL |
eed6b3eb OJ |
152 | help |
153 | This enables support for Hisilicon ARMv8 SoC family | |
154 | ||
a6a4abf8 DA |
155 | config ARCH_KEEMBAY |
156 | bool "Keem Bay SoC" | |
157 | help | |
158 | This enables support for Intel Movidius SoC code-named Keem Bay. | |
159 | ||
eed6b3eb | 160 | config ARCH_MEDIATEK |
598f9b2e | 161 | bool "MediaTek SoC Family" |
eed6b3eb OJ |
162 | select ARM_GIC |
163 | select PINCTRL | |
c050b45d | 164 | select MTK_TIMER |
eed6b3eb | 165 | help |
598f9b2e SW |
166 | This enables support for MediaTek MT27xx, MT65xx, MT76xx |
167 | & MT81xx ARMv8 SoCs | |
eed6b3eb | 168 | |
451e9e54 AF |
169 | config ARCH_MESON |
170 | bool "Amlogic Platforms" | |
f2c2122a | 171 | select MESON_IRQ_GPIO |
451e9e54 | 172 | help |
b3077ffc JB |
173 | This enables support for the arm64 based Amlogic SoCs |
174 | such as the s905, S905X/D, S912, A113X/D or S905X/D2 | |
451e9e54 | 175 | |
b4f596b1 GC |
176 | config ARCH_MVEBU |
177 | bool "Marvell EBU SoC Family" | |
ad87c0f6 TP |
178 | select ARMADA_AP806_SYSCON |
179 | select ARMADA_CP110_SYSCON | |
ff60d834 | 180 | select ARMADA_37XX_CLK |
d2718d13 GC |
181 | select GPIOLIB |
182 | select GPIOLIB_IRQCHIP | |
29ad6bd9 TP |
183 | select MVEBU_GICP |
184 | select MVEBU_ICU | |
b3920b2b | 185 | select MVEBU_ODMI |
04208a24 | 186 | select MVEBU_PIC |
228197c5 | 187 | select MVEBU_SEI |
d2718d13 GC |
188 | select OF_GPIO |
189 | select PINCTRL | |
190 | select PINCTRL_ARMADA_37XX | |
c4c14365 GC |
191 | select PINCTRL_ARMADA_AP806 |
192 | select PINCTRL_ARMADA_CP110 | |
b4f596b1 | 193 | help |
b3920b2b TP |
194 | This enables support for Marvell EBU familly, including: |
195 | - Armada 3700 SoC Family | |
196 | - Armada 7K SoC Family | |
197 | - Armada 8K SoC Family | |
b4f596b1 | 198 | |
930507c1 LS |
199 | config ARCH_MXC |
200 | bool "ARMv8 based NXP i.MX SoC family" | |
201 | select ARM64_ERRATUM_843419 | |
a29c7823 | 202 | select ARM64_ERRATUM_845719 if COMPAT |
67b92823 | 203 | select IMX_GPCV2 |
84a2ab25 LS |
204 | select IMX_GPCV2_PM_DOMAINS |
205 | select PM | |
206 | select PM_GENERIC_DOMAINS | |
fafaa0a2 | 207 | select SOC_BUS |
1991529f | 208 | select TIMER_IMX_SYS_CTR |
930507c1 LS |
209 | help |
210 | This enables support for the ARMv8 based SoCs in the | |
211 | NXP i.MX family. | |
212 | ||
eed6b3eb OJ |
213 | config ARCH_QCOM |
214 | bool "Qualcomm Platforms" | |
e19811a8 | 215 | select GPIOLIB |
eed6b3eb OJ |
216 | select PINCTRL |
217 | help | |
218 | This enables support for the ARMv8 based Qualcomm chipsets. | |
219 | ||
1b0d665e AF |
220 | config ARCH_REALTEK |
221 | bool "Realtek Platforms" | |
e3ca9556 | 222 | select RESET_CONTROLLER |
1b0d665e AF |
223 | help |
224 | This enables support for the ARMv8 based Realtek chipsets, | |
225 | like the RTD1295. | |
226 | ||
26a7e06d SH |
227 | config ARCH_RENESAS |
228 | bool "Renesas SoC Platforms" | |
9374eee3 | 229 | select GPIOLIB |
26a7e06d | 230 | select PINCTRL |
8d6799a9 | 231 | select SOC_BUS |
26a7e06d SH |
232 | help |
233 | This enables support for the ARMv8 based Renesas SoCs. | |
234 | ||
0964d660 GU |
235 | config ARCH_ROCKCHIP |
236 | bool "Rockchip Platforms" | |
237 | select ARCH_HAS_RESET_CONTROLLER | |
238 | select GPIOLIB | |
239 | select PINCTRL | |
240 | select PINCTRL_ROCKCHIP | |
241 | select PM | |
242 | select ROCKCHIP_TIMER | |
243 | help | |
244 | This enables support for the ARMv8 based Rockchip chipsets, | |
245 | like the RK3368. | |
246 | ||
3d4e0158 MM |
247 | config ARCH_S32 |
248 | bool "NXP S32 SoC Family" | |
249 | help | |
250 | This enables support for the NXP S32 family of processors. | |
251 | ||
0964d660 GU |
252 | config ARCH_SEATTLE |
253 | bool "AMD Seattle SoC Family" | |
254 | help | |
255 | This enables support for AMD Seattle SOC Family | |
256 | ||
78cd6a9d DN |
257 | config ARCH_STRATIX10 |
258 | bool "Altera's Stratix 10 SoCFPGA Family" | |
910499e1 | 259 | select ARCH_INTEL_SOCFPGA |
78cd6a9d DN |
260 | help |
261 | This enables support for Altera's Stratix 10 SoCFPGA Family. | |
262 | ||
910499e1 KK |
263 | config ARCH_INTEL_SOCFPGA |
264 | bool | |
265 | ||
0964d660 GU |
266 | config ARCH_SYNQUACER |
267 | bool "Socionext SynQuacer SoC Family" | |
268 | ||
eed6b3eb OJ |
269 | config ARCH_TEGRA |
270 | bool "NVIDIA Tegra SoC Family" | |
271 | select ARCH_HAS_RESET_CONTROLLER | |
2e988a83 | 272 | select ARM_GIC_PM |
eed6b3eb | 273 | select CLKSRC_MMIO |
bb0eb050 | 274 | select TIMER_OF |
da9a1c67 | 275 | select GPIOLIB |
eed6b3eb | 276 | select PINCTRL |
98823241 JH |
277 | select PM |
278 | select PM_GENERIC_DOMAINS | |
eed6b3eb OJ |
279 | select RESET_CONTROLLER |
280 | help | |
281 | This enables support for the NVIDIA Tegra SoC family. | |
282 | ||
eed6b3eb | 283 | config ARCH_SPRD |
b5f73d47 | 284 | bool "Spreadtrum SoC platform" |
eed6b3eb OJ |
285 | help |
286 | Support for Spreadtrum ARM based SoCs | |
287 | ||
288 | config ARCH_THUNDER | |
289 | bool "Cavium Inc. Thunder SoC Family" | |
290 | help | |
291 | This enables support for Cavium's Thunder Family of SoCs. | |
292 | ||
03b6fd5d J |
293 | config ARCH_THUNDER2 |
294 | bool "Cavium ThunderX2 Server Processors" | |
295 | select GPIOLIB | |
296 | help | |
297 | This enables support for Cavium's ThunderX2 CN99XX family of | |
298 | server processors. | |
299 | ||
56aaafb6 MY |
300 | config ARCH_UNIPHIER |
301 | bool "Socionext UniPhier SoC Family" | |
75924903 | 302 | select ARCH_HAS_RESET_CONTROLLER |
56aaafb6 | 303 | select PINCTRL |
ab6ab445 | 304 | select RESET_CONTROLLER |
56aaafb6 MY |
305 | help |
306 | This enables support for Socionext UniPhier SoC family. | |
307 | ||
eed6b3eb OJ |
308 | config ARCH_VEXPRESS |
309 | bool "ARMv8 software model (Versatile Express)" | |
da9a1c67 | 310 | select GPIOLIB |
8da7cc08 SH |
311 | select PM |
312 | select PM_GENERIC_DOMAINS | |
eed6b3eb OJ |
313 | help |
314 | This enables support for the ARMv8 software model (Versatile | |
315 | Express). | |
316 | ||
0aa56c7e NI |
317 | config ARCH_VISCONTI |
318 | bool "Toshiba Visconti SoC Family" | |
319 | select PINCTRL | |
320 | select PINCTRL_VISCONTI | |
321 | help | |
322 | This enables support for Toshiba Visconti SoCs Family. | |
323 | ||
5bfb3889 | 324 | config ARCH_VULCAN |
a314520d | 325 | def_bool n |
5bfb3889 | 326 | |
eed6b3eb OJ |
327 | config ARCH_XGENE |
328 | bool "AppliedMicro X-Gene SOC Family" | |
329 | help | |
330 | This enables support for AppliedMicro X-Gene SOC Family | |
331 | ||
332 | config ARCH_ZYNQMP | |
333 | bool "Xilinx ZynqMP Family" | |
334 | help | |
335 | This enables support for Xilinx ZynqMP Family | |
336 | ||
337 | endmenu |