Commit | Line | Data |
---|---|---|
ec8f24b7 | 1 | # SPDX-License-Identifier: GPL-2.0-only |
eed6b3eb OJ |
2 | menu "Platform selection" |
3 | ||
c88cc3ee AF |
4 | config ARCH_ACTIONS |
5 | bool "Actions Semi Platforms" | |
6 | select OWL_TIMER | |
e0c27a10 | 7 | select PINCTRL |
c88cc3ee AF |
8 | help |
9 | This enables support for the Actions Semiconductor S900 SoC family. | |
10 | ||
4b36daf9 DN |
11 | config ARCH_AGILEX |
12 | bool "Intel's Agilex SoCFPGA Family" | |
13 | help | |
14 | This enables support for Intel's Agilex SoCFPGA Family. | |
15 | ||
ce3dd55b AP |
16 | config ARCH_SUNXI |
17 | bool "Allwinner sunxi 64-bit SoC Family" | |
900a9020 | 18 | select ARCH_HAS_RESET_CONTROLLER |
23485482 | 19 | select GENERIC_IRQ_CHIP |
d229d205 | 20 | select PINCTRL |
900a9020 | 21 | select RESET_CONTROLLER |
ce3dd55b AP |
22 | help |
23 | This enables support for Allwinner sunxi based SoCs like the A64. | |
24 | ||
e2f0abaf AT |
25 | config ARCH_ALPINE |
26 | bool "Annapurna Labs Alpine platform" | |
5a3f75a4 | 27 | select ALPINE_MSI if PCI |
e2f0abaf AT |
28 | help |
29 | This enables support for the Annapurna Labs Alpine | |
30 | Soc family. | |
31 | ||
628d30d1 EA |
32 | config ARCH_BCM2835 |
33 | bool "Broadcom BCM2835 family" | |
bb0eb050 | 34 | select TIMER_OF |
da9a1c67 | 35 | select GPIOLIB |
7a9b6be9 | 36 | select MFD_CORE |
628d30d1 EA |
37 | select PINCTRL |
38 | select PINCTRL_BCM2835 | |
39 | select ARM_AMBA | |
40 | select ARM_TIMER_SP804 | |
41 | select HAVE_ARM_ARCH_TIMER | |
42 | help | |
43 | This enables support for the Broadcom BCM2837 SoC. | |
44 | This SoC is used in the Raspberry Pi 3 device. | |
45 | ||
36b7c583 RJ |
46 | config ARCH_BCM_IPROC |
47 | bool "Broadcom iProc SoC Family" | |
382618bb | 48 | select COMMON_CLK_IPROC |
da9a1c67 | 49 | select GPIOLIB |
382618bb | 50 | select PINCTRL |
36b7c583 RJ |
51 | help |
52 | This enables support for Broadcom iProc based SoCs | |
53 | ||
dd40fd92 JZ |
54 | config ARCH_BERLIN |
55 | bool "Marvell Berlin SoC Family" | |
56 | select DW_APB_ICTL | |
da9a1c67 | 57 | select GPIOLIB |
75d8e1ba | 58 | select PINCTRL |
dd40fd92 JZ |
59 | help |
60 | This enables support for Marvell Berlin SoC Family | |
61 | ||
ea367d38 MS |
62 | config ARCH_BITMAIN |
63 | bool "Bitmain SoC Platforms" | |
64 | help | |
65 | This enables support for the Bitmain SoC Family. | |
66 | ||
37eb56dc FF |
67 | config ARCH_BRCMSTB |
68 | bool "Broadcom Set-Top-Box SoCs" | |
809eec69 | 69 | select ARCH_HAS_RESET_CONTROLLER |
bf0349df | 70 | select BCM7038_L1_IRQ |
37eb56dc FF |
71 | select BRCMSTB_L2_IRQ |
72 | select GENERIC_IRQ_CHIP | |
724cf0ae | 73 | select PINCTRL |
37eb56dc FF |
74 | help |
75 | This enables support for Broadcom's ARMv8 Set Top Box SoCs | |
76 | ||
eed6b3eb | 77 | config ARCH_EXYNOS |
c87b3e97 | 78 | bool "ARMv8 based Samsung Exynos SoC family" |
eed6b3eb | 79 | select COMMON_CLK_SAMSUNG |
caab3df9 KK |
80 | select EXYNOS_PM_DOMAINS if PM_GENERIC_DOMAINS |
81 | select EXYNOS_PMU | |
eed6b3eb OJ |
82 | select HAVE_S3C2410_WATCHDOG if WATCHDOG |
83 | select HAVE_S3C_RTC if RTC_CLASS | |
84 | select PINCTRL | |
85 | select PINCTRL_EXYNOS | |
5220a73a | 86 | select PM_GENERIC_DOMAINS if PM |
3b3428e3 | 87 | select SOC_SAMSUNG |
eed6b3eb | 88 | help |
c87b3e97 | 89 | This enables support for ARMv8 based Samsung Exynos SoC family. |
eed6b3eb | 90 | |
c7724572 NM |
91 | config ARCH_K3 |
92 | bool "Texas Instruments Inc. K3 multicore SoC architecture" | |
93 | select PM_GENERIC_DOMAINS if PM | |
009669e7 | 94 | select MAILBOX |
a6b112b0 | 95 | select SOC_TI |
009669e7 LV |
96 | select TI_MESSAGE_MANAGER |
97 | select TI_SCI_PROTOCOL | |
98 | select TI_SCI_INTR_IRQCHIP | |
99 | select TI_SCI_INTA_IRQCHIP | |
c7724572 NM |
100 | help |
101 | This enables support for Texas Instruments' K3 multicore SoC | |
102 | architecture. | |
103 | ||
53a5fde0 BS |
104 | config ARCH_LAYERSCAPE |
105 | bool "ARMv8 based Freescale Layerscape SoC family" | |
eeb3d68b | 106 | select EDAC_SUPPORT |
eed6b3eb | 107 | help |
53a5fde0 | 108 | This enables support for the Freescale Layerscape SoC family. |
eed6b3eb | 109 | |
198ed962 CM |
110 | config ARCH_LG1K |
111 | bool "LG Electronics LG1K SoC Family" | |
112 | help | |
113 | This enables support for LG Electronics LG1K SoC Family | |
114 | ||
eed6b3eb OJ |
115 | config ARCH_HISI |
116 | bool "Hisilicon SoC Family" | |
2b905d3a | 117 | select ARM_TIMER_SP804 |
f9db43bc | 118 | select HISILICON_IRQ_MBIGEN if PCI |
21adc4d7 | 119 | select PINCTRL |
eed6b3eb OJ |
120 | help |
121 | This enables support for Hisilicon ARMv8 SoC family | |
122 | ||
123 | config ARCH_MEDIATEK | |
598f9b2e | 124 | bool "MediaTek SoC Family" |
eed6b3eb OJ |
125 | select ARM_GIC |
126 | select PINCTRL | |
c050b45d | 127 | select MTK_TIMER |
eed6b3eb | 128 | help |
598f9b2e SW |
129 | This enables support for MediaTek MT27xx, MT65xx, MT76xx |
130 | & MT81xx ARMv8 SoCs | |
eed6b3eb | 131 | |
451e9e54 AF |
132 | config ARCH_MESON |
133 | bool "Amlogic Platforms" | |
bf56c776 CC |
134 | select PINCTRL |
135 | select PINCTRL_MESON | |
59bdefe9 | 136 | select COMMON_CLK_GXBB |
78b4af31 | 137 | select COMMON_CLK_AXG |
b3077ffc | 138 | select COMMON_CLK_G12A |
f2c2122a | 139 | select MESON_IRQ_GPIO |
451e9e54 | 140 | help |
b3077ffc JB |
141 | This enables support for the arm64 based Amlogic SoCs |
142 | such as the s905, S905X/D, S912, A113X/D or S905X/D2 | |
451e9e54 | 143 | |
b4f596b1 GC |
144 | config ARCH_MVEBU |
145 | bool "Marvell EBU SoC Family" | |
ad87c0f6 TP |
146 | select ARMADA_AP806_SYSCON |
147 | select ARMADA_CP110_SYSCON | |
ff60d834 | 148 | select ARMADA_37XX_CLK |
d2718d13 GC |
149 | select GPIOLIB |
150 | select GPIOLIB_IRQCHIP | |
29ad6bd9 TP |
151 | select MVEBU_GICP |
152 | select MVEBU_ICU | |
b3920b2b | 153 | select MVEBU_ODMI |
04208a24 | 154 | select MVEBU_PIC |
228197c5 | 155 | select MVEBU_SEI |
d2718d13 GC |
156 | select OF_GPIO |
157 | select PINCTRL | |
158 | select PINCTRL_ARMADA_37XX | |
c4c14365 GC |
159 | select PINCTRL_ARMADA_AP806 |
160 | select PINCTRL_ARMADA_CP110 | |
b4f596b1 | 161 | help |
b3920b2b TP |
162 | This enables support for Marvell EBU familly, including: |
163 | - Armada 3700 SoC Family | |
164 | - Armada 7K SoC Family | |
165 | - Armada 8K SoC Family | |
b4f596b1 | 166 | |
930507c1 LS |
167 | config ARCH_MXC |
168 | bool "ARMv8 based NXP i.MX SoC family" | |
169 | select ARM64_ERRATUM_843419 | |
a29c7823 | 170 | select ARM64_ERRATUM_845719 if COMPAT |
67b92823 | 171 | select IMX_GPCV2 |
84a2ab25 LS |
172 | select IMX_GPCV2_PM_DOMAINS |
173 | select PM | |
174 | select PM_GENERIC_DOMAINS | |
fafaa0a2 | 175 | select SOC_BUS |
930507c1 LS |
176 | help |
177 | This enables support for the ARMv8 based SoCs in the | |
178 | NXP i.MX family. | |
179 | ||
eed6b3eb OJ |
180 | config ARCH_QCOM |
181 | bool "Qualcomm Platforms" | |
e19811a8 | 182 | select GPIOLIB |
eed6b3eb OJ |
183 | select PINCTRL |
184 | help | |
185 | This enables support for the ARMv8 based Qualcomm chipsets. | |
186 | ||
1b0d665e AF |
187 | config ARCH_REALTEK |
188 | bool "Realtek Platforms" | |
189 | help | |
190 | This enables support for the ARMv8 based Realtek chipsets, | |
191 | like the RTD1295. | |
192 | ||
26a7e06d SH |
193 | config ARCH_RENESAS |
194 | bool "Renesas SoC Platforms" | |
9374eee3 | 195 | select GPIOLIB |
26a7e06d | 196 | select PINCTRL |
8d6799a9 | 197 | select SOC_BUS |
26a7e06d SH |
198 | help |
199 | This enables support for the ARMv8 based Renesas SoCs. | |
200 | ||
0964d660 GU |
201 | config ARCH_ROCKCHIP |
202 | bool "Rockchip Platforms" | |
203 | select ARCH_HAS_RESET_CONTROLLER | |
204 | select GPIOLIB | |
205 | select PINCTRL | |
206 | select PINCTRL_ROCKCHIP | |
207 | select PM | |
208 | select ROCKCHIP_TIMER | |
209 | help | |
210 | This enables support for the ARMv8 based Rockchip chipsets, | |
211 | like the RK3368. | |
212 | ||
213 | config ARCH_SEATTLE | |
214 | bool "AMD Seattle SoC Family" | |
215 | help | |
216 | This enables support for AMD Seattle SOC Family | |
217 | ||
78cd6a9d DN |
218 | config ARCH_STRATIX10 |
219 | bool "Altera's Stratix 10 SoCFPGA Family" | |
220 | help | |
221 | This enables support for Altera's Stratix 10 SoCFPGA Family. | |
222 | ||
0964d660 GU |
223 | config ARCH_SYNQUACER |
224 | bool "Socionext SynQuacer SoC Family" | |
225 | ||
eed6b3eb OJ |
226 | config ARCH_TEGRA |
227 | bool "NVIDIA Tegra SoC Family" | |
228 | select ARCH_HAS_RESET_CONTROLLER | |
2e988a83 | 229 | select ARM_GIC_PM |
eed6b3eb OJ |
230 | select CLKDEV_LOOKUP |
231 | select CLKSRC_MMIO | |
bb0eb050 | 232 | select TIMER_OF |
eed6b3eb | 233 | select GENERIC_CLOCKEVENTS |
da9a1c67 | 234 | select GPIOLIB |
eed6b3eb | 235 | select PINCTRL |
98823241 JH |
236 | select PM |
237 | select PM_GENERIC_DOMAINS | |
eed6b3eb OJ |
238 | select RESET_CONTROLLER |
239 | help | |
240 | This enables support for the NVIDIA Tegra SoC family. | |
241 | ||
eed6b3eb OJ |
242 | config ARCH_SPRD |
243 | bool "Spreadtrum SoC platform" | |
244 | help | |
245 | Support for Spreadtrum ARM based SoCs | |
246 | ||
247 | config ARCH_THUNDER | |
248 | bool "Cavium Inc. Thunder SoC Family" | |
249 | help | |
250 | This enables support for Cavium's Thunder Family of SoCs. | |
251 | ||
03b6fd5d J |
252 | config ARCH_THUNDER2 |
253 | bool "Cavium ThunderX2 Server Processors" | |
254 | select GPIOLIB | |
255 | help | |
256 | This enables support for Cavium's ThunderX2 CN99XX family of | |
257 | server processors. | |
258 | ||
56aaafb6 MY |
259 | config ARCH_UNIPHIER |
260 | bool "Socionext UniPhier SoC Family" | |
75924903 | 261 | select ARCH_HAS_RESET_CONTROLLER |
56aaafb6 | 262 | select PINCTRL |
ab6ab445 | 263 | select RESET_CONTROLLER |
56aaafb6 MY |
264 | help |
265 | This enables support for Socionext UniPhier SoC family. | |
266 | ||
eed6b3eb OJ |
267 | config ARCH_VEXPRESS |
268 | bool "ARMv8 software model (Versatile Express)" | |
eed6b3eb | 269 | select COMMON_CLK_VERSATILE |
da9a1c67 | 270 | select GPIOLIB |
8da7cc08 SH |
271 | select PM |
272 | select PM_GENERIC_DOMAINS | |
eed6b3eb OJ |
273 | select POWER_RESET_VEXPRESS |
274 | select VEXPRESS_CONFIG | |
275 | help | |
276 | This enables support for the ARMv8 software model (Versatile | |
277 | Express). | |
278 | ||
5bfb3889 | 279 | config ARCH_VULCAN |
a314520d | 280 | def_bool n |
5bfb3889 | 281 | |
eed6b3eb OJ |
282 | config ARCH_XGENE |
283 | bool "AppliedMicro X-Gene SOC Family" | |
284 | help | |
285 | This enables support for AppliedMicro X-Gene SOC Family | |
286 | ||
12496aea JN |
287 | config ARCH_ZX |
288 | bool "ZTE ZX SoC Family" | |
03d95c26 | 289 | select PINCTRL |
12496aea JN |
290 | help |
291 | This enables support for ZTE ZX SoC Family | |
292 | ||
eed6b3eb OJ |
293 | config ARCH_ZYNQMP |
294 | bool "Xilinx ZynqMP Family" | |
76582671 | 295 | select ZYNQMP_FIRMWARE |
eed6b3eb OJ |
296 | help |
297 | This enables support for Xilinx ZynqMP Family | |
298 | ||
299 | endmenu |