Commit | Line | Data |
---|---|---|
ec8f24b7 | 1 | # SPDX-License-Identifier: GPL-2.0-only |
eed6b3eb OJ |
2 | menu "Platform selection" |
3 | ||
c88cc3ee AF |
4 | config ARCH_ACTIONS |
5 | bool "Actions Semi Platforms" | |
6 | select OWL_TIMER | |
e0c27a10 | 7 | select PINCTRL |
c88cc3ee AF |
8 | help |
9 | This enables support for the Actions Semiconductor S900 SoC family. | |
10 | ||
ce3dd55b AP |
11 | config ARCH_SUNXI |
12 | bool "Allwinner sunxi 64-bit SoC Family" | |
900a9020 | 13 | select ARCH_HAS_RESET_CONTROLLER |
d229d205 | 14 | select PINCTRL |
900a9020 | 15 | select RESET_CONTROLLER |
cbccad66 | 16 | select SUN4I_TIMER |
d421fd6d SH |
17 | select SUN6I_R_INTC |
18 | select SUNXI_NMI_INTC | |
ce3dd55b AP |
19 | help |
20 | This enables support for Allwinner sunxi based SoCs like the A64. | |
21 | ||
e2f0abaf AT |
22 | config ARCH_ALPINE |
23 | bool "Annapurna Labs Alpine platform" | |
5a3f75a4 | 24 | select ALPINE_MSI if PCI |
e2f0abaf AT |
25 | help |
26 | This enables support for the Annapurna Labs Alpine | |
27 | Soc family. | |
28 | ||
aea5f69f HM |
29 | config ARCH_APPLE |
30 | bool "Apple Silicon SoC family" | |
31 | select APPLE_AIC | |
32 | help | |
33 | This enables support for Apple's in-house ARM SoC family, starting | |
34 | with the Apple M1. | |
35 | ||
96796c91 FF |
36 | menuconfig ARCH_BCM |
37 | bool "Broadcom SoC Support" | |
38 | ||
39 | if ARCH_BCM | |
40 | ||
628d30d1 EA |
41 | config ARCH_BCM2835 |
42 | bool "Broadcom BCM2835 family" | |
bb0eb050 | 43 | select TIMER_OF |
da9a1c67 | 44 | select GPIOLIB |
7a9b6be9 | 45 | select MFD_CORE |
628d30d1 EA |
46 | select PINCTRL |
47 | select PINCTRL_BCM2835 | |
48 | select ARM_AMBA | |
781fa0a9 | 49 | select ARM_GIC |
628d30d1 | 50 | select ARM_TIMER_SP804 |
628d30d1 | 51 | help |
781fa0a9 SW |
52 | This enables support for the Broadcom BCM2837 and BCM2711 SoC. |
53 | These SoCs are used in the Raspberry Pi 3 and 4 devices. | |
628d30d1 | 54 | |
36b7c583 RJ |
55 | config ARCH_BCM_IPROC |
56 | bool "Broadcom iProc SoC Family" | |
382618bb | 57 | select COMMON_CLK_IPROC |
da9a1c67 | 58 | select GPIOLIB |
382618bb | 59 | select PINCTRL |
36b7c583 RJ |
60 | help |
61 | This enables support for Broadcom iProc based SoCs | |
62 | ||
fdcd652c | 63 | config ARCH_BCMBCA |
746ef3ac | 64 | bool "Broadcom Broadband Carrier Access (BCA) origin SoC" |
dd5c672d | 65 | select GPIOLIB |
fdcd652c WZ |
66 | help |
67 | Say Y if you intend to run the kernel on a Broadcom Broadband ARM-based | |
68 | BCA chipset. | |
69 | ||
70 | This enables support for Broadcom BCA ARM-based broadband chipsets, | |
71 | including the DSL, PON and Wireless family of chips. | |
72 | ||
96796c91 FF |
73 | config ARCH_BRCMSTB |
74 | bool "Broadcom Set-Top-Box SoCs" | |
75 | select ARCH_HAS_RESET_CONTROLLER | |
76 | select GENERIC_IRQ_CHIP | |
77 | select PINCTRL | |
78 | help | |
79 | This enables support for Broadcom's ARMv8 Set Top Box SoCs | |
80 | ||
81 | endif | |
82 | ||
dd40fd92 JZ |
83 | config ARCH_BERLIN |
84 | bool "Marvell Berlin SoC Family" | |
85 | select DW_APB_ICTL | |
b0fc70ce | 86 | select DW_APB_TIMER_OF |
da9a1c67 | 87 | select GPIOLIB |
75d8e1ba | 88 | select PINCTRL |
dd40fd92 JZ |
89 | help |
90 | This enables support for Marvell Berlin SoC Family | |
91 | ||
ea367d38 MS |
92 | config ARCH_BITMAIN |
93 | bool "Bitmain SoC Platforms" | |
94 | help | |
95 | This enables support for the Bitmain SoC Family. | |
96 | ||
eed6b3eb | 97 | config ARCH_EXYNOS |
69d8a5f8 | 98 | bool "Samsung Exynos SoC family" |
eed6b3eb | 99 | select COMMON_CLK_SAMSUNG |
ce96a964 | 100 | select CLKSRC_EXYNOS_MCT |
caab3df9 KK |
101 | select EXYNOS_PM_DOMAINS if PM_GENERIC_DOMAINS |
102 | select EXYNOS_PMU | |
eed6b3eb OJ |
103 | select PINCTRL |
104 | select PINCTRL_EXYNOS | |
5220a73a | 105 | select PM_GENERIC_DOMAINS if PM |
3b3428e3 | 106 | select SOC_SAMSUNG |
eed6b3eb | 107 | help |
c87b3e97 | 108 | This enables support for ARMv8 based Samsung Exynos SoC family. |
eed6b3eb | 109 | |
31a91c87 | 110 | config ARCH_SPARX5 |
69d8a5f8 | 111 | bool "Microchip Sparx5 SoC family" |
31a91c87 LP |
112 | select PINCTRL |
113 | select DW_APB_TIMER_OF | |
114 | help | |
115 | This enables support for the Microchip Sparx5 ARMv8-based | |
116 | SoC family of TSN-capable gigabit switches. | |
117 | ||
118 | The SparX-5 Ethernet switch family provides a rich set of | |
119 | switching features such as advanced TCAM-based VLAN and QoS | |
120 | processing enabling delivery of differentiated services, and | |
121 | security through TCAM-based frame processing using versatile | |
122 | content aware processor (VCAP). | |
123 | ||
c7724572 NM |
124 | config ARCH_K3 |
125 | bool "Texas Instruments Inc. K3 multicore SoC architecture" | |
126 | select PM_GENERIC_DOMAINS if PM | |
009669e7 | 127 | select MAILBOX |
a6b112b0 | 128 | select SOC_TI |
009669e7 LV |
129 | select TI_MESSAGE_MANAGER |
130 | select TI_SCI_PROTOCOL | |
131 | select TI_SCI_INTR_IRQCHIP | |
132 | select TI_SCI_INTA_IRQCHIP | |
ec792ecf | 133 | select TI_K3_SOCINFO |
c7724572 NM |
134 | help |
135 | This enables support for Texas Instruments' K3 multicore SoC | |
136 | architecture. | |
137 | ||
198ed962 CM |
138 | config ARCH_LG1K |
139 | bool "LG Electronics LG1K SoC Family" | |
140 | help | |
141 | This enables support for LG Electronics LG1K SoC Family | |
142 | ||
eed6b3eb OJ |
143 | config ARCH_HISI |
144 | bool "Hisilicon SoC Family" | |
2b905d3a | 145 | select ARM_TIMER_SP804 |
f9db43bc | 146 | select HISILICON_IRQ_MBIGEN if PCI |
21adc4d7 | 147 | select PINCTRL |
eed6b3eb OJ |
148 | help |
149 | This enables support for Hisilicon ARMv8 SoC family | |
150 | ||
a6a4abf8 DA |
151 | config ARCH_KEEMBAY |
152 | bool "Keem Bay SoC" | |
153 | help | |
154 | This enables support for Intel Movidius SoC code-named Keem Bay. | |
155 | ||
eed6b3eb | 156 | config ARCH_MEDIATEK |
598f9b2e | 157 | bool "MediaTek SoC Family" |
eed6b3eb OJ |
158 | select ARM_GIC |
159 | select PINCTRL | |
c050b45d | 160 | select MTK_TIMER |
eed6b3eb | 161 | help |
598f9b2e SW |
162 | This enables support for MediaTek MT27xx, MT65xx, MT76xx |
163 | & MT81xx ARMv8 SoCs | |
eed6b3eb | 164 | |
451e9e54 AF |
165 | config ARCH_MESON |
166 | bool "Amlogic Platforms" | |
167 | help | |
b3077ffc JB |
168 | This enables support for the arm64 based Amlogic SoCs |
169 | such as the s905, S905X/D, S912, A113X/D or S905X/D2 | |
451e9e54 | 170 | |
b4f596b1 GC |
171 | config ARCH_MVEBU |
172 | bool "Marvell EBU SoC Family" | |
ad87c0f6 TP |
173 | select ARMADA_AP806_SYSCON |
174 | select ARMADA_CP110_SYSCON | |
ff60d834 | 175 | select ARMADA_37XX_CLK |
d2718d13 GC |
176 | select GPIOLIB |
177 | select GPIOLIB_IRQCHIP | |
29ad6bd9 TP |
178 | select MVEBU_GICP |
179 | select MVEBU_ICU | |
b3920b2b | 180 | select MVEBU_ODMI |
04208a24 | 181 | select MVEBU_PIC |
228197c5 | 182 | select MVEBU_SEI |
d2718d13 GC |
183 | select OF_GPIO |
184 | select PINCTRL | |
185 | select PINCTRL_ARMADA_37XX | |
c4c14365 GC |
186 | select PINCTRL_ARMADA_AP806 |
187 | select PINCTRL_ARMADA_CP110 | |
8225663e | 188 | select PINCTRL_AC5 |
b4f596b1 | 189 | help |
11fc944f | 190 | This enables support for Marvell EBU family, including: |
b3920b2b TP |
191 | - Armada 3700 SoC Family |
192 | - Armada 7K SoC Family | |
193 | - Armada 8K SoC Family | |
8225663e | 194 | - 98DX2530 SoC Family |
b4f596b1 | 195 | |
566e373f FF |
196 | menuconfig ARCH_NXP |
197 | bool "NXP SoC support" | |
198 | ||
199 | if ARCH_NXP | |
200 | ||
201 | config ARCH_LAYERSCAPE | |
69d8a5f8 | 202 | bool "Freescale Layerscape SoC family" |
566e373f FF |
203 | select EDAC_SUPPORT |
204 | help | |
205 | This enables support for the Freescale Layerscape SoC family. | |
206 | ||
930507c1 | 207 | config ARCH_MXC |
69d8a5f8 | 208 | bool "NXP i.MX SoC family" |
930507c1 | 209 | select ARM64_ERRATUM_843419 |
a29c7823 | 210 | select ARM64_ERRATUM_845719 if COMPAT |
67b92823 | 211 | select IMX_GPCV2 |
84a2ab25 LS |
212 | select IMX_GPCV2_PM_DOMAINS |
213 | select PM | |
214 | select PM_GENERIC_DOMAINS | |
fafaa0a2 | 215 | select SOC_BUS |
1991529f | 216 | select TIMER_IMX_SYS_CTR |
930507c1 LS |
217 | help |
218 | This enables support for the ARMv8 based SoCs in the | |
219 | NXP i.MX family. | |
220 | ||
566e373f FF |
221 | config ARCH_S32 |
222 | bool "NXP S32 SoC Family" | |
223 | help | |
224 | This enables support for the NXP S32 family of processors. | |
225 | ||
226 | endif | |
227 | ||
64b88e9f JH |
228 | config ARCH_MA35 |
229 | bool "Nuvoton MA35 Architecture" | |
230 | select GPIOLIB | |
231 | select PINCTRL | |
232 | select RESET_CONTROLLER | |
233 | help | |
234 | This enables support for the ARMv8 based Nuvoton MA35 series SoCs. | |
235 | ||
3670d2ec TM |
236 | config ARCH_NPCM |
237 | bool "Nuvoton NPCM Architecture" | |
238 | select PINCTRL | |
239 | select GPIOLIB | |
240 | select NPCM7XX_TIMER | |
241 | select RESET_CONTROLLER | |
242 | select MFD_SYSCON | |
243 | help | |
244 | General support for NPCM8xx BMC (Arbel). | |
245 | Nuvoton NPCM8xx BMC based on the Cortex A35. | |
246 | ||
646fe2e4 BL |
247 | config ARCH_PENSANDO |
248 | bool "AMD Pensando Platforms" | |
249 | help | |
250 | This enables support for the ARMv8 based AMD Pensando SoC | |
251 | family to include the Elba SoC. | |
252 | ||
253 | AMD Pensando SoCs support a range of Distributed Services | |
254 | Cards in PCIe format installed into servers. The Elba | |
255 | SoC includes 16 Cortex A-72 CPU cores, 144 P4-programmable | |
256 | cores for a minimal latency/jitter datapath, and network | |
257 | interfaces up to 200 Gb/s. | |
258 | ||
eed6b3eb OJ |
259 | config ARCH_QCOM |
260 | bool "Qualcomm Platforms" | |
e19811a8 | 261 | select GPIOLIB |
eed6b3eb OJ |
262 | select PINCTRL |
263 | help | |
264 | This enables support for the ARMv8 based Qualcomm chipsets. | |
265 | ||
1b0d665e AF |
266 | config ARCH_REALTEK |
267 | bool "Realtek Platforms" | |
e3ca9556 | 268 | select RESET_CONTROLLER |
1b0d665e AF |
269 | help |
270 | This enables support for the ARMv8 based Realtek chipsets, | |
271 | like the RTD1295. | |
272 | ||
26a7e06d SH |
273 | config ARCH_RENESAS |
274 | bool "Renesas SoC Platforms" | |
26a7e06d SH |
275 | help |
276 | This enables support for the ARMv8 based Renesas SoCs. | |
277 | ||
0964d660 GU |
278 | config ARCH_ROCKCHIP |
279 | bool "Rockchip Platforms" | |
280 | select ARCH_HAS_RESET_CONTROLLER | |
0964d660 | 281 | select PINCTRL |
0964d660 GU |
282 | select PM |
283 | select ROCKCHIP_TIMER | |
284 | help | |
285 | This enables support for the ARMv8 based Rockchip chipsets, | |
286 | like the RK3368. | |
287 | ||
288 | config ARCH_SEATTLE | |
289 | bool "AMD Seattle SoC Family" | |
290 | help | |
291 | This enables support for AMD Seattle SOC Family | |
292 | ||
910499e1 | 293 | config ARCH_INTEL_SOCFPGA |
4a9a1a56 KK |
294 | bool "Intel's SoCFPGA ARMv8 Families" |
295 | help | |
296 | This enables support for Intel's SoCFPGA ARMv8 families: | |
2b59af8c TWP |
297 | Stratix 10 (ex. Altera), Stratix10 Software Virtual Platform, |
298 | Agilex and eASIC N5X. | |
910499e1 | 299 | |
9e4e2441 AT |
300 | config ARCH_STM32 |
301 | bool "STMicroelectronics STM32 SoC Family" | |
302 | select GPIOLIB | |
303 | select PINCTRL | |
304 | select PINCTRL_STM32MP257 | |
305 | select ARM_SMC_MBOX | |
306 | select ARM_SCMI_PROTOCOL | |
307 | select COMMON_CLK_SCMI | |
308 | help | |
309 | This enables support for ARMv8 based STMicroelectronics | |
310 | STM32 family, including: | |
311 | - STM32MP25: | |
312 | - STM32MP251, STM32MP253, STM32MP255 and STM32MP257. | |
313 | ||
0964d660 GU |
314 | config ARCH_SYNQUACER |
315 | bool "Socionext SynQuacer SoC Family" | |
4efc851c | 316 | select IRQ_FASTEOI_HIERARCHY_HANDLERS |
0964d660 | 317 | |
eed6b3eb OJ |
318 | config ARCH_TEGRA |
319 | bool "NVIDIA Tegra SoC Family" | |
320 | select ARCH_HAS_RESET_CONTROLLER | |
2e988a83 | 321 | select ARM_GIC_PM |
eed6b3eb | 322 | select CLKSRC_MMIO |
bb0eb050 | 323 | select TIMER_OF |
da9a1c67 | 324 | select GPIOLIB |
eed6b3eb | 325 | select PINCTRL |
98823241 JH |
326 | select PM |
327 | select PM_GENERIC_DOMAINS | |
eed6b3eb OJ |
328 | select RESET_CONTROLLER |
329 | help | |
330 | This enables support for the NVIDIA Tegra SoC family. | |
331 | ||
18b1db6a | 332 | config ARCH_TESLA_FSD |
69d8a5f8 | 333 | bool "Tesla platform" |
18b1db6a AA |
334 | depends on ARCH_EXYNOS |
335 | help | |
336 | Support for ARMv8 based Tesla platforms. | |
337 | ||
eed6b3eb | 338 | config ARCH_SPRD |
b5f73d47 | 339 | bool "Spreadtrum SoC platform" |
eed6b3eb OJ |
340 | help |
341 | Support for Spreadtrum ARM based SoCs | |
342 | ||
343 | config ARCH_THUNDER | |
344 | bool "Cavium Inc. Thunder SoC Family" | |
345 | help | |
346 | This enables support for Cavium's Thunder Family of SoCs. | |
347 | ||
03b6fd5d J |
348 | config ARCH_THUNDER2 |
349 | bool "Cavium ThunderX2 Server Processors" | |
350 | select GPIOLIB | |
351 | help | |
352 | This enables support for Cavium's ThunderX2 CN99XX family of | |
353 | server processors. | |
354 | ||
56aaafb6 MY |
355 | config ARCH_UNIPHIER |
356 | bool "Socionext UniPhier SoC Family" | |
75924903 | 357 | select ARCH_HAS_RESET_CONTROLLER |
56aaafb6 | 358 | select PINCTRL |
ab6ab445 | 359 | select RESET_CONTROLLER |
56aaafb6 MY |
360 | help |
361 | This enables support for Socionext UniPhier SoC family. | |
362 | ||
eed6b3eb OJ |
363 | config ARCH_VEXPRESS |
364 | bool "ARMv8 software model (Versatile Express)" | |
da9a1c67 | 365 | select GPIOLIB |
8da7cc08 SH |
366 | select PM |
367 | select PM_GENERIC_DOMAINS | |
eed6b3eb OJ |
368 | help |
369 | This enables support for the ARMv8 software model (Versatile | |
370 | Express). | |
371 | ||
0aa56c7e NI |
372 | config ARCH_VISCONTI |
373 | bool "Toshiba Visconti SoC Family" | |
374 | select PINCTRL | |
375 | select PINCTRL_VISCONTI | |
376 | help | |
377 | This enables support for Toshiba Visconti SoCs Family. | |
378 | ||
eed6b3eb OJ |
379 | config ARCH_XGENE |
380 | bool "AppliedMicro X-Gene SOC Family" | |
381 | help | |
382 | This enables support for AppliedMicro X-Gene SOC Family | |
383 | ||
384 | config ARCH_ZYNQMP | |
385 | bool "Xilinx ZynqMP Family" | |
386 | help | |
387 | This enables support for Xilinx ZynqMP Family | |
388 | ||
aea3cb35 | 389 | endmenu # "Platform selection" |