Commit | Line | Data |
---|---|---|
8c2c3df3 CM |
1 | config ARM64 |
2 | def_bool y | |
b6197b93 | 3 | select ACPI_CCA_REQUIRED if ACPI |
d8f4f161 | 4 | select ACPI_GENERIC_GSI if ACPI |
6933de0c | 5 | select ACPI_REDUCED_HARDWARE_ONLY if ACPI |
21266be9 | 6 | select ARCH_HAS_DEVMEM_IS_ALLOWED |
8c2c3df3 | 7 | select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE |
2b68f6ca | 8 | select ARCH_HAS_ELF_RANDOMIZE |
957e3fac | 9 | select ARCH_HAS_GCOV_PROFILE_ALL |
308c09f1 | 10 | select ARCH_HAS_SG_CHAIN |
1f85008e | 11 | select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST |
c63c8700 | 12 | select ARCH_USE_CMPXCHG_LOCKREF |
4badad35 | 13 | select ARCH_SUPPORTS_ATOMIC_RMW |
56166230 | 14 | select ARCH_SUPPORTS_NUMA_BALANCING |
9170100e | 15 | select ARCH_WANT_OPTIONAL_GPIOLIB |
6212a512 | 16 | select ARCH_WANT_COMPAT_IPC_PARSE_VERSION |
b6f35981 | 17 | select ARCH_WANT_FRAME_POINTERS |
f0b7f8a4 | 18 | select ARCH_HAS_UBSAN_SANITIZE_ALL |
25c92a37 | 19 | select ARM_AMBA |
1aee5d7a | 20 | select ARM_ARCH_TIMER |
c4188edc | 21 | select ARM_GIC |
875cbf3e | 22 | select AUDIT_ARCH_COMPAT_GENERIC |
853a33ce | 23 | select ARM_GIC_V2M if PCI_MSI |
021f6537 | 24 | select ARM_GIC_V3 |
19812729 | 25 | select ARM_GIC_V3_ITS if PCI_MSI |
bff60792 | 26 | select ARM_PSCI_FW |
adace895 | 27 | select BUILDTIME_EXTABLE_SORT |
db2789b5 | 28 | select CLONE_BACKWARDS |
7ca2ef33 | 29 | select COMMON_CLK |
166936ba | 30 | select CPU_PM if (SUSPEND || CPU_IDLE) |
7bc13fd3 | 31 | select DCACHE_WORD_ACCESS |
ef37566c | 32 | select EDAC_SUPPORT |
2f34f173 | 33 | select FRAME_POINTER |
d4932f9e | 34 | select GENERIC_ALLOCATOR |
8c2c3df3 | 35 | select GENERIC_CLOCKEVENTS |
4b3dc967 | 36 | select GENERIC_CLOCKEVENTS_BROADCAST |
3be1a5c4 | 37 | select GENERIC_CPU_AUTOPROBE |
bf4b558e | 38 | select GENERIC_EARLY_IOREMAP |
2314ee4d | 39 | select GENERIC_IDLE_POLL_SETUP |
8c2c3df3 CM |
40 | select GENERIC_IRQ_PROBE |
41 | select GENERIC_IRQ_SHOW | |
6544e67b | 42 | select GENERIC_IRQ_SHOW_LEVEL |
cb61f676 | 43 | select GENERIC_PCI_IOMAP |
65cd4f6c | 44 | select GENERIC_SCHED_CLOCK |
8c2c3df3 | 45 | select GENERIC_SMP_IDLE_THREAD |
12a0ef7b WD |
46 | select GENERIC_STRNCPY_FROM_USER |
47 | select GENERIC_STRNLEN_USER | |
8c2c3df3 | 48 | select GENERIC_TIME_VSYSCALL |
a1ddc74a | 49 | select HANDLE_DOMAIN_IRQ |
8c2c3df3 | 50 | select HARDIRQS_SW_RESEND |
5284e1b4 | 51 | select HAVE_ALIGNED_STRUCT_PAGE if SLUB |
875cbf3e | 52 | select HAVE_ARCH_AUDITSYSCALL |
8e7a4cef | 53 | select HAVE_ARCH_BITREVERSE |
324420bf | 54 | select HAVE_ARCH_HUGE_VMAP |
9732cafd | 55 | select HAVE_ARCH_JUMP_LABEL |
f1b9032f | 56 | select HAVE_ARCH_KASAN if SPARSEMEM_VMEMMAP && !(ARM64_16K_PAGES && ARM64_VA_BITS_48) |
9529247d | 57 | select HAVE_ARCH_KGDB |
8f0d3aa9 DC |
58 | select HAVE_ARCH_MMAP_RND_BITS |
59 | select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT | |
a1ae65b2 | 60 | select HAVE_ARCH_SECCOMP_FILTER |
8c2c3df3 | 61 | select HAVE_ARCH_TRACEHOOK |
8ee70879 YS |
62 | select HAVE_ARCH_TRANSPARENT_HUGEPAGE |
63 | select HAVE_ARM_SMCCC | |
6077776b | 64 | select HAVE_EBPF_JIT |
af64d2aa | 65 | select HAVE_C_RECORDMCOUNT |
c0c264ae | 66 | select HAVE_CC_STACKPROTECTOR |
5284e1b4 | 67 | select HAVE_CMPXCHG_DOUBLE |
95eff6b2 | 68 | select HAVE_CMPXCHG_LOCAL |
8ee70879 | 69 | select HAVE_CONTEXT_TRACKING |
9b2a60c4 | 70 | select HAVE_DEBUG_BUGVERBOSE |
b69ec42b | 71 | select HAVE_DEBUG_KMEMLEAK |
8c2c3df3 | 72 | select HAVE_DMA_API_DEBUG |
6ac2104d | 73 | select HAVE_DMA_CONTIGUOUS |
bd7d38db | 74 | select HAVE_DYNAMIC_FTRACE |
50afc33a | 75 | select HAVE_EFFICIENT_UNALIGNED_ACCESS |
af64d2aa | 76 | select HAVE_FTRACE_MCOUNT_RECORD |
819e50e2 AT |
77 | select HAVE_FUNCTION_TRACER |
78 | select HAVE_FUNCTION_GRAPH_TRACER | |
8c2c3df3 | 79 | select HAVE_GENERIC_DMA_COHERENT |
8c2c3df3 | 80 | select HAVE_HW_BREAKPOINT if PERF_EVENTS |
24da208d | 81 | select HAVE_IRQ_TIME_ACCOUNTING |
8c2c3df3 | 82 | select HAVE_MEMBLOCK |
1a2db300 | 83 | select HAVE_MEMBLOCK_NODE_MAP if NUMA |
55834a77 | 84 | select HAVE_PATA_PLATFORM |
8c2c3df3 | 85 | select HAVE_PERF_EVENTS |
2ee0d7fd JP |
86 | select HAVE_PERF_REGS |
87 | select HAVE_PERF_USER_STACK_DUMP | |
5e5f6dc1 | 88 | select HAVE_RCU_TABLE_FREE |
055b1212 | 89 | select HAVE_SYSCALL_TRACEPOINTS |
876945db | 90 | select IOMMU_DMA if IOMMU_SUPPORT |
8c2c3df3 | 91 | select IRQ_DOMAIN |
e8557d1f | 92 | select IRQ_FORCED_THREADING |
fea2acaa | 93 | select MODULES_USE_ELF_RELA |
8c2c3df3 CM |
94 | select NO_BOOTMEM |
95 | select OF | |
96 | select OF_EARLY_FLATTREE | |
8ee70879 | 97 | select OF_NUMA if NUMA && OF |
9bf14b7c | 98 | select OF_RESERVED_MEM |
8c2c3df3 | 99 | select PERF_USE_VMALLOC |
aa1e8ec1 CM |
100 | select POWER_RESET |
101 | select POWER_SUPPLY | |
8c2c3df3 | 102 | select SPARSE_IRQ |
7ac57a89 | 103 | select SYSCTL_EXCEPTION_TRACE |
8c2c3df3 CM |
104 | help |
105 | ARM 64-bit (AArch64) Linux support. | |
106 | ||
107 | config 64BIT | |
108 | def_bool y | |
109 | ||
110 | config ARCH_PHYS_ADDR_T_64BIT | |
111 | def_bool y | |
112 | ||
113 | config MMU | |
114 | def_bool y | |
115 | ||
8f0d3aa9 DC |
116 | config ARCH_MMAP_RND_BITS_MIN |
117 | default 14 if ARM64_64K_PAGES | |
118 | default 16 if ARM64_16K_PAGES | |
119 | default 18 | |
120 | ||
121 | # max bits determined by the following formula: | |
122 | # VA_BITS - PAGE_SHIFT - 3 | |
123 | config ARCH_MMAP_RND_BITS_MAX | |
124 | default 19 if ARM64_VA_BITS=36 | |
125 | default 24 if ARM64_VA_BITS=39 | |
126 | default 27 if ARM64_VA_BITS=42 | |
127 | default 30 if ARM64_VA_BITS=47 | |
128 | default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES | |
129 | default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES | |
130 | default 33 if ARM64_VA_BITS=48 | |
131 | default 14 if ARM64_64K_PAGES | |
132 | default 16 if ARM64_16K_PAGES | |
133 | default 18 | |
134 | ||
135 | config ARCH_MMAP_RND_COMPAT_BITS_MIN | |
136 | default 7 if ARM64_64K_PAGES | |
137 | default 9 if ARM64_16K_PAGES | |
138 | default 11 | |
139 | ||
140 | config ARCH_MMAP_RND_COMPAT_BITS_MAX | |
141 | default 16 | |
142 | ||
ce816fa8 | 143 | config NO_IOPORT_MAP |
d1e6dc91 | 144 | def_bool y if !PCI |
8c2c3df3 CM |
145 | |
146 | config STACKTRACE_SUPPORT | |
147 | def_bool y | |
148 | ||
bf0c4e04 JVS |
149 | config ILLEGAL_POINTER_VALUE |
150 | hex | |
151 | default 0xdead000000000000 | |
152 | ||
8c2c3df3 CM |
153 | config LOCKDEP_SUPPORT |
154 | def_bool y | |
155 | ||
156 | config TRACE_IRQFLAGS_SUPPORT | |
157 | def_bool y | |
158 | ||
c209f799 | 159 | config RWSEM_XCHGADD_ALGORITHM |
8c2c3df3 CM |
160 | def_bool y |
161 | ||
9fb7410f DM |
162 | config GENERIC_BUG |
163 | def_bool y | |
164 | depends on BUG | |
165 | ||
166 | config GENERIC_BUG_RELATIVE_POINTERS | |
167 | def_bool y | |
168 | depends on GENERIC_BUG | |
169 | ||
8c2c3df3 CM |
170 | config GENERIC_HWEIGHT |
171 | def_bool y | |
172 | ||
173 | config GENERIC_CSUM | |
174 | def_bool y | |
175 | ||
176 | config GENERIC_CALIBRATE_DELAY | |
177 | def_bool y | |
178 | ||
19e7640d | 179 | config ZONE_DMA |
8c2c3df3 CM |
180 | def_bool y |
181 | ||
29e56940 SC |
182 | config HAVE_GENERIC_RCU_GUP |
183 | def_bool y | |
184 | ||
8c2c3df3 CM |
185 | config ARCH_DMA_ADDR_T_64BIT |
186 | def_bool y | |
187 | ||
188 | config NEED_DMA_MAP_STATE | |
189 | def_bool y | |
190 | ||
191 | config NEED_SG_DMA_LENGTH | |
192 | def_bool y | |
193 | ||
4b3dc967 WD |
194 | config SMP |
195 | def_bool y | |
196 | ||
8c2c3df3 CM |
197 | config SWIOTLB |
198 | def_bool y | |
199 | ||
200 | config IOMMU_HELPER | |
201 | def_bool SWIOTLB | |
202 | ||
4cfb3613 AB |
203 | config KERNEL_MODE_NEON |
204 | def_bool y | |
205 | ||
92cc15fc RH |
206 | config FIX_EARLYCON_MEM |
207 | def_bool y | |
208 | ||
9f25e6ad KS |
209 | config PGTABLE_LEVELS |
210 | int | |
21539939 | 211 | default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36 |
9f25e6ad KS |
212 | default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42 |
213 | default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48 | |
214 | default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39 | |
44eaacf1 SP |
215 | default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47 |
216 | default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48 | |
9f25e6ad | 217 | |
8c2c3df3 CM |
218 | source "init/Kconfig" |
219 | ||
220 | source "kernel/Kconfig.freezer" | |
221 | ||
6a377491 | 222 | source "arch/arm64/Kconfig.platforms" |
8c2c3df3 CM |
223 | |
224 | menu "Bus support" | |
225 | ||
d1e6dc91 LD |
226 | config PCI |
227 | bool "PCI support" | |
228 | help | |
229 | This feature enables support for PCI bus system. If you say Y | |
230 | here, the kernel will include drivers and infrastructure code | |
231 | to support PCI bus devices. | |
232 | ||
233 | config PCI_DOMAINS | |
234 | def_bool PCI | |
235 | ||
236 | config PCI_DOMAINS_GENERIC | |
237 | def_bool PCI | |
238 | ||
239 | config PCI_SYSCALL | |
240 | def_bool PCI | |
241 | ||
242 | source "drivers/pci/Kconfig" | |
d1e6dc91 | 243 | |
8c2c3df3 CM |
244 | endmenu |
245 | ||
246 | menu "Kernel Features" | |
247 | ||
c0a01b84 AP |
248 | menu "ARM errata workarounds via the alternatives framework" |
249 | ||
250 | config ARM64_ERRATUM_826319 | |
251 | bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted" | |
252 | default y | |
253 | help | |
254 | This option adds an alternative code sequence to work around ARM | |
255 | erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or | |
256 | AXI master interface and an L2 cache. | |
257 | ||
258 | If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors | |
259 | and is unable to accept a certain write via this interface, it will | |
260 | not progress on read data presented on the read data channel and the | |
261 | system can deadlock. | |
262 | ||
263 | The workaround promotes data cache clean instructions to | |
264 | data cache clean-and-invalidate. | |
265 | Please note that this does not necessarily enable the workaround, | |
266 | as it depends on the alternative framework, which will only patch | |
267 | the kernel if an affected CPU is detected. | |
268 | ||
269 | If unsure, say Y. | |
270 | ||
271 | config ARM64_ERRATUM_827319 | |
272 | bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect" | |
273 | default y | |
274 | help | |
275 | This option adds an alternative code sequence to work around ARM | |
276 | erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI | |
277 | master interface and an L2 cache. | |
278 | ||
279 | Under certain conditions this erratum can cause a clean line eviction | |
280 | to occur at the same time as another transaction to the same address | |
281 | on the AMBA 5 CHI interface, which can cause data corruption if the | |
282 | interconnect reorders the two transactions. | |
283 | ||
284 | The workaround promotes data cache clean instructions to | |
285 | data cache clean-and-invalidate. | |
286 | Please note that this does not necessarily enable the workaround, | |
287 | as it depends on the alternative framework, which will only patch | |
288 | the kernel if an affected CPU is detected. | |
289 | ||
290 | If unsure, say Y. | |
291 | ||
292 | config ARM64_ERRATUM_824069 | |
293 | bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop" | |
294 | default y | |
295 | help | |
296 | This option adds an alternative code sequence to work around ARM | |
297 | erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected | |
298 | to a coherent interconnect. | |
299 | ||
300 | If a Cortex-A53 processor is executing a store or prefetch for | |
301 | write instruction at the same time as a processor in another | |
302 | cluster is executing a cache maintenance operation to the same | |
303 | address, then this erratum might cause a clean cache line to be | |
304 | incorrectly marked as dirty. | |
305 | ||
306 | The workaround promotes data cache clean instructions to | |
307 | data cache clean-and-invalidate. | |
308 | Please note that this option does not necessarily enable the | |
309 | workaround, as it depends on the alternative framework, which will | |
310 | only patch the kernel if an affected CPU is detected. | |
311 | ||
312 | If unsure, say Y. | |
313 | ||
314 | config ARM64_ERRATUM_819472 | |
315 | bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption" | |
316 | default y | |
317 | help | |
318 | This option adds an alternative code sequence to work around ARM | |
319 | erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache | |
320 | present when it is connected to a coherent interconnect. | |
321 | ||
322 | If the processor is executing a load and store exclusive sequence at | |
323 | the same time as a processor in another cluster is executing a cache | |
324 | maintenance operation to the same address, then this erratum might | |
325 | cause data corruption. | |
326 | ||
327 | The workaround promotes data cache clean instructions to | |
328 | data cache clean-and-invalidate. | |
329 | Please note that this does not necessarily enable the workaround, | |
330 | as it depends on the alternative framework, which will only patch | |
331 | the kernel if an affected CPU is detected. | |
332 | ||
333 | If unsure, say Y. | |
334 | ||
335 | config ARM64_ERRATUM_832075 | |
336 | bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads" | |
337 | default y | |
338 | help | |
339 | This option adds an alternative code sequence to work around ARM | |
340 | erratum 832075 on Cortex-A57 parts up to r1p2. | |
341 | ||
342 | Affected Cortex-A57 parts might deadlock when exclusive load/store | |
343 | instructions to Write-Back memory are mixed with Device loads. | |
344 | ||
345 | The workaround is to promote device loads to use Load-Acquire | |
346 | semantics. | |
347 | Please note that this does not necessarily enable the workaround, | |
498cd5c3 MZ |
348 | as it depends on the alternative framework, which will only patch |
349 | the kernel if an affected CPU is detected. | |
350 | ||
351 | If unsure, say Y. | |
352 | ||
353 | config ARM64_ERRATUM_834220 | |
354 | bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault" | |
355 | depends on KVM | |
356 | default y | |
357 | help | |
358 | This option adds an alternative code sequence to work around ARM | |
359 | erratum 834220 on Cortex-A57 parts up to r1p2. | |
360 | ||
361 | Affected Cortex-A57 parts might report a Stage 2 translation | |
362 | fault as the result of a Stage 1 fault for load crossing a | |
363 | page boundary when there is a permission or device memory | |
364 | alignment fault at Stage 1 and a translation fault at Stage 2. | |
365 | ||
366 | The workaround is to verify that the Stage 1 translation | |
367 | doesn't generate a fault before handling the Stage 2 fault. | |
368 | Please note that this does not necessarily enable the workaround, | |
c0a01b84 AP |
369 | as it depends on the alternative framework, which will only patch |
370 | the kernel if an affected CPU is detected. | |
371 | ||
372 | If unsure, say Y. | |
373 | ||
905e8c5d WD |
374 | config ARM64_ERRATUM_845719 |
375 | bool "Cortex-A53: 845719: a load might read incorrect data" | |
376 | depends on COMPAT | |
377 | default y | |
378 | help | |
379 | This option adds an alternative code sequence to work around ARM | |
380 | erratum 845719 on Cortex-A53 parts up to r0p4. | |
381 | ||
382 | When running a compat (AArch32) userspace on an affected Cortex-A53 | |
383 | part, a load at EL0 from a virtual address that matches the bottom 32 | |
384 | bits of the virtual address used by a recent load at (AArch64) EL1 | |
385 | might return incorrect data. | |
386 | ||
387 | The workaround is to write the contextidr_el1 register on exception | |
388 | return to a 32-bit task. | |
389 | Please note that this does not necessarily enable the workaround, | |
390 | as it depends on the alternative framework, which will only patch | |
391 | the kernel if an affected CPU is detected. | |
392 | ||
393 | If unsure, say Y. | |
394 | ||
df057cc7 WD |
395 | config ARM64_ERRATUM_843419 |
396 | bool "Cortex-A53: 843419: A load or store might access an incorrect address" | |
397 | depends on MODULES | |
398 | default y | |
fd045f6c | 399 | select ARM64_MODULE_CMODEL_LARGE |
df057cc7 WD |
400 | help |
401 | This option builds kernel modules using the large memory model in | |
402 | order to avoid the use of the ADRP instruction, which can cause | |
403 | a subsequent memory access to use an incorrect address on Cortex-A53 | |
404 | parts up to r0p4. | |
405 | ||
406 | Note that the kernel itself must be linked with a version of ld | |
407 | which fixes potentially affected ADRP instructions through the | |
408 | use of veneers. | |
409 | ||
410 | If unsure, say Y. | |
411 | ||
94100970 RR |
412 | config CAVIUM_ERRATUM_22375 |
413 | bool "Cavium erratum 22375, 24313" | |
414 | default y | |
415 | help | |
416 | Enable workaround for erratum 22375, 24313. | |
417 | ||
418 | This implements two gicv3-its errata workarounds for ThunderX. Both | |
419 | with small impact affecting only ITS table allocation. | |
420 | ||
421 | erratum 22375: only alloc 8MB table size | |
422 | erratum 24313: ignore memory access type | |
423 | ||
424 | The fixes are in ITS initialization and basically ignore memory access | |
425 | type and table size provided by the TYPER and BASER registers. | |
426 | ||
427 | If unsure, say Y. | |
428 | ||
fbf8f40e GK |
429 | config CAVIUM_ERRATUM_23144 |
430 | bool "Cavium erratum 23144: ITS SYNC hang on dual socket system" | |
431 | depends on NUMA | |
432 | default y | |
433 | help | |
434 | ITS SYNC command hang for cross node io and collections/cpu mapping. | |
435 | ||
436 | If unsure, say Y. | |
437 | ||
6d4e11c5 RR |
438 | config CAVIUM_ERRATUM_23154 |
439 | bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed" | |
440 | default y | |
441 | help | |
442 | The gicv3 of ThunderX requires a modified version for | |
443 | reading the IAR status to ensure data synchronization | |
444 | (access to icc_iar1_el1 is not sync'ed before and after). | |
445 | ||
446 | If unsure, say Y. | |
447 | ||
104a0c02 AP |
448 | config CAVIUM_ERRATUM_27456 |
449 | bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption" | |
450 | default y | |
451 | help | |
452 | On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI | |
453 | instructions may cause the icache to become corrupted if it | |
454 | contains data for a non-current ASID. The fix is to | |
455 | invalidate the icache when changing the mm context. | |
456 | ||
457 | If unsure, say Y. | |
458 | ||
c0a01b84 AP |
459 | endmenu |
460 | ||
461 | ||
e41ceed0 JL |
462 | choice |
463 | prompt "Page size" | |
464 | default ARM64_4K_PAGES | |
465 | help | |
466 | Page size (translation granule) configuration. | |
467 | ||
468 | config ARM64_4K_PAGES | |
469 | bool "4KB" | |
470 | help | |
471 | This feature enables 4KB pages support. | |
472 | ||
44eaacf1 SP |
473 | config ARM64_16K_PAGES |
474 | bool "16KB" | |
475 | help | |
476 | The system will use 16KB pages support. AArch32 emulation | |
477 | requires applications compiled with 16K (or a multiple of 16K) | |
478 | aligned segments. | |
479 | ||
8c2c3df3 | 480 | config ARM64_64K_PAGES |
e41ceed0 | 481 | bool "64KB" |
8c2c3df3 CM |
482 | help |
483 | This feature enables 64KB pages support (4KB by default) | |
484 | allowing only two levels of page tables and faster TLB | |
db488be3 SP |
485 | look-up. AArch32 emulation requires applications compiled |
486 | with 64K aligned segments. | |
8c2c3df3 | 487 | |
e41ceed0 JL |
488 | endchoice |
489 | ||
490 | choice | |
491 | prompt "Virtual address space size" | |
492 | default ARM64_VA_BITS_39 if ARM64_4K_PAGES | |
44eaacf1 | 493 | default ARM64_VA_BITS_47 if ARM64_16K_PAGES |
e41ceed0 JL |
494 | default ARM64_VA_BITS_42 if ARM64_64K_PAGES |
495 | help | |
496 | Allows choosing one of multiple possible virtual address | |
497 | space sizes. The level of translation table is determined by | |
498 | a combination of page size and virtual address space size. | |
499 | ||
21539939 | 500 | config ARM64_VA_BITS_36 |
56a3f30e | 501 | bool "36-bit" if EXPERT |
21539939 SP |
502 | depends on ARM64_16K_PAGES |
503 | ||
e41ceed0 JL |
504 | config ARM64_VA_BITS_39 |
505 | bool "39-bit" | |
506 | depends on ARM64_4K_PAGES | |
507 | ||
508 | config ARM64_VA_BITS_42 | |
509 | bool "42-bit" | |
510 | depends on ARM64_64K_PAGES | |
511 | ||
44eaacf1 SP |
512 | config ARM64_VA_BITS_47 |
513 | bool "47-bit" | |
514 | depends on ARM64_16K_PAGES | |
515 | ||
c79b954b JL |
516 | config ARM64_VA_BITS_48 |
517 | bool "48-bit" | |
c79b954b | 518 | |
e41ceed0 JL |
519 | endchoice |
520 | ||
521 | config ARM64_VA_BITS | |
522 | int | |
21539939 | 523 | default 36 if ARM64_VA_BITS_36 |
e41ceed0 JL |
524 | default 39 if ARM64_VA_BITS_39 |
525 | default 42 if ARM64_VA_BITS_42 | |
44eaacf1 | 526 | default 47 if ARM64_VA_BITS_47 |
c79b954b | 527 | default 48 if ARM64_VA_BITS_48 |
e41ceed0 | 528 | |
a872013d WD |
529 | config CPU_BIG_ENDIAN |
530 | bool "Build big-endian kernel" | |
531 | help | |
532 | Say Y if you plan on running a kernel in big-endian mode. | |
533 | ||
f6e763b9 MB |
534 | config SCHED_MC |
535 | bool "Multi-core scheduler support" | |
f6e763b9 MB |
536 | help |
537 | Multi-core scheduler support improves the CPU scheduler's decision | |
538 | making when dealing with multi-core CPU chips at a cost of slightly | |
539 | increased overhead in some places. If unsure say N here. | |
540 | ||
541 | config SCHED_SMT | |
542 | bool "SMT scheduler support" | |
f6e763b9 MB |
543 | help |
544 | Improves the CPU scheduler's decision making when dealing with | |
545 | MultiThreading at a cost of slightly increased overhead in some | |
546 | places. If unsure say N here. | |
547 | ||
8c2c3df3 | 548 | config NR_CPUS |
62aa9655 GK |
549 | int "Maximum number of CPUs (2-4096)" |
550 | range 2 4096 | |
15942853 | 551 | # These have to remain sorted largest to smallest |
e3672649 | 552 | default "64" |
8c2c3df3 | 553 | |
9327e2c6 MR |
554 | config HOTPLUG_CPU |
555 | bool "Support for hot-pluggable CPUs" | |
217d453d | 556 | select GENERIC_IRQ_MIGRATION |
9327e2c6 MR |
557 | help |
558 | Say Y here to experiment with turning CPUs off and on. CPUs | |
559 | can be controlled through /sys/devices/system/cpu. | |
560 | ||
1a2db300 GK |
561 | # Common NUMA Features |
562 | config NUMA | |
563 | bool "Numa Memory Allocation and Scheduler Support" | |
564 | depends on SMP | |
565 | help | |
566 | Enable NUMA (Non Uniform Memory Access) support. | |
567 | ||
568 | The kernel will try to allocate memory used by a CPU on the | |
569 | local memory of the CPU and add some more | |
570 | NUMA awareness to the kernel. | |
571 | ||
572 | config NODES_SHIFT | |
573 | int "Maximum NUMA Nodes (as a power of 2)" | |
574 | range 1 10 | |
575 | default "2" | |
576 | depends on NEED_MULTIPLE_NODES | |
577 | help | |
578 | Specify the maximum number of NUMA Nodes available on the target | |
579 | system. Increases memory reserved to accommodate various tables. | |
580 | ||
581 | config USE_PERCPU_NUMA_NODE_ID | |
582 | def_bool y | |
583 | depends on NUMA | |
584 | ||
8c2c3df3 | 585 | source kernel/Kconfig.preempt |
f90df5e2 | 586 | source kernel/Kconfig.hz |
8c2c3df3 | 587 | |
83863f25 | 588 | config ARCH_SUPPORTS_DEBUG_PAGEALLOC |
da24eb1f | 589 | depends on !HIBERNATION |
83863f25 LA |
590 | def_bool y |
591 | ||
8c2c3df3 CM |
592 | config ARCH_HAS_HOLES_MEMORYMODEL |
593 | def_bool y if SPARSEMEM | |
594 | ||
595 | config ARCH_SPARSEMEM_ENABLE | |
596 | def_bool y | |
597 | select SPARSEMEM_VMEMMAP_ENABLE | |
598 | ||
599 | config ARCH_SPARSEMEM_DEFAULT | |
600 | def_bool ARCH_SPARSEMEM_ENABLE | |
601 | ||
602 | config ARCH_SELECT_MEMORY_MODEL | |
603 | def_bool ARCH_SPARSEMEM_ENABLE | |
604 | ||
605 | config HAVE_ARCH_PFN_VALID | |
606 | def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM | |
607 | ||
608 | config HW_PERF_EVENTS | |
6475b2d8 MR |
609 | def_bool y |
610 | depends on ARM_PMU | |
8c2c3df3 | 611 | |
084bd298 SC |
612 | config SYS_SUPPORTS_HUGETLBFS |
613 | def_bool y | |
614 | ||
084bd298 | 615 | config ARCH_WANT_HUGE_PMD_SHARE |
21539939 | 616 | def_bool y if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36) |
084bd298 | 617 | |
a41dc0e8 CM |
618 | config ARCH_HAS_CACHE_LINE_SIZE |
619 | def_bool y | |
620 | ||
8c2c3df3 CM |
621 | source "mm/Kconfig" |
622 | ||
a1ae65b2 AT |
623 | config SECCOMP |
624 | bool "Enable seccomp to safely compute untrusted bytecode" | |
625 | ---help--- | |
626 | This kernel feature is useful for number crunching applications | |
627 | that may need to compute untrusted bytecode during their | |
628 | execution. By using pipes or other transports made available to | |
629 | the process as file descriptors supporting the read/write | |
630 | syscalls, it's possible to isolate those applications in | |
631 | their own address space using seccomp. Once seccomp is | |
632 | enabled via prctl(PR_SET_SECCOMP), it cannot be disabled | |
633 | and the task is only allowed to execute a few safe syscalls | |
634 | defined by each seccomp mode. | |
635 | ||
dfd57bc3 SS |
636 | config PARAVIRT |
637 | bool "Enable paravirtualization code" | |
638 | help | |
639 | This changes the kernel so it can modify itself when it is run | |
640 | under a hypervisor, potentially improving performance significantly | |
641 | over full virtualization. | |
642 | ||
643 | config PARAVIRT_TIME_ACCOUNTING | |
644 | bool "Paravirtual steal time accounting" | |
645 | select PARAVIRT | |
646 | default n | |
647 | help | |
648 | Select this option to enable fine granularity task steal time | |
649 | accounting. Time spent executing other tasks in parallel with | |
650 | the current vCPU is discounted from the vCPU power. To account for | |
651 | that, there can be a small performance impact. | |
652 | ||
653 | If in doubt, say N here. | |
654 | ||
aa42aa13 SS |
655 | config XEN_DOM0 |
656 | def_bool y | |
657 | depends on XEN | |
658 | ||
659 | config XEN | |
c2ba1f7d | 660 | bool "Xen guest support on ARM64" |
aa42aa13 | 661 | depends on ARM64 && OF |
83862ccf | 662 | select SWIOTLB_XEN |
dfd57bc3 | 663 | select PARAVIRT |
aa42aa13 SS |
664 | help |
665 | Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64. | |
666 | ||
d03bb145 SC |
667 | config FORCE_MAX_ZONEORDER |
668 | int | |
669 | default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE) | |
44eaacf1 | 670 | default "12" if (ARM64_16K_PAGES && TRANSPARENT_HUGEPAGE) |
d03bb145 | 671 | default "11" |
44eaacf1 SP |
672 | help |
673 | The kernel memory allocator divides physically contiguous memory | |
674 | blocks into "zones", where each zone is a power of two number of | |
675 | pages. This option selects the largest power of two that the kernel | |
676 | keeps in the memory allocator. If you need to allocate very large | |
677 | blocks of physically contiguous memory, then you may need to | |
678 | increase this value. | |
679 | ||
680 | This config option is actually maximum order plus one. For example, | |
681 | a value of 11 means that the largest free memory block is 2^10 pages. | |
682 | ||
683 | We make sure that we can allocate upto a HugePage size for each configuration. | |
684 | Hence we have : | |
685 | MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2 | |
686 | ||
687 | However for 4K, we choose a higher default value, 11 as opposed to 10, giving us | |
688 | 4M allocations matching the default size used by generic code. | |
d03bb145 | 689 | |
1b907f46 WD |
690 | menuconfig ARMV8_DEPRECATED |
691 | bool "Emulate deprecated/obsolete ARMv8 instructions" | |
692 | depends on COMPAT | |
693 | help | |
694 | Legacy software support may require certain instructions | |
695 | that have been deprecated or obsoleted in the architecture. | |
696 | ||
697 | Enable this config to enable selective emulation of these | |
698 | features. | |
699 | ||
700 | If unsure, say Y | |
701 | ||
702 | if ARMV8_DEPRECATED | |
703 | ||
704 | config SWP_EMULATION | |
705 | bool "Emulate SWP/SWPB instructions" | |
706 | help | |
707 | ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that | |
708 | they are always undefined. Say Y here to enable software | |
709 | emulation of these instructions for userspace using LDXR/STXR. | |
710 | ||
711 | In some older versions of glibc [<=2.8] SWP is used during futex | |
712 | trylock() operations with the assumption that the code will not | |
713 | be preempted. This invalid assumption may be more likely to fail | |
714 | with SWP emulation enabled, leading to deadlock of the user | |
715 | application. | |
716 | ||
717 | NOTE: when accessing uncached shared regions, LDXR/STXR rely | |
718 | on an external transaction monitoring block called a global | |
719 | monitor to maintain update atomicity. If your system does not | |
720 | implement a global monitor, this option can cause programs that | |
721 | perform SWP operations to uncached memory to deadlock. | |
722 | ||
723 | If unsure, say Y | |
724 | ||
725 | config CP15_BARRIER_EMULATION | |
726 | bool "Emulate CP15 Barrier instructions" | |
727 | help | |
728 | The CP15 barrier instructions - CP15ISB, CP15DSB, and | |
729 | CP15DMB - are deprecated in ARMv8 (and ARMv7). It is | |
730 | strongly recommended to use the ISB, DSB, and DMB | |
731 | instructions instead. | |
732 | ||
733 | Say Y here to enable software emulation of these | |
734 | instructions for AArch32 userspace code. When this option is | |
735 | enabled, CP15 barrier usage is traced which can help | |
736 | identify software that needs updating. | |
737 | ||
738 | If unsure, say Y | |
739 | ||
2d888f48 SP |
740 | config SETEND_EMULATION |
741 | bool "Emulate SETEND instruction" | |
742 | help | |
743 | The SETEND instruction alters the data-endianness of the | |
744 | AArch32 EL0, and is deprecated in ARMv8. | |
745 | ||
746 | Say Y here to enable software emulation of the instruction | |
747 | for AArch32 userspace code. | |
748 | ||
749 | Note: All the cpus on the system must have mixed endian support at EL0 | |
750 | for this feature to be enabled. If a new CPU - which doesn't support mixed | |
751 | endian - is hotplugged in after this feature has been enabled, there could | |
752 | be unexpected results in the applications. | |
753 | ||
754 | If unsure, say Y | |
1b907f46 WD |
755 | endif |
756 | ||
0e4a0709 WD |
757 | menu "ARMv8.1 architectural features" |
758 | ||
759 | config ARM64_HW_AFDBM | |
760 | bool "Support for hardware updates of the Access and Dirty page flags" | |
761 | default y | |
762 | help | |
763 | The ARMv8.1 architecture extensions introduce support for | |
764 | hardware updates of the access and dirty information in page | |
765 | table entries. When enabled in TCR_EL1 (HA and HD bits) on | |
766 | capable processors, accesses to pages with PTE_AF cleared will | |
767 | set this bit instead of raising an access flag fault. | |
768 | Similarly, writes to read-only pages with the DBM bit set will | |
769 | clear the read-only bit (AP[2]) instead of raising a | |
770 | permission fault. | |
771 | ||
772 | Kernels built with this configuration option enabled continue | |
773 | to work on pre-ARMv8.1 hardware and the performance impact is | |
774 | minimal. If unsure, say Y. | |
775 | ||
776 | config ARM64_PAN | |
777 | bool "Enable support for Privileged Access Never (PAN)" | |
778 | default y | |
779 | help | |
780 | Privileged Access Never (PAN; part of the ARMv8.1 Extensions) | |
781 | prevents the kernel or hypervisor from accessing user-space (EL0) | |
782 | memory directly. | |
783 | ||
784 | Choosing this option will cause any unprotected (not using | |
785 | copy_to_user et al) memory access to fail with a permission fault. | |
786 | ||
787 | The feature is detected at runtime, and will remain as a 'nop' | |
788 | instruction if the cpu does not implement the feature. | |
789 | ||
790 | config ARM64_LSE_ATOMICS | |
791 | bool "Atomic instructions" | |
792 | help | |
793 | As part of the Large System Extensions, ARMv8.1 introduces new | |
794 | atomic instructions that are designed specifically to scale in | |
795 | very large systems. | |
796 | ||
797 | Say Y here to make use of these instructions for the in-kernel | |
798 | atomic routines. This incurs a small overhead on CPUs that do | |
799 | not support these instructions and requires the kernel to be | |
800 | built with binutils >= 2.25. | |
801 | ||
1f364c8c MZ |
802 | config ARM64_VHE |
803 | bool "Enable support for Virtualization Host Extensions (VHE)" | |
804 | default y | |
805 | help | |
806 | Virtualization Host Extensions (VHE) allow the kernel to run | |
807 | directly at EL2 (instead of EL1) on processors that support | |
808 | it. This leads to better performance for KVM, as they reduce | |
809 | the cost of the world switch. | |
810 | ||
811 | Selecting this option allows the VHE feature to be detected | |
812 | at runtime, and does not affect processors that do not | |
813 | implement this feature. | |
814 | ||
0e4a0709 WD |
815 | endmenu |
816 | ||
f993318b WD |
817 | menu "ARMv8.2 architectural features" |
818 | ||
57f4959b JM |
819 | config ARM64_UAO |
820 | bool "Enable support for User Access Override (UAO)" | |
821 | default y | |
822 | help | |
823 | User Access Override (UAO; part of the ARMv8.2 Extensions) | |
824 | causes the 'unprivileged' variant of the load/store instructions to | |
825 | be overriden to be privileged. | |
826 | ||
827 | This option changes get_user() and friends to use the 'unprivileged' | |
828 | variant of the load/store instructions. This ensures that user-space | |
829 | really did have access to the supplied memory. When addr_limit is | |
830 | set to kernel memory the UAO bit will be set, allowing privileged | |
831 | access to kernel memory. | |
832 | ||
833 | Choosing this option will cause copy_to_user() et al to use user-space | |
834 | memory permissions. | |
835 | ||
836 | The feature is detected at runtime, the kernel will use the | |
837 | regular load/store instructions if the cpu does not implement the | |
838 | feature. | |
839 | ||
f993318b WD |
840 | endmenu |
841 | ||
fd045f6c AB |
842 | config ARM64_MODULE_CMODEL_LARGE |
843 | bool | |
844 | ||
845 | config ARM64_MODULE_PLTS | |
846 | bool | |
847 | select ARM64_MODULE_CMODEL_LARGE | |
848 | select HAVE_MOD_ARCH_SPECIFIC | |
849 | ||
1e48ef7f AB |
850 | config RELOCATABLE |
851 | bool | |
852 | help | |
853 | This builds the kernel as a Position Independent Executable (PIE), | |
854 | which retains all relocation metadata required to relocate the | |
855 | kernel binary at runtime to a different virtual address than the | |
856 | address it was linked at. | |
857 | Since AArch64 uses the RELA relocation format, this requires a | |
858 | relocation pass at runtime even if the kernel is loaded at the | |
859 | same address it was linked at. | |
860 | ||
f80fb3a3 AB |
861 | config RANDOMIZE_BASE |
862 | bool "Randomize the address of the kernel image" | |
863 | select ARM64_MODULE_PLTS | |
864 | select RELOCATABLE | |
865 | help | |
866 | Randomizes the virtual address at which the kernel image is | |
867 | loaded, as a security feature that deters exploit attempts | |
868 | relying on knowledge of the location of kernel internals. | |
869 | ||
870 | It is the bootloader's job to provide entropy, by passing a | |
871 | random u64 value in /chosen/kaslr-seed at kernel entry. | |
872 | ||
2b5fe07a AB |
873 | When booting via the UEFI stub, it will invoke the firmware's |
874 | EFI_RNG_PROTOCOL implementation (if available) to supply entropy | |
875 | to the kernel proper. In addition, it will randomise the physical | |
876 | location of the kernel Image as well. | |
877 | ||
f80fb3a3 AB |
878 | If unsure, say N. |
879 | ||
880 | config RANDOMIZE_MODULE_REGION_FULL | |
881 | bool "Randomize the module region independently from the core kernel" | |
882 | depends on RANDOMIZE_BASE | |
883 | default y | |
884 | help | |
885 | Randomizes the location of the module region without considering the | |
886 | location of the core kernel. This way, it is impossible for modules | |
887 | to leak information about the location of core kernel data structures | |
888 | but it does imply that function calls between modules and the core | |
889 | kernel will need to be resolved via veneers in the module PLT. | |
890 | ||
891 | When this option is not set, the module region will be randomized over | |
892 | a limited range that contains the [_stext, _etext] interval of the | |
893 | core kernel, so branch relocations are always in range. | |
894 | ||
8c2c3df3 CM |
895 | endmenu |
896 | ||
897 | menu "Boot options" | |
898 | ||
5e89c55e LP |
899 | config ARM64_ACPI_PARKING_PROTOCOL |
900 | bool "Enable support for the ARM64 ACPI parking protocol" | |
901 | depends on ACPI | |
902 | help | |
903 | Enable support for the ARM64 ACPI parking protocol. If disabled | |
904 | the kernel will not allow booting through the ARM64 ACPI parking | |
905 | protocol even if the corresponding data is present in the ACPI | |
906 | MADT table. | |
907 | ||
8c2c3df3 CM |
908 | config CMDLINE |
909 | string "Default kernel command string" | |
910 | default "" | |
911 | help | |
912 | Provide a set of default command-line options at build time by | |
913 | entering them here. As a minimum, you should specify the the | |
914 | root device (e.g. root=/dev/nfs). | |
915 | ||
916 | config CMDLINE_FORCE | |
917 | bool "Always use the default kernel command string" | |
918 | help | |
919 | Always use the default kernel command string, even if the boot | |
920 | loader passes other arguments to the kernel. | |
921 | This is useful if you cannot or don't want to change the | |
922 | command-line options your boot loader passes to the kernel. | |
923 | ||
f4f75ad5 AB |
924 | config EFI_STUB |
925 | bool | |
926 | ||
f84d0275 MS |
927 | config EFI |
928 | bool "UEFI runtime support" | |
929 | depends on OF && !CPU_BIG_ENDIAN | |
930 | select LIBFDT | |
931 | select UCS2_STRING | |
932 | select EFI_PARAMS_FROM_FDT | |
e15dd494 | 933 | select EFI_RUNTIME_WRAPPERS |
f4f75ad5 AB |
934 | select EFI_STUB |
935 | select EFI_ARMSTUB | |
f84d0275 MS |
936 | default y |
937 | help | |
938 | This option provides support for runtime services provided | |
939 | by UEFI firmware (such as non-volatile variables, realtime | |
3c7f2550 MS |
940 | clock, and platform reset). A UEFI stub is also provided to |
941 | allow the kernel to be booted as an EFI application. This | |
942 | is only useful on systems that have UEFI firmware. | |
f84d0275 | 943 | |
d1ae8c00 YL |
944 | config DMI |
945 | bool "Enable support for SMBIOS (DMI) tables" | |
946 | depends on EFI | |
947 | default y | |
948 | help | |
949 | This enables SMBIOS/DMI feature for systems. | |
950 | ||
951 | This option is only useful on systems that have UEFI firmware. | |
952 | However, even with this option, the resultant kernel should | |
953 | continue to boot on existing non-UEFI platforms. | |
954 | ||
8c2c3df3 CM |
955 | endmenu |
956 | ||
957 | menu "Userspace binary formats" | |
958 | ||
959 | source "fs/Kconfig.binfmt" | |
960 | ||
961 | config COMPAT | |
962 | bool "Kernel support for 32-bit EL0" | |
755e70b7 | 963 | depends on ARM64_4K_PAGES || EXPERT |
8c2c3df3 | 964 | select COMPAT_BINFMT_ELF |
af1839eb | 965 | select HAVE_UID16 |
84b9e9b4 | 966 | select OLD_SIGSUSPEND3 |
51682036 | 967 | select COMPAT_OLD_SIGACTION |
8c2c3df3 CM |
968 | help |
969 | This option enables support for a 32-bit EL0 running under a 64-bit | |
970 | kernel at EL1. AArch32-specific components such as system calls, | |
971 | the user helper functions, VFP support and the ptrace interface are | |
972 | handled appropriately by the kernel. | |
973 | ||
44eaacf1 SP |
974 | If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware |
975 | that you will only be able to execute AArch32 binaries that were compiled | |
976 | with page size aligned segments. | |
a8fcd8b1 | 977 | |
8c2c3df3 CM |
978 | If you want to execute 32-bit userspace applications, say Y. |
979 | ||
980 | config SYSVIPC_COMPAT | |
981 | def_bool y | |
982 | depends on COMPAT && SYSVIPC | |
983 | ||
984 | endmenu | |
985 | ||
166936ba LP |
986 | menu "Power management options" |
987 | ||
988 | source "kernel/power/Kconfig" | |
989 | ||
82869ac5 JM |
990 | config ARCH_HIBERNATION_POSSIBLE |
991 | def_bool y | |
992 | depends on CPU_PM | |
993 | ||
994 | config ARCH_HIBERNATION_HEADER | |
995 | def_bool y | |
996 | depends on HIBERNATION | |
997 | ||
166936ba LP |
998 | config ARCH_SUSPEND_POSSIBLE |
999 | def_bool y | |
1000 | ||
166936ba LP |
1001 | endmenu |
1002 | ||
1307220d LP |
1003 | menu "CPU Power Management" |
1004 | ||
1005 | source "drivers/cpuidle/Kconfig" | |
1006 | ||
52e7e816 RH |
1007 | source "drivers/cpufreq/Kconfig" |
1008 | ||
1009 | endmenu | |
1010 | ||
8c2c3df3 CM |
1011 | source "net/Kconfig" |
1012 | ||
1013 | source "drivers/Kconfig" | |
1014 | ||
f84d0275 MS |
1015 | source "drivers/firmware/Kconfig" |
1016 | ||
b6a02173 GG |
1017 | source "drivers/acpi/Kconfig" |
1018 | ||
8c2c3df3 CM |
1019 | source "fs/Kconfig" |
1020 | ||
c3eb5b14 MZ |
1021 | source "arch/arm64/kvm/Kconfig" |
1022 | ||
8c2c3df3 CM |
1023 | source "arch/arm64/Kconfig.debug" |
1024 | ||
1025 | source "security/Kconfig" | |
1026 | ||
1027 | source "crypto/Kconfig" | |
2c98833a AB |
1028 | if CRYPTO |
1029 | source "arch/arm64/crypto/Kconfig" | |
1030 | endif | |
8c2c3df3 CM |
1031 | |
1032 | source "lib/Kconfig" |