Commit | Line | Data |
---|---|---|
ec8f24b7 | 1 | # SPDX-License-Identifier: GPL-2.0-only |
8c2c3df3 CM |
2 | config ARM64 |
3 | def_bool y | |
6251d380 | 4 | select ACPI_APMT if ACPI |
b6197b93 | 5 | select ACPI_CCA_REQUIRED if ACPI |
d8f4f161 | 6 | select ACPI_GENERIC_GSI if ACPI |
5f1ae4eb | 7 | select ACPI_GTDT if ACPI |
c6bb8f89 | 8 | select ACPI_IORT if ACPI |
6933de0c | 9 | select ACPI_REDUCED_HARDWARE_ONLY if ACPI |
52146173 | 10 | select ACPI_MCFG if (ACPI && PCI) |
888125a7 | 11 | select ACPI_SPCR_TABLE if ACPI |
0ce82232 | 12 | select ACPI_PPTT if ACPI |
09587a09 | 13 | select ARCH_HAS_DEBUG_WX |
6dd8b1a0 | 14 | select ARCH_BINFMT_ELF_EXTRA_PHDRS |
ab7876a9 | 15 | select ARCH_BINFMT_ELF_STATE |
cd9bc2c9 | 16 | select ARCH_CORRECT_STACKTRACE_ON_KRETPROBE |
1e866974 | 17 | select ARCH_ENABLE_HUGEPAGE_MIGRATION if HUGETLB_PAGE && MIGRATION |
91024b3c AK |
18 | select ARCH_ENABLE_MEMORY_HOTPLUG |
19 | select ARCH_ENABLE_MEMORY_HOTREMOVE | |
66f24fa7 | 20 | select ARCH_ENABLE_SPLIT_PMD_PTLOCK if PGTABLE_LEVELS > 2 |
1e866974 | 21 | select ARCH_ENABLE_THP_MIGRATION if TRANSPARENT_HUGEPAGE |
c2280be8 | 22 | select ARCH_HAS_CACHE_LINE_SIZE |
2792d84e | 23 | select ARCH_HAS_CURRENT_STACK_POINTER |
ec6d06ef | 24 | select ARCH_HAS_DEBUG_VIRTUAL |
399145f9 | 25 | select ARCH_HAS_DEBUG_VM_PGTABLE |
13bf5ced | 26 | select ARCH_HAS_DMA_PREP_COHERENT |
38b04a74 | 27 | select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI |
e75bef2a | 28 | select ARCH_HAS_FAST_MULTIPLIER |
6974f0c4 | 29 | select ARCH_HAS_FORTIFY_SOURCE |
957e3fac | 30 | select ARCH_HAS_GCOV_PROFILE_ALL |
4eb0716e | 31 | select ARCH_HAS_GIGANTIC_PAGE |
5e4c7549 | 32 | select ARCH_HAS_KCOV |
d8ae8a37 | 33 | select ARCH_HAS_KEEPINITRD |
f1e3a12b | 34 | select ARCH_HAS_MEMBARRIER_SYNC_CORE |
6cc9203b | 35 | select ARCH_HAS_NMI_SAFE_THIS_CPU_OPS |
0ebeea8c | 36 | select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE |
73b20c84 | 37 | select ARCH_HAS_PTE_DEVMAP |
3010a5ea | 38 | select ARCH_HAS_PTE_SPECIAL |
71ce1ab5 | 39 | select ARCH_HAS_HW_PTE_YOUNG |
347cb6af | 40 | select ARCH_HAS_SETUP_DMA_OPS |
4739d53f | 41 | select ARCH_HAS_SET_DIRECT_MAP |
d2852a22 | 42 | select ARCH_HAS_SET_MEMORY |
5fc57df2 | 43 | select ARCH_STACKWALK |
ad21fc4f LA |
44 | select ARCH_HAS_STRICT_KERNEL_RWX |
45 | select ARCH_HAS_STRICT_MODULE_RWX | |
886643b7 CH |
46 | select ARCH_HAS_SYNC_DMA_FOR_DEVICE |
47 | select ARCH_HAS_SYNC_DMA_FOR_CPU | |
4378a7d4 | 48 | select ARCH_HAS_SYSCALL_WRAPPER |
dc2acded | 49 | select ARCH_HAS_TEARDOWN_DMA_OPS if IOMMU_SUPPORT |
1f85008e | 50 | select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST |
63703f37 | 51 | select ARCH_HAS_ZONE_DMA_SET if EXPERT |
ab7876a9 | 52 | select ARCH_HAVE_ELF_PROT |
396a5d4a | 53 | select ARCH_HAVE_NMI_SAFE_CMPXCHG |
d593d64f | 54 | select ARCH_HAVE_TRACE_MMIO_ACCESS |
7ef858da TG |
55 | select ARCH_INLINE_READ_LOCK if !PREEMPTION |
56 | select ARCH_INLINE_READ_LOCK_BH if !PREEMPTION | |
57 | select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPTION | |
58 | select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPTION | |
59 | select ARCH_INLINE_READ_UNLOCK if !PREEMPTION | |
60 | select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPTION | |
61 | select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPTION | |
62 | select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPTION | |
63 | select ARCH_INLINE_WRITE_LOCK if !PREEMPTION | |
64 | select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPTION | |
65 | select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPTION | |
66 | select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPTION | |
67 | select ARCH_INLINE_WRITE_UNLOCK if !PREEMPTION | |
68 | select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPTION | |
69 | select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPTION | |
70 | select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPTION | |
71 | select ARCH_INLINE_SPIN_TRYLOCK if !PREEMPTION | |
72 | select ARCH_INLINE_SPIN_TRYLOCK_BH if !PREEMPTION | |
73 | select ARCH_INLINE_SPIN_LOCK if !PREEMPTION | |
74 | select ARCH_INLINE_SPIN_LOCK_BH if !PREEMPTION | |
75 | select ARCH_INLINE_SPIN_LOCK_IRQ if !PREEMPTION | |
76 | select ARCH_INLINE_SPIN_LOCK_IRQSAVE if !PREEMPTION | |
77 | select ARCH_INLINE_SPIN_UNLOCK if !PREEMPTION | |
78 | select ARCH_INLINE_SPIN_UNLOCK_BH if !PREEMPTION | |
79 | select ARCH_INLINE_SPIN_UNLOCK_IRQ if !PREEMPTION | |
80 | select ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE if !PREEMPTION | |
350e88ba | 81 | select ARCH_KEEP_MEMBLOCK |
04d5ea46 | 82 | select ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE |
c63c8700 | 83 | select ARCH_USE_CMPXCHG_LOCKREF |
bf7f15c5 | 84 | select ARCH_USE_GNU_PROPERTY |
dce44566 | 85 | select ARCH_USE_MEMTEST |
087133ac | 86 | select ARCH_USE_QUEUED_RWLOCKS |
c1109047 | 87 | select ARCH_USE_QUEUED_SPINLOCKS |
50479d58 | 88 | select ARCH_USE_SYM_ANNOTATIONS |
5d6ad668 | 89 | select ARCH_SUPPORTS_DEBUG_PAGEALLOC |
855f9a8e | 90 | select ARCH_SUPPORTS_HUGETLBFS |
c484f256 | 91 | select ARCH_SUPPORTS_MEMORY_FAILURE |
5287569a | 92 | select ARCH_SUPPORTS_SHADOW_CALL_STACK if CC_HAVE_SHADOW_CALL_STACK |
112b6a8e ST |
93 | select ARCH_SUPPORTS_LTO_CLANG if CPU_LITTLE_ENDIAN |
94 | select ARCH_SUPPORTS_LTO_CLANG_THIN | |
9186ad8e | 95 | select ARCH_SUPPORTS_CFI_CLANG |
4badad35 | 96 | select ARCH_SUPPORTS_ATOMIC_RMW |
42a7ba16 | 97 | select ARCH_SUPPORTS_INT128 if CC_HAS_INT128 |
56166230 | 98 | select ARCH_SUPPORTS_NUMA_BALANCING |
42b25471 | 99 | select ARCH_SUPPORTS_PAGE_TABLE_CHECK |
cd7f176a | 100 | select ARCH_SUPPORTS_PER_VMA_LOCK |
43b3dfdd | 101 | select ARCH_WANT_BATCHED_UNMAP_TLB_FLUSH |
84c187af | 102 | select ARCH_WANT_COMPAT_IPC_PARSE_VERSION if COMPAT |
81c22041 | 103 | select ARCH_WANT_DEFAULT_BPF_JIT |
67f3977f | 104 | select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT |
b6f35981 | 105 | select ARCH_WANT_FRAME_POINTERS |
3876d4a3 | 106 | select ARCH_WANT_HUGE_PMD_SHARE if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36) |
59612b24 | 107 | select ARCH_WANT_LD_ORPHAN_WARN |
51c2ee6d | 108 | select ARCH_WANTS_NO_INSTR |
d0637c50 | 109 | select ARCH_WANTS_THP_SWAP if ARM64_4K_PAGES |
f0b7f8a4 | 110 | select ARCH_HAS_UBSAN_SANITIZE_ALL |
25c92a37 | 111 | select ARM_AMBA |
1aee5d7a | 112 | select ARM_ARCH_TIMER |
c4188edc | 113 | select ARM_GIC |
875cbf3e | 114 | select AUDIT_ARCH_COMPAT_GENERIC |
3ee80364 | 115 | select ARM_GIC_V2M if PCI |
021f6537 | 116 | select ARM_GIC_V3 |
3ee80364 | 117 | select ARM_GIC_V3_ITS if PCI |
bff60792 | 118 | select ARM_PSCI_FW |
10916706 | 119 | select BUILDTIME_TABLE_SORT |
db2789b5 | 120 | select CLONE_BACKWARDS |
7ca2ef33 | 121 | select COMMON_CLK |
166936ba | 122 | select CPU_PM if (SUSPEND || CPU_IDLE) |
7481cddf | 123 | select CRC32 |
7bc13fd3 | 124 | select DCACHE_WORD_ACCESS |
cfce092d | 125 | select DYNAMIC_FTRACE if FUNCTION_TRACER |
1c1a429e | 126 | select DMA_BOUNCE_UNALIGNED_KMALLOC |
0c3b3171 | 127 | select DMA_DIRECT_REMAP |
ef37566c | 128 | select EDAC_SUPPORT |
2f34f173 | 129 | select FRAME_POINTER |
47a15aa5 | 130 | select FUNCTION_ALIGNMENT_4B |
baaf553d | 131 | select FUNCTION_ALIGNMENT_8B if DYNAMIC_FTRACE_WITH_CALL_OPS |
d4932f9e | 132 | select GENERIC_ALLOCATOR |
2ef7a295 | 133 | select GENERIC_ARCH_TOPOLOGY |
4b3dc967 | 134 | select GENERIC_CLOCKEVENTS_BROADCAST |
3be1a5c4 | 135 | select GENERIC_CPU_AUTOPROBE |
d127db1a | 136 | select GENERIC_CPU_DEVICES |
61ae1321 | 137 | select GENERIC_CPU_VULNERABILITIES |
bf4b558e | 138 | select GENERIC_EARLY_IOREMAP |
2314ee4d | 139 | select GENERIC_IDLE_POLL_SETUP |
f23eab0b | 140 | select GENERIC_IOREMAP |
d3afc7f1 | 141 | select GENERIC_IRQ_IPI |
8c2c3df3 CM |
142 | select GENERIC_IRQ_PROBE |
143 | select GENERIC_IRQ_SHOW | |
6544e67b | 144 | select GENERIC_IRQ_SHOW_LEVEL |
6585bd82 | 145 | select GENERIC_LIB_DEVMEM_IS_ALLOWED |
cb61f676 | 146 | select GENERIC_PCI_IOMAP |
102f45fd | 147 | select GENERIC_PTDUMP |
65cd4f6c | 148 | select GENERIC_SCHED_CLOCK |
8c2c3df3 CM |
149 | select GENERIC_SMP_IDLE_THREAD |
150 | select GENERIC_TIME_VSYSCALL | |
28b1a824 | 151 | select GENERIC_GETTIMEOFDAY |
9614cc57 | 152 | select GENERIC_VDSO_TIME_NS |
8c2c3df3 | 153 | select HARDIRQS_SW_RESEND |
fcbfe812 | 154 | select HAS_IOPORT |
45544eee | 155 | select HAVE_MOVE_PMD |
f5308c89 | 156 | select HAVE_MOVE_PUD |
eb01d42a | 157 | select HAVE_PCI |
9f9a35a7 | 158 | select HAVE_ACPI_APEI if (ACPI && EFI) |
2a19be61 | 159 | select HAVE_ALIGNED_STRUCT_PAGE |
875cbf3e | 160 | select HAVE_ARCH_AUDITSYSCALL |
8e7a4cef | 161 | select HAVE_ARCH_BITREVERSE |
689eae42 | 162 | select HAVE_ARCH_COMPILER_H |
e9207223 | 163 | select HAVE_ARCH_HUGE_VMALLOC |
324420bf | 164 | select HAVE_ARCH_HUGE_VMAP |
9732cafd | 165 | select HAVE_ARCH_JUMP_LABEL |
c296146c | 166 | select HAVE_ARCH_JUMP_LABEL_RELATIVE |
e17d8025 | 167 | select HAVE_ARCH_KASAN if !(ARM64_16K_PAGES && ARM64_VA_BITS_48) |
71b613fc | 168 | select HAVE_ARCH_KASAN_VMALLOC if HAVE_ARCH_KASAN |
2d4acb90 | 169 | select HAVE_ARCH_KASAN_SW_TAGS if HAVE_ARCH_KASAN |
94ab5b61 | 170 | select HAVE_ARCH_KASAN_HW_TAGS if (HAVE_ARCH_KASAN && ARM64_MTE) |
dd03762a KW |
171 | # Some instrumentation may be unsound, hence EXPERT |
172 | select HAVE_ARCH_KCSAN if EXPERT | |
840b2398 | 173 | select HAVE_ARCH_KFENCE |
9529247d | 174 | select HAVE_ARCH_KGDB |
8f0d3aa9 DC |
175 | select HAVE_ARCH_MMAP_RND_BITS |
176 | select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT | |
271ca788 | 177 | select HAVE_ARCH_PREL32_RELOCATIONS |
70918779 | 178 | select HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET |
a1ae65b2 | 179 | select HAVE_ARCH_SECCOMP_FILTER |
0b3e3366 | 180 | select HAVE_ARCH_STACKLEAK |
9e8084d3 | 181 | select HAVE_ARCH_THREAD_STRUCT_WHITELIST |
8c2c3df3 | 182 | select HAVE_ARCH_TRACEHOOK |
8ee70879 | 183 | select HAVE_ARCH_TRANSPARENT_HUGEPAGE |
e3067861 | 184 | select HAVE_ARCH_VMAP_STACK |
8ee70879 | 185 | select HAVE_ARM_SMCCC |
2ff2b7ec | 186 | select HAVE_ASM_MODVERSIONS |
6077776b | 187 | select HAVE_EBPF_JIT |
af64d2aa | 188 | select HAVE_C_RECORDMCOUNT |
5284e1b4 | 189 | select HAVE_CMPXCHG_DOUBLE |
95eff6b2 | 190 | select HAVE_CMPXCHG_LOCAL |
24a9c541 | 191 | select HAVE_CONTEXT_TRACKING_USER |
b69ec42b | 192 | select HAVE_DEBUG_KMEMLEAK |
6ac2104d | 193 | select HAVE_DMA_CONTIGUOUS |
bd7d38db | 194 | select HAVE_DYNAMIC_FTRACE |
2aa6ac03 FR |
195 | select HAVE_DYNAMIC_FTRACE_WITH_ARGS \ |
196 | if $(cc-option,-fpatchable-function-entry=2) | |
197 | select HAVE_DYNAMIC_FTRACE_WITH_DIRECT_CALLS \ | |
198 | if DYNAMIC_FTRACE_WITH_ARGS && DYNAMIC_FTRACE_WITH_CALL_OPS | |
baaf553d | 199 | select HAVE_DYNAMIC_FTRACE_WITH_CALL_OPS \ |
b3f11af9 MR |
200 | if (DYNAMIC_FTRACE_WITH_ARGS && !CFI_CLANG && \ |
201 | !CC_OPTIMIZE_FOR_SIZE) | |
a31d793d | 202 | select FTRACE_MCOUNT_USE_PATCHABLE_FUNCTION_ENTRY \ |
26299b3f | 203 | if DYNAMIC_FTRACE_WITH_ARGS |
8c3526fb FR |
204 | select HAVE_SAMPLE_FTRACE_DIRECT |
205 | select HAVE_SAMPLE_FTRACE_DIRECT_MULTI | |
50afc33a | 206 | select HAVE_EFFICIENT_UNALIGNED_ACCESS |
67a929e0 | 207 | select HAVE_FAST_GUP |
af64d2aa | 208 | select HAVE_FTRACE_MCOUNT_RECORD |
819e50e2 | 209 | select HAVE_FUNCTION_TRACER |
42d038c4 | 210 | select HAVE_FUNCTION_ERROR_INJECTION |
36469703 | 211 | select HAVE_FUNCTION_GRAPH_RETVAL if HAVE_FUNCTION_GRAPH_TRACER |
819e50e2 | 212 | select HAVE_FUNCTION_GRAPH_TRACER |
6b90bd4b | 213 | select HAVE_GCC_PLUGINS |
d7a0fe9e DA |
214 | select HAVE_HARDLOCKUP_DETECTOR_PERF if PERF_EVENTS && \ |
215 | HW_PERF_EVENTS && HAVE_PERF_EVENTS_NMI | |
8c2c3df3 | 216 | select HAVE_HW_BREAKPOINT if PERF_EVENTS |
893dea9c | 217 | select HAVE_IOREMAP_PROT |
24da208d | 218 | select HAVE_IRQ_TIME_ACCOUNTING |
e26bb75a | 219 | select HAVE_KVM |
ea3752ba | 220 | select HAVE_MOD_ARCH_SPECIFIC |
396a5d4a | 221 | select HAVE_NMI |
8c2c3df3 | 222 | select HAVE_PERF_EVENTS |
d7a0fe9e | 223 | select HAVE_PERF_EVENTS_NMI if ARM64_PSEUDO_NMI |
2ee0d7fd JP |
224 | select HAVE_PERF_REGS |
225 | select HAVE_PERF_USER_STACK_DUMP | |
1b2d3451 | 226 | select HAVE_PREEMPT_DYNAMIC_KEY |
0a8ea52c | 227 | select HAVE_REGS_AND_STACK_ACCESS_API |
a68773bd | 228 | select HAVE_POSIX_CPU_TIMERS_TASK_WORK |
a823c35f | 229 | select HAVE_FUNCTION_ARG_ACCESS_API |
ff2e6d72 | 230 | select MMU_GATHER_RCU_TABLE_FREE |
409d5db4 | 231 | select HAVE_RSEQ |
d148eac0 | 232 | select HAVE_STACKPROTECTOR |
055b1212 | 233 | select HAVE_SYSCALL_TRACEPOINTS |
2dd0e8d2 | 234 | select HAVE_KPROBES |
cd1ee3b1 | 235 | select HAVE_KRETPROBES |
28b1a824 | 236 | select HAVE_GENERIC_VDSO |
b3091f17 | 237 | select HOTPLUG_CORE_SYNC_DEAD if HOTPLUG_CPU |
8c2c3df3 | 238 | select IRQ_DOMAIN |
e8557d1f | 239 | select IRQ_FORCED_THREADING |
f6f37d93 | 240 | select KASAN_VMALLOC if KASAN |
ae870a68 | 241 | select LOCK_MM_AND_FIND_VMA |
fea2acaa | 242 | select MODULES_USE_ELF_RELA |
f616ab59 | 243 | select NEED_DMA_MAP_STATE |
86596f0a | 244 | select NEED_SG_DMA_LENGTH |
8c2c3df3 CM |
245 | select OF |
246 | select OF_EARLY_FLATTREE | |
2eac9c2d | 247 | select PCI_DOMAINS_GENERIC if PCI |
52146173 | 248 | select PCI_ECAM if (ACPI && PCI) |
20f1b79d | 249 | select PCI_SYSCALL if PCI |
aa1e8ec1 CM |
250 | select POWER_RESET |
251 | select POWER_SUPPLY | |
8c2c3df3 | 252 | select SPARSE_IRQ |
09230cbc | 253 | select SWIOTLB |
7ac57a89 | 254 | select SYSCTL_EXCEPTION_TRACE |
c02433dd | 255 | select THREAD_INFO_IN_TASK |
7677f7fd | 256 | select HAVE_ARCH_USERFAULTFD_MINOR if USERFAULTFD |
4aae683f | 257 | select TRACE_IRQFLAGS_SUPPORT |
3381da25 | 258 | select TRACE_IRQFLAGS_NMI_SUPPORT |
8eb858c4 | 259 | select HAVE_SOFTIRQ_ON_OWN_STACK |
8c2c3df3 CM |
260 | help |
261 | ARM 64-bit (AArch64) Linux support. | |
262 | ||
26299b3f | 263 | config CLANG_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS |
45bd8951 NC |
264 | def_bool CC_IS_CLANG |
265 | # https://github.com/ClangBuiltLinux/linux/issues/1507 | |
266 | depends on AS_IS_GNU || (AS_IS_LLVM && (LD_IS_LLD || LD_VERSION >= 23600)) | |
26299b3f | 267 | select HAVE_DYNAMIC_FTRACE_WITH_ARGS |
45bd8951 | 268 | |
26299b3f | 269 | config GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS |
45bd8951 NC |
270 | def_bool CC_IS_GCC |
271 | depends on $(cc-option,-fpatchable-function-entry=2) | |
26299b3f | 272 | select HAVE_DYNAMIC_FTRACE_WITH_ARGS |
45bd8951 | 273 | |
8c2c3df3 CM |
274 | config 64BIT |
275 | def_bool y | |
276 | ||
8c2c3df3 CM |
277 | config MMU |
278 | def_bool y | |
279 | ||
c0d6de32 | 280 | config ARM64_CONT_PTE_SHIFT |
030c4d24 | 281 | int |
d3e5bab9 AB |
282 | default 5 if PAGE_SIZE_64KB |
283 | default 7 if PAGE_SIZE_16KB | |
030c4d24 MR |
284 | default 4 |
285 | ||
e6765941 GS |
286 | config ARM64_CONT_PMD_SHIFT |
287 | int | |
d3e5bab9 AB |
288 | default 5 if PAGE_SIZE_64KB |
289 | default 5 if PAGE_SIZE_16KB | |
e6765941 GS |
290 | default 4 |
291 | ||
8f0d3aa9 | 292 | config ARCH_MMAP_RND_BITS_MIN |
d3e5bab9 AB |
293 | default 14 if PAGE_SIZE_64KB |
294 | default 16 if PAGE_SIZE_16KB | |
3cb7e662 | 295 | default 18 |
8f0d3aa9 DC |
296 | |
297 | # max bits determined by the following formula: | |
298 | # VA_BITS - PAGE_SHIFT - 3 | |
299 | config ARCH_MMAP_RND_BITS_MAX | |
3cb7e662 JH |
300 | default 19 if ARM64_VA_BITS=36 |
301 | default 24 if ARM64_VA_BITS=39 | |
302 | default 27 if ARM64_VA_BITS=42 | |
303 | default 30 if ARM64_VA_BITS=47 | |
304 | default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES | |
305 | default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES | |
306 | default 33 if ARM64_VA_BITS=48 | |
307 | default 14 if ARM64_64K_PAGES | |
308 | default 16 if ARM64_16K_PAGES | |
309 | default 18 | |
8f0d3aa9 DC |
310 | |
311 | config ARCH_MMAP_RND_COMPAT_BITS_MIN | |
3cb7e662 JH |
312 | default 7 if ARM64_64K_PAGES |
313 | default 9 if ARM64_16K_PAGES | |
314 | default 11 | |
8f0d3aa9 DC |
315 | |
316 | config ARCH_MMAP_RND_COMPAT_BITS_MAX | |
3cb7e662 | 317 | default 16 |
8f0d3aa9 | 318 | |
ce816fa8 | 319 | config NO_IOPORT_MAP |
d1e6dc91 | 320 | def_bool y if !PCI |
8c2c3df3 CM |
321 | |
322 | config STACKTRACE_SUPPORT | |
323 | def_bool y | |
324 | ||
bf0c4e04 JVS |
325 | config ILLEGAL_POINTER_VALUE |
326 | hex | |
327 | default 0xdead000000000000 | |
328 | ||
8c2c3df3 CM |
329 | config LOCKDEP_SUPPORT |
330 | def_bool y | |
331 | ||
9fb7410f DM |
332 | config GENERIC_BUG |
333 | def_bool y | |
334 | depends on BUG | |
335 | ||
336 | config GENERIC_BUG_RELATIVE_POINTERS | |
337 | def_bool y | |
338 | depends on GENERIC_BUG | |
339 | ||
8c2c3df3 CM |
340 | config GENERIC_HWEIGHT |
341 | def_bool y | |
342 | ||
343 | config GENERIC_CSUM | |
3cb7e662 | 344 | def_bool y |
8c2c3df3 CM |
345 | |
346 | config GENERIC_CALIBRATE_DELAY | |
347 | def_bool y | |
348 | ||
4b3dc967 WD |
349 | config SMP |
350 | def_bool y | |
351 | ||
4cfb3613 AB |
352 | config KERNEL_MODE_NEON |
353 | def_bool y | |
354 | ||
92cc15fc RH |
355 | config FIX_EARLYCON_MEM |
356 | def_bool y | |
357 | ||
9f25e6ad KS |
358 | config PGTABLE_LEVELS |
359 | int | |
21539939 | 360 | default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36 |
9f25e6ad | 361 | default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42 |
b6d00d47 | 362 | default 3 if ARM64_64K_PAGES && (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) |
9f25e6ad | 363 | default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39 |
44eaacf1 SP |
364 | default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47 |
365 | default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48 | |
9f25e6ad | 366 | |
9842ceae PA |
367 | config ARCH_SUPPORTS_UPROBES |
368 | def_bool y | |
369 | ||
8f360948 AB |
370 | config ARCH_PROC_KCORE_TEXT |
371 | def_bool y | |
372 | ||
8bf9284d VM |
373 | config BROKEN_GAS_INST |
374 | def_bool !$(as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n) | |
375 | ||
9df3f508 MR |
376 | config BUILTIN_RETURN_ADDRESS_STRIPS_PAC |
377 | bool | |
378 | # Clang's __builtin_return_adddress() strips the PAC since 12.0.0 | |
379 | # https://reviews.llvm.org/D75044 | |
380 | default y if CC_IS_CLANG && (CLANG_VERSION >= 120000) | |
381 | # GCC's __builtin_return_address() strips the PAC since 11.1.0, | |
382 | # and this was backported to 10.2.0, 9.4.0, 8.5.0, but not earlier | |
383 | # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94891 | |
384 | default y if CC_IS_GCC && (GCC_VERSION >= 110100) | |
385 | default y if CC_IS_GCC && (GCC_VERSION >= 100200) && (GCC_VERSION < 110000) | |
386 | default y if CC_IS_GCC && (GCC_VERSION >= 90400) && (GCC_VERSION < 100000) | |
387 | default y if CC_IS_GCC && (GCC_VERSION >= 80500) && (GCC_VERSION < 90000) | |
388 | default n | |
389 | ||
6bd1d0be SC |
390 | config KASAN_SHADOW_OFFSET |
391 | hex | |
0fea6e9a | 392 | depends on KASAN_GENERIC || KASAN_SW_TAGS |
f4693c27 AB |
393 | default 0xdfff800000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && !KASAN_SW_TAGS |
394 | default 0xdfffc00000000000 if ARM64_VA_BITS_47 && !KASAN_SW_TAGS | |
395 | default 0xdffffe0000000000 if ARM64_VA_BITS_42 && !KASAN_SW_TAGS | |
396 | default 0xdfffffc000000000 if ARM64_VA_BITS_39 && !KASAN_SW_TAGS | |
397 | default 0xdffffff800000000 if ARM64_VA_BITS_36 && !KASAN_SW_TAGS | |
398 | default 0xefff800000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && KASAN_SW_TAGS | |
399 | default 0xefffc00000000000 if ARM64_VA_BITS_47 && KASAN_SW_TAGS | |
400 | default 0xeffffe0000000000 if ARM64_VA_BITS_42 && KASAN_SW_TAGS | |
401 | default 0xefffffc000000000 if ARM64_VA_BITS_39 && KASAN_SW_TAGS | |
402 | default 0xeffffff800000000 if ARM64_VA_BITS_36 && KASAN_SW_TAGS | |
6bd1d0be SC |
403 | default 0xffffffffffffffff |
404 | ||
68c76ad4 AB |
405 | config UNWIND_TABLES |
406 | bool | |
407 | ||
6a377491 | 408 | source "arch/arm64/Kconfig.platforms" |
8c2c3df3 | 409 | |
8c2c3df3 CM |
410 | menu "Kernel Features" |
411 | ||
c0a01b84 AP |
412 | menu "ARM errata workarounds via the alternatives framework" |
413 | ||
6df696cd OU |
414 | config AMPERE_ERRATUM_AC03_CPU_38 |
415 | bool "AmpereOne: AC03_CPU_38: Certain bits in the Virtualization Translation Control Register and Translation Control Registers do not follow RES0 semantics" | |
416 | default y | |
417 | help | |
418 | This option adds an alternative code sequence to work around Ampere | |
419 | erratum AC03_CPU_38 on AmpereOne. | |
420 | ||
421 | The affected design reports FEAT_HAFDBS as not implemented in | |
422 | ID_AA64MMFR1_EL1.HAFDBS, but (V)TCR_ELx.{HA,HD} are not RES0 | |
423 | as required by the architecture. The unadvertised HAFDBS | |
424 | implementation suffers from an additional erratum where hardware | |
425 | A/D updates can occur after a PTE has been marked invalid. | |
426 | ||
427 | The workaround forces KVM to explicitly set VTCR_EL2.HA to 0, | |
428 | which avoids enabling unadvertised hardware Access Flag management | |
429 | at stage-2. | |
430 | ||
431 | If unsure, say Y. | |
432 | ||
c9460dcb | 433 | config ARM64_WORKAROUND_CLEAN_CACHE |
bc15cf70 | 434 | bool |
c9460dcb | 435 | |
c0a01b84 AP |
436 | config ARM64_ERRATUM_826319 |
437 | bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted" | |
438 | default y | |
c9460dcb | 439 | select ARM64_WORKAROUND_CLEAN_CACHE |
c0a01b84 AP |
440 | help |
441 | This option adds an alternative code sequence to work around ARM | |
442 | erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or | |
443 | AXI master interface and an L2 cache. | |
444 | ||
445 | If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors | |
446 | and is unable to accept a certain write via this interface, it will | |
447 | not progress on read data presented on the read data channel and the | |
448 | system can deadlock. | |
449 | ||
450 | The workaround promotes data cache clean instructions to | |
451 | data cache clean-and-invalidate. | |
452 | Please note that this does not necessarily enable the workaround, | |
453 | as it depends on the alternative framework, which will only patch | |
454 | the kernel if an affected CPU is detected. | |
455 | ||
456 | If unsure, say Y. | |
457 | ||
458 | config ARM64_ERRATUM_827319 | |
459 | bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect" | |
460 | default y | |
c9460dcb | 461 | select ARM64_WORKAROUND_CLEAN_CACHE |
c0a01b84 AP |
462 | help |
463 | This option adds an alternative code sequence to work around ARM | |
464 | erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI | |
465 | master interface and an L2 cache. | |
466 | ||
467 | Under certain conditions this erratum can cause a clean line eviction | |
468 | to occur at the same time as another transaction to the same address | |
469 | on the AMBA 5 CHI interface, which can cause data corruption if the | |
470 | interconnect reorders the two transactions. | |
471 | ||
472 | The workaround promotes data cache clean instructions to | |
473 | data cache clean-and-invalidate. | |
474 | Please note that this does not necessarily enable the workaround, | |
475 | as it depends on the alternative framework, which will only patch | |
476 | the kernel if an affected CPU is detected. | |
477 | ||
478 | If unsure, say Y. | |
479 | ||
480 | config ARM64_ERRATUM_824069 | |
481 | bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop" | |
482 | default y | |
c9460dcb | 483 | select ARM64_WORKAROUND_CLEAN_CACHE |
c0a01b84 AP |
484 | help |
485 | This option adds an alternative code sequence to work around ARM | |
486 | erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected | |
487 | to a coherent interconnect. | |
488 | ||
489 | If a Cortex-A53 processor is executing a store or prefetch for | |
490 | write instruction at the same time as a processor in another | |
491 | cluster is executing a cache maintenance operation to the same | |
492 | address, then this erratum might cause a clean cache line to be | |
493 | incorrectly marked as dirty. | |
494 | ||
495 | The workaround promotes data cache clean instructions to | |
496 | data cache clean-and-invalidate. | |
497 | Please note that this option does not necessarily enable the | |
498 | workaround, as it depends on the alternative framework, which will | |
499 | only patch the kernel if an affected CPU is detected. | |
500 | ||
501 | If unsure, say Y. | |
502 | ||
503 | config ARM64_ERRATUM_819472 | |
504 | bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption" | |
505 | default y | |
c9460dcb | 506 | select ARM64_WORKAROUND_CLEAN_CACHE |
c0a01b84 AP |
507 | help |
508 | This option adds an alternative code sequence to work around ARM | |
509 | erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache | |
510 | present when it is connected to a coherent interconnect. | |
511 | ||
512 | If the processor is executing a load and store exclusive sequence at | |
513 | the same time as a processor in another cluster is executing a cache | |
514 | maintenance operation to the same address, then this erratum might | |
515 | cause data corruption. | |
516 | ||
517 | The workaround promotes data cache clean instructions to | |
518 | data cache clean-and-invalidate. | |
519 | Please note that this does not necessarily enable the workaround, | |
520 | as it depends on the alternative framework, which will only patch | |
521 | the kernel if an affected CPU is detected. | |
522 | ||
523 | If unsure, say Y. | |
524 | ||
525 | config ARM64_ERRATUM_832075 | |
526 | bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads" | |
527 | default y | |
528 | help | |
529 | This option adds an alternative code sequence to work around ARM | |
530 | erratum 832075 on Cortex-A57 parts up to r1p2. | |
531 | ||
532 | Affected Cortex-A57 parts might deadlock when exclusive load/store | |
533 | instructions to Write-Back memory are mixed with Device loads. | |
534 | ||
535 | The workaround is to promote device loads to use Load-Acquire | |
536 | semantics. | |
537 | Please note that this does not necessarily enable the workaround, | |
498cd5c3 MZ |
538 | as it depends on the alternative framework, which will only patch |
539 | the kernel if an affected CPU is detected. | |
540 | ||
541 | If unsure, say Y. | |
542 | ||
543 | config ARM64_ERRATUM_834220 | |
544 | bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault" | |
545 | depends on KVM | |
546 | default y | |
547 | help | |
548 | This option adds an alternative code sequence to work around ARM | |
549 | erratum 834220 on Cortex-A57 parts up to r1p2. | |
550 | ||
551 | Affected Cortex-A57 parts might report a Stage 2 translation | |
552 | fault as the result of a Stage 1 fault for load crossing a | |
553 | page boundary when there is a permission or device memory | |
554 | alignment fault at Stage 1 and a translation fault at Stage 2. | |
555 | ||
556 | The workaround is to verify that the Stage 1 translation | |
557 | doesn't generate a fault before handling the Stage 2 fault. | |
558 | Please note that this does not necessarily enable the workaround, | |
c0a01b84 AP |
559 | as it depends on the alternative framework, which will only patch |
560 | the kernel if an affected CPU is detected. | |
561 | ||
562 | If unsure, say Y. | |
563 | ||
44b3834b JM |
564 | config ARM64_ERRATUM_1742098 |
565 | bool "Cortex-A57/A72: 1742098: ELR recorded incorrectly on interrupt taken between cryptographic instructions in a sequence" | |
566 | depends on COMPAT | |
567 | default y | |
568 | help | |
569 | This option removes the AES hwcap for aarch32 user-space to | |
570 | workaround erratum 1742098 on Cortex-A57 and Cortex-A72. | |
571 | ||
572 | Affected parts may corrupt the AES state if an interrupt is | |
573 | taken between a pair of AES instructions. These instructions | |
574 | are only present if the cryptography extensions are present. | |
575 | All software should have a fallback implementation for CPUs | |
576 | that don't implement the cryptography extensions. | |
577 | ||
578 | If unsure, say Y. | |
579 | ||
905e8c5d WD |
580 | config ARM64_ERRATUM_845719 |
581 | bool "Cortex-A53: 845719: a load might read incorrect data" | |
582 | depends on COMPAT | |
583 | default y | |
584 | help | |
585 | This option adds an alternative code sequence to work around ARM | |
586 | erratum 845719 on Cortex-A53 parts up to r0p4. | |
587 | ||
588 | When running a compat (AArch32) userspace on an affected Cortex-A53 | |
589 | part, a load at EL0 from a virtual address that matches the bottom 32 | |
590 | bits of the virtual address used by a recent load at (AArch64) EL1 | |
591 | might return incorrect data. | |
592 | ||
593 | The workaround is to write the contextidr_el1 register on exception | |
594 | return to a 32-bit task. | |
595 | Please note that this does not necessarily enable the workaround, | |
596 | as it depends on the alternative framework, which will only patch | |
597 | the kernel if an affected CPU is detected. | |
598 | ||
599 | If unsure, say Y. | |
600 | ||
df057cc7 WD |
601 | config ARM64_ERRATUM_843419 |
602 | bool "Cortex-A53: 843419: A load or store might access an incorrect address" | |
df057cc7 WD |
603 | default y |
604 | help | |
6ffe9923 | 605 | This option links the kernel with '--fix-cortex-a53-843419' and |
a257e025 AB |
606 | enables PLT support to replace certain ADRP instructions, which can |
607 | cause subsequent memory accesses to use an incorrect address on | |
608 | Cortex-A53 parts up to r0p4. | |
df057cc7 WD |
609 | |
610 | If unsure, say Y. | |
611 | ||
987fdfec MY |
612 | config ARM64_LD_HAS_FIX_ERRATUM_843419 |
613 | def_bool $(ld-option,--fix-cortex-a53-843419) | |
614 | ||
ece1397c SP |
615 | config ARM64_ERRATUM_1024718 |
616 | bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update" | |
617 | default y | |
618 | help | |
bc15cf70 | 619 | This option adds a workaround for ARM Cortex-A55 Erratum 1024718. |
ece1397c | 620 | |
c0b15c25 | 621 | Affected Cortex-A55 cores (all revisions) could cause incorrect |
ece1397c | 622 | update of the hardware dirty bit when the DBM/AP bits are updated |
bc15cf70 | 623 | without a break-before-make. The workaround is to disable the usage |
ece1397c | 624 | of hardware DBM locally on the affected cores. CPUs not affected by |
bc15cf70 | 625 | this erratum will continue to use the feature. |
df057cc7 WD |
626 | |
627 | If unsure, say Y. | |
628 | ||
a5325089 | 629 | config ARM64_ERRATUM_1418040 |
6989303a | 630 | bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result" |
95b861a4 | 631 | default y |
c2b5bba3 | 632 | depends on COMPAT |
95b861a4 | 633 | help |
24cf262d | 634 | This option adds a workaround for ARM Cortex-A76/Neoverse-N1 |
a5325089 | 635 | errata 1188873 and 1418040. |
95b861a4 | 636 | |
a5325089 | 637 | Affected Cortex-A76/Neoverse-N1 cores (r0p0 to r3p1) could |
6989303a MZ |
638 | cause register corruption when accessing the timer registers |
639 | from AArch32 userspace. | |
95b861a4 MZ |
640 | |
641 | If unsure, say Y. | |
642 | ||
02ab1f50 | 643 | config ARM64_WORKAROUND_SPECULATIVE_AT |
e85d68fa SP |
644 | bool |
645 | ||
a457b0f7 | 646 | config ARM64_ERRATUM_1165522 |
02ab1f50 | 647 | bool "Cortex-A76: 1165522: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation" |
a457b0f7 | 648 | default y |
02ab1f50 | 649 | select ARM64_WORKAROUND_SPECULATIVE_AT |
a457b0f7 | 650 | help |
bc15cf70 | 651 | This option adds a workaround for ARM Cortex-A76 erratum 1165522. |
a457b0f7 MZ |
652 | |
653 | Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with | |
654 | corrupted TLBs by speculating an AT instruction during a guest | |
655 | context switch. | |
656 | ||
657 | If unsure, say Y. | |
658 | ||
02ab1f50 AS |
659 | config ARM64_ERRATUM_1319367 |
660 | bool "Cortex-A57/A72: 1319537: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation" | |
661 | default y | |
662 | select ARM64_WORKAROUND_SPECULATIVE_AT | |
663 | help | |
664 | This option adds work arounds for ARM Cortex-A57 erratum 1319537 | |
665 | and A72 erratum 1319367 | |
666 | ||
667 | Cortex-A57 and A72 cores could end-up with corrupted TLBs by | |
668 | speculating an AT instruction during a guest context switch. | |
669 | ||
670 | If unsure, say Y. | |
671 | ||
275fa0ea | 672 | config ARM64_ERRATUM_1530923 |
02ab1f50 | 673 | bool "Cortex-A55: 1530923: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation" |
275fa0ea | 674 | default y |
02ab1f50 | 675 | select ARM64_WORKAROUND_SPECULATIVE_AT |
275fa0ea SP |
676 | help |
677 | This option adds a workaround for ARM Cortex-A55 erratum 1530923. | |
678 | ||
679 | Affected Cortex-A55 cores (r0p0, r0p1, r1p0, r2p0) could end-up with | |
680 | corrupted TLBs by speculating an AT instruction during a guest | |
681 | context switch. | |
682 | ||
683 | If unsure, say Y. | |
a457b0f7 | 684 | |
ebcea694 GU |
685 | config ARM64_WORKAROUND_REPEAT_TLBI |
686 | bool | |
687 | ||
171df580 JM |
688 | config ARM64_ERRATUM_2441007 |
689 | bool "Cortex-A55: Completion of affected memory accesses might not be guaranteed by completion of a TLBI" | |
690 | default y | |
691 | select ARM64_WORKAROUND_REPEAT_TLBI | |
692 | help | |
693 | This option adds a workaround for ARM Cortex-A55 erratum #2441007. | |
694 | ||
695 | Under very rare circumstances, affected Cortex-A55 CPUs | |
696 | may not handle a race between a break-before-make sequence on one | |
697 | CPU, and another CPU accessing the same page. This could allow a | |
698 | store to a page that has been unmapped. | |
699 | ||
700 | Work around this by adding the affected CPUs to the list that needs | |
701 | TLB sequences to be done twice. | |
702 | ||
703 | If unsure, say Y. | |
704 | ||
ce8c80c5 CM |
705 | config ARM64_ERRATUM_1286807 |
706 | bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-after-read ordering violation" | |
707 | default y | |
708 | select ARM64_WORKAROUND_REPEAT_TLBI | |
709 | help | |
bc15cf70 | 710 | This option adds a workaround for ARM Cortex-A76 erratum 1286807. |
ce8c80c5 CM |
711 | |
712 | On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual | |
713 | address for a cacheable mapping of a location is being | |
714 | accessed by a core while another core is remapping the virtual | |
715 | address to a new physical page using the recommended | |
716 | break-before-make sequence, then under very rare circumstances | |
717 | TLBI+DSB completes before a read using the translation being | |
718 | invalidated has been observed by other observers. The | |
719 | workaround repeats the TLBI+DSB operation. | |
720 | ||
969f5ea6 WD |
721 | config ARM64_ERRATUM_1463225 |
722 | bool "Cortex-A76: Software Step might prevent interrupt recognition" | |
723 | default y | |
724 | help | |
725 | This option adds a workaround for Arm Cortex-A76 erratum 1463225. | |
726 | ||
727 | On the affected Cortex-A76 cores (r0p0 to r3p1), software stepping | |
728 | of a system call instruction (SVC) can prevent recognition of | |
729 | subsequent interrupts when software stepping is disabled in the | |
730 | exception handler of the system call and either kernel debugging | |
731 | is enabled or VHE is in use. | |
732 | ||
733 | Work around the erratum by triggering a dummy step exception | |
734 | when handling a system call from a task that is being stepped | |
735 | in a VHE configuration of the kernel. | |
736 | ||
737 | If unsure, say Y. | |
738 | ||
05460849 JM |
739 | config ARM64_ERRATUM_1542419 |
740 | bool "Neoverse-N1: workaround mis-ordering of instruction fetches" | |
741 | default y | |
742 | help | |
743 | This option adds a workaround for ARM Neoverse-N1 erratum | |
744 | 1542419. | |
745 | ||
746 | Affected Neoverse-N1 cores could execute a stale instruction when | |
747 | modified by another CPU. The workaround depends on a firmware | |
748 | counterpart. | |
749 | ||
750 | Workaround the issue by hiding the DIC feature from EL0. This | |
751 | forces user-space to perform cache maintenance. | |
752 | ||
753 | If unsure, say Y. | |
754 | ||
96d389ca RH |
755 | config ARM64_ERRATUM_1508412 |
756 | bool "Cortex-A77: 1508412: workaround deadlock on sequence of NC/Device load and store exclusive or PAR read" | |
757 | default y | |
758 | help | |
759 | This option adds a workaround for Arm Cortex-A77 erratum 1508412. | |
760 | ||
761 | Affected Cortex-A77 cores (r0p0, r1p0) could deadlock on a sequence | |
762 | of a store-exclusive or read of PAR_EL1 and a load with device or | |
763 | non-cacheable memory attributes. The workaround depends on a firmware | |
764 | counterpart. | |
765 | ||
766 | KVM guests must also have the workaround implemented or they can | |
767 | deadlock the system. | |
768 | ||
769 | Work around the issue by inserting DMB SY barriers around PAR_EL1 | |
770 | register reads and warning KVM users. The DMB barrier is sufficient | |
771 | to prevent a speculative PAR_EL1 read. | |
772 | ||
773 | If unsure, say Y. | |
774 | ||
b9d216fc SP |
775 | config ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE |
776 | bool | |
777 | ||
297ae1eb JM |
778 | config ARM64_ERRATUM_2051678 |
779 | bool "Cortex-A510: 2051678: disable Hardware Update of the page table dirty bit" | |
a4b92ceb | 780 | default y |
297ae1eb JM |
781 | help |
782 | This options adds the workaround for ARM Cortex-A510 erratum ARM64_ERRATUM_2051678. | |
0ff74a23 | 783 | Affected Cortex-A510 might not respect the ordering rules for |
297ae1eb JM |
784 | hardware update of the page table's dirty bit. The workaround |
785 | is to not enable the feature on affected CPUs. | |
786 | ||
787 | If unsure, say Y. | |
788 | ||
1dd498e5 JM |
789 | config ARM64_ERRATUM_2077057 |
790 | bool "Cortex-A510: 2077057: workaround software-step corrupting SPSR_EL2" | |
4c11113c | 791 | default y |
1dd498e5 JM |
792 | help |
793 | This option adds the workaround for ARM Cortex-A510 erratum 2077057. | |
794 | Affected Cortex-A510 may corrupt SPSR_EL2 when the a step exception is | |
795 | expected, but a Pointer Authentication trap is taken instead. The | |
796 | erratum causes SPSR_EL1 to be copied to SPSR_EL2, which could allow | |
797 | EL1 to cause a return to EL2 with a guest controlled ELR_EL2. | |
798 | ||
799 | This can only happen when EL2 is stepping EL1. | |
800 | ||
801 | When these conditions occur, the SPSR_EL2 value is unchanged from the | |
802 | previous guest entry, and can be restored from the in-memory copy. | |
803 | ||
804 | If unsure, say Y. | |
805 | ||
1bdb0fbb JM |
806 | config ARM64_ERRATUM_2658417 |
807 | bool "Cortex-A510: 2658417: remove BF16 support due to incorrect result" | |
808 | default y | |
809 | help | |
810 | This option adds the workaround for ARM Cortex-A510 erratum 2658417. | |
811 | Affected Cortex-A510 (r0p0 to r1p1) may produce the wrong result for | |
812 | BFMMLA or VMMLA instructions in rare circumstances when a pair of | |
813 | A510 CPUs are using shared neon hardware. As the sharing is not | |
814 | discoverable by the kernel, hide the BF16 HWCAP to indicate that | |
815 | user-space should not be using these instructions. | |
816 | ||
817 | If unsure, say Y. | |
818 | ||
b9d216fc | 819 | config ARM64_ERRATUM_2119858 |
eb30d838 | 820 | bool "Cortex-A710/X2: 2119858: workaround TRBE overwriting trace data in FILL mode" |
b9d216fc | 821 | default y |
b9d216fc SP |
822 | depends on CORESIGHT_TRBE |
823 | select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE | |
824 | help | |
eb30d838 | 825 | This option adds the workaround for ARM Cortex-A710/X2 erratum 2119858. |
b9d216fc | 826 | |
eb30d838 | 827 | Affected Cortex-A710/X2 cores could overwrite up to 3 cache lines of trace |
b9d216fc SP |
828 | data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in |
829 | the event of a WRAP event. | |
830 | ||
831 | Work around the issue by always making sure we move the TRBPTR_EL1 by | |
832 | 256 bytes before enabling the buffer and filling the first 256 bytes of | |
833 | the buffer with ETM ignore packets upon disabling. | |
834 | ||
835 | If unsure, say Y. | |
836 | ||
837 | config ARM64_ERRATUM_2139208 | |
838 | bool "Neoverse-N2: 2139208: workaround TRBE overwriting trace data in FILL mode" | |
839 | default y | |
b9d216fc SP |
840 | depends on CORESIGHT_TRBE |
841 | select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE | |
842 | help | |
843 | This option adds the workaround for ARM Neoverse-N2 erratum 2139208. | |
844 | ||
845 | Affected Neoverse-N2 cores could overwrite up to 3 cache lines of trace | |
846 | data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in | |
847 | the event of a WRAP event. | |
848 | ||
849 | Work around the issue by always making sure we move the TRBPTR_EL1 by | |
850 | 256 bytes before enabling the buffer and filling the first 256 bytes of | |
851 | the buffer with ETM ignore packets upon disabling. | |
852 | ||
853 | If unsure, say Y. | |
854 | ||
fa82d0b4 SP |
855 | config ARM64_WORKAROUND_TSB_FLUSH_FAILURE |
856 | bool | |
857 | ||
858 | config ARM64_ERRATUM_2054223 | |
859 | bool "Cortex-A710: 2054223: workaround TSB instruction failing to flush trace" | |
860 | default y | |
861 | select ARM64_WORKAROUND_TSB_FLUSH_FAILURE | |
862 | help | |
863 | Enable workaround for ARM Cortex-A710 erratum 2054223 | |
864 | ||
865 | Affected cores may fail to flush the trace data on a TSB instruction, when | |
866 | the PE is in trace prohibited state. This will cause losing a few bytes | |
867 | of the trace cached. | |
868 | ||
869 | Workaround is to issue two TSB consecutively on affected cores. | |
870 | ||
871 | If unsure, say Y. | |
872 | ||
873 | config ARM64_ERRATUM_2067961 | |
874 | bool "Neoverse-N2: 2067961: workaround TSB instruction failing to flush trace" | |
875 | default y | |
876 | select ARM64_WORKAROUND_TSB_FLUSH_FAILURE | |
877 | help | |
878 | Enable workaround for ARM Neoverse-N2 erratum 2067961 | |
879 | ||
880 | Affected cores may fail to flush the trace data on a TSB instruction, when | |
881 | the PE is in trace prohibited state. This will cause losing a few bytes | |
882 | of the trace cached. | |
883 | ||
884 | Workaround is to issue two TSB consecutively on affected cores. | |
885 | ||
886 | If unsure, say Y. | |
887 | ||
8d81b2a3 SP |
888 | config ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE |
889 | bool | |
890 | ||
891 | config ARM64_ERRATUM_2253138 | |
892 | bool "Neoverse-N2: 2253138: workaround TRBE writing to address out-of-range" | |
8d81b2a3 SP |
893 | depends on CORESIGHT_TRBE |
894 | default y | |
895 | select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE | |
896 | help | |
897 | This option adds the workaround for ARM Neoverse-N2 erratum 2253138. | |
898 | ||
899 | Affected Neoverse-N2 cores might write to an out-of-range address, not reserved | |
900 | for TRBE. Under some conditions, the TRBE might generate a write to the next | |
901 | virtually addressed page following the last page of the TRBE address space | |
902 | (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base. | |
903 | ||
904 | Work around this in the driver by always making sure that there is a | |
905 | page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE. | |
906 | ||
907 | If unsure, say Y. | |
908 | ||
909 | config ARM64_ERRATUM_2224489 | |
eb30d838 | 910 | bool "Cortex-A710/X2: 2224489: workaround TRBE writing to address out-of-range" |
8d81b2a3 SP |
911 | depends on CORESIGHT_TRBE |
912 | default y | |
913 | select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE | |
914 | help | |
eb30d838 | 915 | This option adds the workaround for ARM Cortex-A710/X2 erratum 2224489. |
8d81b2a3 | 916 | |
eb30d838 | 917 | Affected Cortex-A710/X2 cores might write to an out-of-range address, not reserved |
8d81b2a3 SP |
918 | for TRBE. Under some conditions, the TRBE might generate a write to the next |
919 | virtually addressed page following the last page of the TRBE address space | |
920 | (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base. | |
921 | ||
922 | Work around this in the driver by always making sure that there is a | |
923 | page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE. | |
924 | ||
925 | If unsure, say Y. | |
926 | ||
39fdb65f JM |
927 | config ARM64_ERRATUM_2441009 |
928 | bool "Cortex-A510: Completion of affected memory accesses might not be guaranteed by completion of a TLBI" | |
929 | default y | |
930 | select ARM64_WORKAROUND_REPEAT_TLBI | |
931 | help | |
932 | This option adds a workaround for ARM Cortex-A510 erratum #2441009. | |
933 | ||
934 | Under very rare circumstances, affected Cortex-A510 CPUs | |
935 | may not handle a race between a break-before-make sequence on one | |
936 | CPU, and another CPU accessing the same page. This could allow a | |
937 | store to a page that has been unmapped. | |
938 | ||
939 | Work around this by adding the affected CPUs to the list that needs | |
940 | TLB sequences to be done twice. | |
941 | ||
942 | If unsure, say Y. | |
943 | ||
607a9afa AK |
944 | config ARM64_ERRATUM_2064142 |
945 | bool "Cortex-A510: 2064142: workaround TRBE register writes while disabled" | |
ac0ba210 | 946 | depends on CORESIGHT_TRBE |
607a9afa AK |
947 | default y |
948 | help | |
949 | This option adds the workaround for ARM Cortex-A510 erratum 2064142. | |
950 | ||
951 | Affected Cortex-A510 core might fail to write into system registers after the | |
952 | TRBE has been disabled. Under some conditions after the TRBE has been disabled | |
953 | writes into TRBE registers TRBLIMITR_EL1, TRBPTR_EL1, TRBBASER_EL1, TRBSR_EL1, | |
954 | and TRBTRG_EL1 will be ignored and will not be effected. | |
955 | ||
956 | Work around this in the driver by executing TSB CSYNC and DSB after collection | |
957 | is stopped and before performing a system register write to one of the affected | |
958 | registers. | |
959 | ||
960 | If unsure, say Y. | |
961 | ||
3bd94a87 AK |
962 | config ARM64_ERRATUM_2038923 |
963 | bool "Cortex-A510: 2038923: workaround TRBE corruption with enable" | |
f209e9fe | 964 | depends on CORESIGHT_TRBE |
3bd94a87 AK |
965 | default y |
966 | help | |
967 | This option adds the workaround for ARM Cortex-A510 erratum 2038923. | |
968 | ||
969 | Affected Cortex-A510 core might cause an inconsistent view on whether trace is | |
970 | prohibited within the CPU. As a result, the trace buffer or trace buffer state | |
971 | might be corrupted. This happens after TRBE buffer has been enabled by setting | |
972 | TRBLIMITR_EL1.E, followed by just a single context synchronization event before | |
973 | execution changes from a context, in which trace is prohibited to one where it | |
974 | isn't, or vice versa. In these mentioned conditions, the view of whether trace | |
975 | is prohibited is inconsistent between parts of the CPU, and the trace buffer or | |
976 | the trace buffer state might be corrupted. | |
977 | ||
978 | Work around this in the driver by preventing an inconsistent view of whether the | |
979 | trace is prohibited or not based on TRBLIMITR_EL1.E by immediately following a | |
980 | change to TRBLIMITR_EL1.E with at least one ISB instruction before an ERET, or | |
981 | two ISB instructions if no ERET is to take place. | |
982 | ||
983 | If unsure, say Y. | |
984 | ||
708e8af4 AK |
985 | config ARM64_ERRATUM_1902691 |
986 | bool "Cortex-A510: 1902691: workaround TRBE trace corruption" | |
3a828845 | 987 | depends on CORESIGHT_TRBE |
708e8af4 AK |
988 | default y |
989 | help | |
990 | This option adds the workaround for ARM Cortex-A510 erratum 1902691. | |
991 | ||
992 | Affected Cortex-A510 core might cause trace data corruption, when being written | |
993 | into the memory. Effectively TRBE is broken and hence cannot be used to capture | |
994 | trace data. | |
995 | ||
996 | Work around this problem in the driver by just preventing TRBE initialization on | |
997 | affected cpus. The firmware must have disabled the access to TRBE for the kernel | |
998 | on such implementations. This will cover the kernel for any firmware that doesn't | |
999 | do this already. | |
1000 | ||
1001 | If unsure, say Y. | |
1002 | ||
e89d120c IV |
1003 | config ARM64_ERRATUM_2457168 |
1004 | bool "Cortex-A510: 2457168: workaround for AMEVCNTR01 incrementing incorrectly" | |
1005 | depends on ARM64_AMU_EXTN | |
1006 | default y | |
1007 | help | |
1008 | This option adds the workaround for ARM Cortex-A510 erratum 2457168. | |
1009 | ||
1010 | The AMU counter AMEVCNTR01 (constant counter) should increment at the same rate | |
1011 | as the system counter. On affected Cortex-A510 cores AMEVCNTR01 increments | |
1012 | incorrectly giving a significantly higher output value. | |
1013 | ||
1014 | Work around this problem by returning 0 when reading the affected counter in | |
1015 | key locations that results in disabling all users of this counter. This effect | |
1016 | is the same to firmware disabling affected counters. | |
1017 | ||
1018 | If unsure, say Y. | |
1019 | ||
5db568e7 AK |
1020 | config ARM64_ERRATUM_2645198 |
1021 | bool "Cortex-A715: 2645198: Workaround possible [ESR|FAR]_ELx corruption" | |
1022 | default y | |
1023 | help | |
1024 | This option adds the workaround for ARM Cortex-A715 erratum 2645198. | |
1025 | ||
1026 | If a Cortex-A715 cpu sees a page mapping permissions change from executable | |
1027 | to non-executable, it may corrupt the ESR_ELx and FAR_ELx registers on the | |
1028 | next instruction abort caused by permission fault. | |
1029 | ||
1030 | Only user-space does executable to non-executable permission transition via | |
1031 | mprotect() system call. Workaround the problem by doing a break-before-make | |
1032 | TLB invalidation, for all changes to executable user space mappings. | |
1033 | ||
1034 | If unsure, say Y. | |
1035 | ||
546b7cde RH |
1036 | config ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD |
1037 | bool | |
1038 | ||
471470bc RH |
1039 | config ARM64_ERRATUM_2966298 |
1040 | bool "Cortex-A520: 2966298: workaround for speculatively executed unprivileged load" | |
546b7cde | 1041 | select ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD |
471470bc RH |
1042 | default y |
1043 | help | |
1044 | This option adds the workaround for ARM Cortex-A520 erratum 2966298. | |
1045 | ||
1046 | On an affected Cortex-A520 core, a speculatively executed unprivileged | |
1047 | load might leak data from a privileged level via a cache side channel. | |
1048 | ||
1049 | Work around this problem by executing a TLBI before returning to EL0. | |
1050 | ||
1051 | If unsure, say Y. | |
1052 | ||
f827bcda RH |
1053 | config ARM64_ERRATUM_3117295 |
1054 | bool "Cortex-A510: 3117295: workaround for speculatively executed unprivileged load" | |
1055 | select ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD | |
1056 | default y | |
1057 | help | |
1058 | This option adds the workaround for ARM Cortex-A510 erratum 3117295. | |
1059 | ||
1060 | On an affected Cortex-A510 core, a speculatively executed unprivileged | |
1061 | load might leak data from a privileged level via a cache side channel. | |
1062 | ||
1063 | Work around this problem by executing a TLBI before returning to EL0. | |
1064 | ||
1065 | If unsure, say Y. | |
1066 | ||
94100970 RR |
1067 | config CAVIUM_ERRATUM_22375 |
1068 | bool "Cavium erratum 22375, 24313" | |
1069 | default y | |
1070 | help | |
bc15cf70 | 1071 | Enable workaround for errata 22375 and 24313. |
94100970 RR |
1072 | |
1073 | This implements two gicv3-its errata workarounds for ThunderX. Both | |
bc15cf70 | 1074 | with a small impact affecting only ITS table allocation. |
94100970 RR |
1075 | |
1076 | erratum 22375: only alloc 8MB table size | |
1077 | erratum 24313: ignore memory access type | |
1078 | ||
1079 | The fixes are in ITS initialization and basically ignore memory access | |
1080 | type and table size provided by the TYPER and BASER registers. | |
1081 | ||
1082 | If unsure, say Y. | |
1083 | ||
fbf8f40e GK |
1084 | config CAVIUM_ERRATUM_23144 |
1085 | bool "Cavium erratum 23144: ITS SYNC hang on dual socket system" | |
1086 | depends on NUMA | |
1087 | default y | |
1088 | help | |
1089 | ITS SYNC command hang for cross node io and collections/cpu mapping. | |
1090 | ||
1091 | If unsure, say Y. | |
1092 | ||
6d4e11c5 | 1093 | config CAVIUM_ERRATUM_23154 |
24a147bc | 1094 | bool "Cavium errata 23154 and 38545: GICv3 lacks HW synchronisation" |
6d4e11c5 RR |
1095 | default y |
1096 | help | |
24a147bc | 1097 | The ThunderX GICv3 implementation requires a modified version for |
6d4e11c5 RR |
1098 | reading the IAR status to ensure data synchronization |
1099 | (access to icc_iar1_el1 is not sync'ed before and after). | |
1100 | ||
24a147bc LC |
1101 | It also suffers from erratum 38545 (also present on Marvell's |
1102 | OcteonTX and OcteonTX2), resulting in deactivated interrupts being | |
1103 | spuriously presented to the CPU interface. | |
1104 | ||
6d4e11c5 RR |
1105 | If unsure, say Y. |
1106 | ||
104a0c02 AP |
1107 | config CAVIUM_ERRATUM_27456 |
1108 | bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption" | |
1109 | default y | |
1110 | help | |
1111 | On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI | |
1112 | instructions may cause the icache to become corrupted if it | |
1113 | contains data for a non-current ASID. The fix is to | |
1114 | invalidate the icache when changing the mm context. | |
1115 | ||
1116 | If unsure, say Y. | |
1117 | ||
690a3415 DD |
1118 | config CAVIUM_ERRATUM_30115 |
1119 | bool "Cavium erratum 30115: Guest may disable interrupts in host" | |
1120 | default y | |
1121 | help | |
1122 | On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through | |
1123 | 1.2, and T83 Pass 1.0, KVM guest execution may disable | |
1124 | interrupts in host. Trapping both GICv3 group-0 and group-1 | |
1125 | accesses sidesteps the issue. | |
1126 | ||
1127 | If unsure, say Y. | |
1128 | ||
603afdc9 MZ |
1129 | config CAVIUM_TX2_ERRATUM_219 |
1130 | bool "Cavium ThunderX2 erratum 219: PRFM between TTBR change and ISB fails" | |
1131 | default y | |
1132 | help | |
1133 | On Cavium ThunderX2, a load, store or prefetch instruction between a | |
1134 | TTBR update and the corresponding context synchronizing operation can | |
1135 | cause a spurious Data Abort to be delivered to any hardware thread in | |
1136 | the CPU core. | |
1137 | ||
1138 | Work around the issue by avoiding the problematic code sequence and | |
1139 | trapping KVM guest TTBRx_EL1 writes to EL2 when SMT is enabled. The | |
1140 | trap handler performs the corresponding register access, skips the | |
1141 | instruction and ensures context synchronization by virtue of the | |
1142 | exception return. | |
1143 | ||
1144 | If unsure, say Y. | |
1145 | ||
ebcea694 GU |
1146 | config FUJITSU_ERRATUM_010001 |
1147 | bool "Fujitsu-A64FX erratum E#010001: Undefined fault may occur wrongly" | |
1148 | default y | |
1149 | help | |
1150 | This option adds a workaround for Fujitsu-A64FX erratum E#010001. | |
1151 | On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1), memory | |
1152 | accesses may cause undefined fault (Data abort, DFSC=0b111111). | |
1153 | This fault occurs under a specific hardware condition when a | |
1154 | load/store instruction performs an address translation using: | |
1155 | case-1 TTBR0_EL1 with TCR_EL1.NFD0 == 1. | |
1156 | case-2 TTBR0_EL2 with TCR_EL2.NFD0 == 1. | |
1157 | case-3 TTBR1_EL1 with TCR_EL1.NFD1 == 1. | |
1158 | case-4 TTBR1_EL2 with TCR_EL2.NFD1 == 1. | |
1159 | ||
1160 | The workaround is to ensure these bits are clear in TCR_ELx. | |
1161 | The workaround only affects the Fujitsu-A64FX. | |
1162 | ||
1163 | If unsure, say Y. | |
1164 | ||
1165 | config HISILICON_ERRATUM_161600802 | |
1166 | bool "Hip07 161600802: Erroneous redistributor VLPI base" | |
1167 | default y | |
1168 | help | |
1169 | The HiSilicon Hip07 SoC uses the wrong redistributor base | |
1170 | when issued ITS commands such as VMOVP and VMAPP, and requires | |
1171 | a 128kB offset to be applied to the target address in this commands. | |
1172 | ||
1173 | If unsure, say Y. | |
1174 | ||
38fd94b0 CC |
1175 | config QCOM_FALKOR_ERRATUM_1003 |
1176 | bool "Falkor E1003: Incorrect translation due to ASID change" | |
1177 | default y | |
38fd94b0 CC |
1178 | help |
1179 | On Falkor v1, an incorrect ASID may be cached in the TLB when ASID | |
d1777e68 WD |
1180 | and BADDR are changed together in TTBRx_EL1. Since we keep the ASID |
1181 | in TTBR1_EL1, this situation only occurs in the entry trampoline and | |
1182 | then only for entries in the walk cache, since the leaf translation | |
1183 | is unchanged. Work around the erratum by invalidating the walk cache | |
1184 | entries for the trampoline before entering the kernel proper. | |
38fd94b0 | 1185 | |
d9ff80f8 CC |
1186 | config QCOM_FALKOR_ERRATUM_1009 |
1187 | bool "Falkor E1009: Prematurely complete a DSB after a TLBI" | |
1188 | default y | |
ce8c80c5 | 1189 | select ARM64_WORKAROUND_REPEAT_TLBI |
d9ff80f8 CC |
1190 | help |
1191 | On Falkor v1, the CPU may prematurely complete a DSB following a | |
1192 | TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation | |
1193 | one more time to fix the issue. | |
1194 | ||
1195 | If unsure, say Y. | |
1196 | ||
90922a2d SD |
1197 | config QCOM_QDF2400_ERRATUM_0065 |
1198 | bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size" | |
1199 | default y | |
1200 | help | |
1201 | On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports | |
1202 | ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have | |
1203 | been indicated as 16Bytes (0xf), not 8Bytes (0x7). | |
1204 | ||
1205 | If unsure, say Y. | |
1206 | ||
932b50c7 SD |
1207 | config QCOM_FALKOR_ERRATUM_E1041 |
1208 | bool "Falkor E1041: Speculative instruction fetches might cause errant memory access" | |
1209 | default y | |
1210 | help | |
1211 | Falkor CPU may speculatively fetch instructions from an improper | |
1212 | memory location when MMU translation is changed from SCTLR_ELn[M]=1 | |
1213 | to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem. | |
1214 | ||
1215 | If unsure, say Y. | |
1216 | ||
20109a85 RW |
1217 | config NVIDIA_CARMEL_CNP_ERRATUM |
1218 | bool "NVIDIA Carmel CNP: CNP on Carmel semantically different than ARM cores" | |
1219 | default y | |
1220 | help | |
1221 | If CNP is enabled on Carmel cores, non-sharable TLBIs on a core will not | |
1222 | invalidate shared TLB entries installed by a different core, as it would | |
1223 | on standard ARM cores. | |
1224 | ||
1225 | If unsure, say Y. | |
1226 | ||
a8707f55 SR |
1227 | config ROCKCHIP_ERRATUM_3588001 |
1228 | bool "Rockchip 3588001: GIC600 can not support shareability attributes" | |
1229 | default y | |
1230 | help | |
1231 | The Rockchip RK3588 GIC600 SoC integration does not support ACE/ACE-lite. | |
1232 | This means, that its sharability feature may not be used, even though it | |
1233 | is supported by the IP itself. | |
1234 | ||
1235 | If unsure, say Y. | |
1236 | ||
ebcea694 GU |
1237 | config SOCIONEXT_SYNQUACER_PREITS |
1238 | bool "Socionext Synquacer: Workaround for GICv3 pre-ITS" | |
3e32131a ZL |
1239 | default y |
1240 | help | |
ebcea694 GU |
1241 | Socionext Synquacer SoCs implement a separate h/w block to generate |
1242 | MSI doorbell writes with non-zero values for the device ID. | |
3e32131a ZL |
1243 | |
1244 | If unsure, say Y. | |
1245 | ||
3cb7e662 | 1246 | endmenu # "ARM errata workarounds via the alternatives framework" |
c0a01b84 | 1247 | |
e41ceed0 JL |
1248 | choice |
1249 | prompt "Page size" | |
1250 | default ARM64_4K_PAGES | |
1251 | help | |
1252 | Page size (translation granule) configuration. | |
1253 | ||
1254 | config ARM64_4K_PAGES | |
1255 | bool "4KB" | |
d3e5bab9 | 1256 | select HAVE_PAGE_SIZE_4KB |
e41ceed0 JL |
1257 | help |
1258 | This feature enables 4KB pages support. | |
1259 | ||
44eaacf1 SP |
1260 | config ARM64_16K_PAGES |
1261 | bool "16KB" | |
d3e5bab9 | 1262 | select HAVE_PAGE_SIZE_16KB |
44eaacf1 SP |
1263 | help |
1264 | The system will use 16KB pages support. AArch32 emulation | |
1265 | requires applications compiled with 16K (or a multiple of 16K) | |
1266 | aligned segments. | |
1267 | ||
8c2c3df3 | 1268 | config ARM64_64K_PAGES |
e41ceed0 | 1269 | bool "64KB" |
d3e5bab9 | 1270 | select HAVE_PAGE_SIZE_64KB |
8c2c3df3 CM |
1271 | help |
1272 | This feature enables 64KB pages support (4KB by default) | |
1273 | allowing only two levels of page tables and faster TLB | |
db488be3 SP |
1274 | look-up. AArch32 emulation requires applications compiled |
1275 | with 64K aligned segments. | |
8c2c3df3 | 1276 | |
e41ceed0 JL |
1277 | endchoice |
1278 | ||
1279 | choice | |
1280 | prompt "Virtual address space size" | |
1281 | default ARM64_VA_BITS_39 if ARM64_4K_PAGES | |
44eaacf1 | 1282 | default ARM64_VA_BITS_47 if ARM64_16K_PAGES |
e41ceed0 JL |
1283 | default ARM64_VA_BITS_42 if ARM64_64K_PAGES |
1284 | help | |
1285 | Allows choosing one of multiple possible virtual address | |
1286 | space sizes. The level of translation table is determined by | |
1287 | a combination of page size and virtual address space size. | |
1288 | ||
21539939 | 1289 | config ARM64_VA_BITS_36 |
56a3f30e | 1290 | bool "36-bit" if EXPERT |
d3e5bab9 | 1291 | depends on PAGE_SIZE_16KB |
21539939 | 1292 | |
e41ceed0 JL |
1293 | config ARM64_VA_BITS_39 |
1294 | bool "39-bit" | |
d3e5bab9 | 1295 | depends on PAGE_SIZE_4KB |
e41ceed0 JL |
1296 | |
1297 | config ARM64_VA_BITS_42 | |
1298 | bool "42-bit" | |
d3e5bab9 | 1299 | depends on PAGE_SIZE_64KB |
e41ceed0 | 1300 | |
44eaacf1 SP |
1301 | config ARM64_VA_BITS_47 |
1302 | bool "47-bit" | |
d3e5bab9 | 1303 | depends on PAGE_SIZE_16KB |
44eaacf1 | 1304 | |
c79b954b JL |
1305 | config ARM64_VA_BITS_48 |
1306 | bool "48-bit" | |
c79b954b | 1307 | |
b6d00d47 SC |
1308 | config ARM64_VA_BITS_52 |
1309 | bool "52-bit" | |
68d23da4 WD |
1310 | depends on ARM64_64K_PAGES && (ARM64_PAN || !ARM64_SW_TTBR0_PAN) |
1311 | help | |
1312 | Enable 52-bit virtual addressing for userspace when explicitly | |
b6d00d47 SC |
1313 | requested via a hint to mmap(). The kernel will also use 52-bit |
1314 | virtual addresses for its own mappings (provided HW support for | |
1315 | this feature is available, otherwise it reverts to 48-bit). | |
68d23da4 WD |
1316 | |
1317 | NOTE: Enabling 52-bit virtual addressing in conjunction with | |
1318 | ARMv8.3 Pointer Authentication will result in the PAC being | |
1319 | reduced from 7 bits to 3 bits, which may have a significant | |
1320 | impact on its susceptibility to brute-force attacks. | |
1321 | ||
1322 | If unsure, select 48-bit virtual addressing instead. | |
1323 | ||
e41ceed0 JL |
1324 | endchoice |
1325 | ||
68d23da4 WD |
1326 | config ARM64_FORCE_52BIT |
1327 | bool "Force 52-bit virtual addresses for userspace" | |
b6d00d47 | 1328 | depends on ARM64_VA_BITS_52 && EXPERT |
68d23da4 WD |
1329 | help |
1330 | For systems with 52-bit userspace VAs enabled, the kernel will attempt | |
1331 | to maintain compatibility with older software by providing 48-bit VAs | |
1332 | unless a hint is supplied to mmap. | |
1333 | ||
1334 | This configuration option disables the 48-bit compatibility logic, and | |
1335 | forces all userspace addresses to be 52-bit on HW that supports it. One | |
1336 | should only enable this configuration option for stress testing userspace | |
1337 | memory management code. If unsure say N here. | |
1338 | ||
e41ceed0 JL |
1339 | config ARM64_VA_BITS |
1340 | int | |
21539939 | 1341 | default 36 if ARM64_VA_BITS_36 |
e41ceed0 JL |
1342 | default 39 if ARM64_VA_BITS_39 |
1343 | default 42 if ARM64_VA_BITS_42 | |
44eaacf1 | 1344 | default 47 if ARM64_VA_BITS_47 |
b6d00d47 SC |
1345 | default 48 if ARM64_VA_BITS_48 |
1346 | default 52 if ARM64_VA_BITS_52 | |
e41ceed0 | 1347 | |
982aa7c5 KM |
1348 | choice |
1349 | prompt "Physical address space size" | |
1350 | default ARM64_PA_BITS_48 | |
1351 | help | |
1352 | Choose the maximum physical address range that the kernel will | |
1353 | support. | |
1354 | ||
1355 | config ARM64_PA_BITS_48 | |
1356 | bool "48-bit" | |
1357 | ||
f77d2817 KM |
1358 | config ARM64_PA_BITS_52 |
1359 | bool "52-bit (ARMv8.2)" | |
1360 | depends on ARM64_64K_PAGES | |
1361 | depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN | |
1362 | help | |
1363 | Enable support for a 52-bit physical address space, introduced as | |
1364 | part of the ARMv8.2-LPA extension. | |
1365 | ||
1366 | With this enabled, the kernel will also continue to work on CPUs that | |
1367 | do not support ARMv8.2-LPA, but with some added memory overhead (and | |
1368 | minor performance overhead). | |
1369 | ||
982aa7c5 KM |
1370 | endchoice |
1371 | ||
1372 | config ARM64_PA_BITS | |
1373 | int | |
1374 | default 48 if ARM64_PA_BITS_48 | |
f77d2817 | 1375 | default 52 if ARM64_PA_BITS_52 |
982aa7c5 | 1376 | |
d8e85e14 AR |
1377 | choice |
1378 | prompt "Endianness" | |
1379 | default CPU_LITTLE_ENDIAN | |
1380 | help | |
1381 | Select the endianness of data accesses performed by the CPU. Userspace | |
1382 | applications will need to be compiled and linked for the endianness | |
1383 | that is selected here. | |
1384 | ||
a872013d | 1385 | config CPU_BIG_ENDIAN |
e9c6deee NC |
1386 | bool "Build big-endian kernel" |
1387 | depends on !LD_IS_LLD || LLD_VERSION >= 130000 | |
146a15b8 NC |
1388 | # https://github.com/llvm/llvm-project/commit/1379b150991f70a5782e9a143c2ba5308da1161c |
1389 | depends on AS_IS_GNU || AS_VERSION >= 150000 | |
e9c6deee | 1390 | help |
d8e85e14 AR |
1391 | Say Y if you plan on running a kernel with a big-endian userspace. |
1392 | ||
1393 | config CPU_LITTLE_ENDIAN | |
1394 | bool "Build little-endian kernel" | |
1395 | help | |
1396 | Say Y if you plan on running a kernel with a little-endian userspace. | |
1397 | This is usually the case for distributions targeting arm64. | |
1398 | ||
1399 | endchoice | |
a872013d | 1400 | |
f6e763b9 MB |
1401 | config SCHED_MC |
1402 | bool "Multi-core scheduler support" | |
f6e763b9 MB |
1403 | help |
1404 | Multi-core scheduler support improves the CPU scheduler's decision | |
1405 | making when dealing with multi-core CPU chips at a cost of slightly | |
1406 | increased overhead in some places. If unsure say N here. | |
1407 | ||
778c558f BS |
1408 | config SCHED_CLUSTER |
1409 | bool "Cluster scheduler support" | |
1410 | help | |
1411 | Cluster scheduler support improves the CPU scheduler's decision | |
1412 | making when dealing with machines that have clusters of CPUs. | |
1413 | Cluster usually means a couple of CPUs which are placed closely | |
1414 | by sharing mid-level caches, last-level cache tags or internal | |
1415 | busses. | |
1416 | ||
f6e763b9 MB |
1417 | config SCHED_SMT |
1418 | bool "SMT scheduler support" | |
f6e763b9 MB |
1419 | help |
1420 | Improves the CPU scheduler's decision making when dealing with | |
1421 | MultiThreading at a cost of slightly increased overhead in some | |
1422 | places. If unsure say N here. | |
1423 | ||
8c2c3df3 | 1424 | config NR_CPUS |
62aa9655 GK |
1425 | int "Maximum number of CPUs (2-4096)" |
1426 | range 2 4096 | |
846a415b | 1427 | default "256" |
8c2c3df3 | 1428 | |
9327e2c6 MR |
1429 | config HOTPLUG_CPU |
1430 | bool "Support for hot-pluggable CPUs" | |
217d453d | 1431 | select GENERIC_IRQ_MIGRATION |
9327e2c6 MR |
1432 | help |
1433 | Say Y here to experiment with turning CPUs off and on. CPUs | |
1434 | can be controlled through /sys/devices/system/cpu. | |
1435 | ||
1a2db300 GK |
1436 | # Common NUMA Features |
1437 | config NUMA | |
4399e6cd | 1438 | bool "NUMA Memory Allocation and Scheduler Support" |
ae3c107c | 1439 | select GENERIC_ARCH_NUMA |
0c2a6cce KW |
1440 | select ACPI_NUMA if ACPI |
1441 | select OF_NUMA | |
7ecd19cf KW |
1442 | select HAVE_SETUP_PER_CPU_AREA |
1443 | select NEED_PER_CPU_EMBED_FIRST_CHUNK | |
1444 | select NEED_PER_CPU_PAGE_FIRST_CHUNK | |
1445 | select USE_PERCPU_NUMA_NODE_ID | |
1a2db300 | 1446 | help |
4399e6cd | 1447 | Enable NUMA (Non-Uniform Memory Access) support. |
1a2db300 GK |
1448 | |
1449 | The kernel will try to allocate memory used by a CPU on the | |
1450 | local memory of the CPU and add some more | |
1451 | NUMA awareness to the kernel. | |
1452 | ||
1453 | config NODES_SHIFT | |
1454 | int "Maximum NUMA Nodes (as a power of 2)" | |
1455 | range 1 10 | |
2a13c13b | 1456 | default "4" |
a9ee6cf5 | 1457 | depends on NUMA |
1a2db300 GK |
1458 | help |
1459 | Specify the maximum number of NUMA Nodes available on the target | |
1460 | system. Increases memory reserved to accommodate various tables. | |
1461 | ||
8636a1f9 | 1462 | source "kernel/Kconfig.hz" |
8c2c3df3 | 1463 | |
8c2c3df3 CM |
1464 | config ARCH_SPARSEMEM_ENABLE |
1465 | def_bool y | |
1466 | select SPARSEMEM_VMEMMAP_ENABLE | |
782276b4 | 1467 | select SPARSEMEM_VMEMMAP |
e7d4bac4 | 1468 | |
8c2c3df3 | 1469 | config HW_PERF_EVENTS |
6475b2d8 MR |
1470 | def_bool y |
1471 | depends on ARM_PMU | |
8c2c3df3 | 1472 | |
afcf5441 | 1473 | # Supported by clang >= 7.0 or GCC >= 12.0.0 |
5287569a ST |
1474 | config CC_HAVE_SHADOW_CALL_STACK |
1475 | def_bool $(cc-option, -fsanitize=shadow-call-stack -ffixed-x18) | |
1476 | ||
dfd57bc3 SS |
1477 | config PARAVIRT |
1478 | bool "Enable paravirtualization code" | |
1479 | help | |
1480 | This changes the kernel so it can modify itself when it is run | |
1481 | under a hypervisor, potentially improving performance significantly | |
1482 | over full virtualization. | |
1483 | ||
1484 | config PARAVIRT_TIME_ACCOUNTING | |
1485 | bool "Paravirtual steal time accounting" | |
1486 | select PARAVIRT | |
dfd57bc3 SS |
1487 | help |
1488 | Select this option to enable fine granularity task steal time | |
1489 | accounting. Time spent executing other tasks in parallel with | |
1490 | the current vCPU is discounted from the vCPU power. To account for | |
1491 | that, there can be a small performance impact. | |
1492 | ||
1493 | If in doubt, say N here. | |
1494 | ||
91506f7e ED |
1495 | config ARCH_SUPPORTS_KEXEC |
1496 | def_bool PM_SLEEP_SMP | |
3ddd9992 | 1497 | |
91506f7e ED |
1498 | config ARCH_SUPPORTS_KEXEC_FILE |
1499 | def_bool y | |
732b7b93 | 1500 | |
91506f7e ED |
1501 | config ARCH_SELECTS_KEXEC_FILE |
1502 | def_bool y | |
1503 | depends on KEXEC_FILE | |
1504 | select HAVE_IMA_KEXEC if IMA | |
732b7b93 | 1505 | |
91506f7e ED |
1506 | config ARCH_SUPPORTS_KEXEC_SIG |
1507 | def_bool y | |
732b7b93 | 1508 | |
91506f7e ED |
1509 | config ARCH_SUPPORTS_KEXEC_IMAGE_VERIFY_SIG |
1510 | def_bool y | |
732b7b93 | 1511 | |
91506f7e ED |
1512 | config ARCH_DEFAULT_KEXEC_IMAGE_VERIFY_SIG |
1513 | def_bool y | |
e62aaeac | 1514 | |
91506f7e ED |
1515 | config ARCH_SUPPORTS_CRASH_DUMP |
1516 | def_bool y | |
e62aaeac | 1517 | |
fdc26823 BH |
1518 | config ARCH_HAS_GENERIC_CRASHKERNEL_RESERVATION |
1519 | def_bool CRASH_CORE | |
1520 | ||
072e3d96 PT |
1521 | config TRANS_TABLE |
1522 | def_bool y | |
08eae0ef | 1523 | depends on HIBERNATION || KEXEC_CORE |
072e3d96 | 1524 | |
aa42aa13 SS |
1525 | config XEN_DOM0 |
1526 | def_bool y | |
1527 | depends on XEN | |
1528 | ||
1529 | config XEN | |
c2ba1f7d | 1530 | bool "Xen guest support on ARM64" |
aa42aa13 | 1531 | depends on ARM64 && OF |
83862ccf | 1532 | select SWIOTLB_XEN |
dfd57bc3 | 1533 | select PARAVIRT |
aa42aa13 SS |
1534 | help |
1535 | Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64. | |
1536 | ||
5a4c2a31 KW |
1537 | # include/linux/mmzone.h requires the following to be true: |
1538 | # | |
5e0a760b | 1539 | # MAX_PAGE_ORDER + PAGE_SHIFT <= SECTION_SIZE_BITS |
5a4c2a31 | 1540 | # |
5e0a760b | 1541 | # so the maximum value of MAX_PAGE_ORDER is SECTION_SIZE_BITS - PAGE_SHIFT: |
5a4c2a31 | 1542 | # |
5e0a760b KS |
1543 | # | SECTION_SIZE_BITS | PAGE_SHIFT | max MAX_PAGE_ORDER | default MAX_PAGE_ORDER | |
1544 | # ----+-------------------+--------------+----------------------+-------------------------+ | |
1545 | # 4K | 27 | 12 | 15 | 10 | | |
1546 | # 16K | 27 | 14 | 13 | 11 | | |
1547 | # 64K | 29 | 16 | 13 | 13 | | |
0192445c | 1548 | config ARCH_FORCE_MAX_ORDER |
f3c37621 | 1549 | int |
23baf831 | 1550 | default "13" if ARM64_64K_PAGES |
23baf831 | 1551 | default "11" if ARM64_16K_PAGES |
23baf831 | 1552 | default "10" |
44eaacf1 | 1553 | help |
4632cb22 | 1554 | The kernel page allocator limits the size of maximal physically |
5e0a760b | 1555 | contiguous allocations. The limit is called MAX_PAGE_ORDER and it |
4632cb22 MRI |
1556 | defines the maximal power of two of number of pages that can be |
1557 | allocated as a single contiguous block. This option allows | |
1558 | overriding the default setting when ability to allocate very | |
1559 | large blocks of physically contiguous memory is required. | |
44eaacf1 | 1560 | |
4632cb22 | 1561 | The maximal size of allocation cannot exceed the size of the |
5e0a760b | 1562 | section, so the value of MAX_PAGE_ORDER should satisfy |
44eaacf1 | 1563 | |
5e0a760b | 1564 | MAX_PAGE_ORDER + PAGE_SHIFT <= SECTION_SIZE_BITS |
4632cb22 MRI |
1565 | |
1566 | Don't change if unsure. | |
d03bb145 | 1567 | |
084eb77c | 1568 | config UNMAP_KERNEL_AT_EL0 |
7540f70d | 1569 | bool "Unmap kernel when running in userspace (KPTI)" if EXPERT |
084eb77c WD |
1570 | default y |
1571 | help | |
0617052d WD |
1572 | Speculation attacks against some high-performance processors can |
1573 | be used to bypass MMU permission checks and leak kernel data to | |
1574 | userspace. This can be defended against by unmapping the kernel | |
1575 | when running in userspace, mapping it back in on exception entry | |
1576 | via a trampoline page in the vector table. | |
084eb77c WD |
1577 | |
1578 | If unsure, say Y. | |
1579 | ||
558c303c JM |
1580 | config MITIGATE_SPECTRE_BRANCH_HISTORY |
1581 | bool "Mitigate Spectre style attacks against branch history" if EXPERT | |
1582 | default y | |
1583 | help | |
1584 | Speculation attacks against some high-performance processors can | |
1585 | make use of branch history to influence future speculation. | |
1586 | When taking an exception from user-space, a sequence of branches | |
1587 | or a firmware call overwrites the branch history. | |
1588 | ||
c55191e9 AB |
1589 | config RODATA_FULL_DEFAULT_ENABLED |
1590 | bool "Apply r/o permissions of VM areas also to their linear aliases" | |
1591 | default y | |
1592 | help | |
1593 | Apply read-only attributes of VM areas to the linear alias of | |
1594 | the backing pages as well. This prevents code or read-only data | |
1595 | from being modified (inadvertently or intentionally) via another | |
1596 | mapping of the same memory page. This additional enhancement can | |
1597 | be turned off at runtime by passing rodata=[off|on] (and turned on | |
1598 | with rodata=full if this option is set to 'n') | |
1599 | ||
1600 | This requires the linear region to be mapped down to pages, | |
1601 | which may adversely affect performance in some cases. | |
1602 | ||
dd523791 WD |
1603 | config ARM64_SW_TTBR0_PAN |
1604 | bool "Emulate Privileged Access Never using TTBR0_EL1 switching" | |
1605 | help | |
1606 | Enabling this option prevents the kernel from accessing | |
1607 | user-space memory directly by pointing TTBR0_EL1 to a reserved | |
1608 | zeroed area and reserved ASID. The user access routines | |
1609 | restore the valid TTBR0_EL1 temporarily. | |
1610 | ||
63f0c603 CM |
1611 | config ARM64_TAGGED_ADDR_ABI |
1612 | bool "Enable the tagged user addresses syscall ABI" | |
1613 | default y | |
1614 | help | |
1615 | When this option is enabled, user applications can opt in to a | |
1616 | relaxed ABI via prctl() allowing tagged addresses to be passed | |
1617 | to system calls as pointer arguments. For details, see | |
6e4596c4 | 1618 | Documentation/arch/arm64/tagged-address-abi.rst. |
63f0c603 | 1619 | |
dd523791 WD |
1620 | menuconfig COMPAT |
1621 | bool "Kernel support for 32-bit EL0" | |
1622 | depends on ARM64_4K_PAGES || EXPERT | |
dd523791 WD |
1623 | select HAVE_UID16 |
1624 | select OLD_SIGSUSPEND3 | |
1625 | select COMPAT_OLD_SIGACTION | |
1626 | help | |
1627 | This option enables support for a 32-bit EL0 running under a 64-bit | |
1628 | kernel at EL1. AArch32-specific components such as system calls, | |
1629 | the user helper functions, VFP support and the ptrace interface are | |
1630 | handled appropriately by the kernel. | |
1631 | ||
1632 | If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware | |
1633 | that you will only be able to execute AArch32 binaries that were compiled | |
1634 | with page size aligned segments. | |
1635 | ||
1636 | If you want to execute 32-bit userspace applications, say Y. | |
1637 | ||
1638 | if COMPAT | |
1639 | ||
1640 | config KUSER_HELPERS | |
7c4791c9 | 1641 | bool "Enable kuser helpers page for 32-bit applications" |
dd523791 WD |
1642 | default y |
1643 | help | |
1644 | Warning: disabling this option may break 32-bit user programs. | |
1645 | ||
1646 | Provide kuser helpers to compat tasks. The kernel provides | |
1647 | helper code to userspace in read only form at a fixed location | |
1648 | to allow userspace to be independent of the CPU type fitted to | |
1649 | the system. This permits binaries to be run on ARMv4 through | |
1650 | to ARMv8 without modification. | |
1651 | ||
263638dc | 1652 | See Documentation/arch/arm/kernel_user_helpers.rst for details. |
dd523791 WD |
1653 | |
1654 | However, the fixed address nature of these helpers can be used | |
1655 | by ROP (return orientated programming) authors when creating | |
1656 | exploits. | |
1657 | ||
1658 | If all of the binaries and libraries which run on your platform | |
1659 | are built specifically for your platform, and make no use of | |
1660 | these helpers, then you can turn this option off to hinder | |
1661 | such exploits. However, in that case, if a binary or library | |
1662 | relying on those helpers is run, it will not function correctly. | |
1663 | ||
1664 | Say N here only if you are absolutely certain that you do not | |
1665 | need these helpers; otherwise, the safe option is to say Y. | |
1666 | ||
7c4791c9 WD |
1667 | config COMPAT_VDSO |
1668 | bool "Enable vDSO for 32-bit applications" | |
3e6f8d1f ND |
1669 | depends on !CPU_BIG_ENDIAN |
1670 | depends on (CC_IS_CLANG && LD_IS_LLD) || "$(CROSS_COMPILE_COMPAT)" != "" | |
7c4791c9 WD |
1671 | select GENERIC_COMPAT_VDSO |
1672 | default y | |
1673 | help | |
1674 | Place in the process address space of 32-bit applications an | |
1675 | ELF shared object providing fast implementations of gettimeofday | |
1676 | and clock_gettime. | |
1677 | ||
1678 | You must have a 32-bit build of glibc 2.22 or later for programs | |
1679 | to seamlessly take advantage of this. | |
dd523791 | 1680 | |
625412c2 ND |
1681 | config THUMB2_COMPAT_VDSO |
1682 | bool "Compile the 32-bit vDSO for Thumb-2 mode" if EXPERT | |
1683 | depends on COMPAT_VDSO | |
1684 | default y | |
1685 | help | |
1686 | Compile the compat vDSO with '-mthumb -fomit-frame-pointer' if y, | |
1687 | otherwise with '-marm'. | |
1688 | ||
3fc24ef3 AB |
1689 | config COMPAT_ALIGNMENT_FIXUPS |
1690 | bool "Fix up misaligned multi-word loads and stores in user space" | |
1691 | ||
1b907f46 WD |
1692 | menuconfig ARMV8_DEPRECATED |
1693 | bool "Emulate deprecated/obsolete ARMv8 instructions" | |
6cfa7cc4 | 1694 | depends on SYSCTL |
1b907f46 WD |
1695 | help |
1696 | Legacy software support may require certain instructions | |
1697 | that have been deprecated or obsoleted in the architecture. | |
1698 | ||
1699 | Enable this config to enable selective emulation of these | |
1700 | features. | |
1701 | ||
1702 | If unsure, say Y | |
1703 | ||
1704 | if ARMV8_DEPRECATED | |
1705 | ||
1706 | config SWP_EMULATION | |
1707 | bool "Emulate SWP/SWPB instructions" | |
1708 | help | |
1709 | ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that | |
1710 | they are always undefined. Say Y here to enable software | |
1711 | emulation of these instructions for userspace using LDXR/STXR. | |
dd720784 MB |
1712 | This feature can be controlled at runtime with the abi.swp |
1713 | sysctl which is disabled by default. | |
1b907f46 WD |
1714 | |
1715 | In some older versions of glibc [<=2.8] SWP is used during futex | |
1716 | trylock() operations with the assumption that the code will not | |
1717 | be preempted. This invalid assumption may be more likely to fail | |
1718 | with SWP emulation enabled, leading to deadlock of the user | |
1719 | application. | |
1720 | ||
1721 | NOTE: when accessing uncached shared regions, LDXR/STXR rely | |
1722 | on an external transaction monitoring block called a global | |
1723 | monitor to maintain update atomicity. If your system does not | |
1724 | implement a global monitor, this option can cause programs that | |
1725 | perform SWP operations to uncached memory to deadlock. | |
1726 | ||
1727 | If unsure, say Y | |
1728 | ||
1729 | config CP15_BARRIER_EMULATION | |
1730 | bool "Emulate CP15 Barrier instructions" | |
1731 | help | |
1732 | The CP15 barrier instructions - CP15ISB, CP15DSB, and | |
1733 | CP15DMB - are deprecated in ARMv8 (and ARMv7). It is | |
1734 | strongly recommended to use the ISB, DSB, and DMB | |
1735 | instructions instead. | |
1736 | ||
1737 | Say Y here to enable software emulation of these | |
1738 | instructions for AArch32 userspace code. When this option is | |
1739 | enabled, CP15 barrier usage is traced which can help | |
dd720784 MB |
1740 | identify software that needs updating. This feature can be |
1741 | controlled at runtime with the abi.cp15_barrier sysctl. | |
1b907f46 WD |
1742 | |
1743 | If unsure, say Y | |
1744 | ||
2d888f48 SP |
1745 | config SETEND_EMULATION |
1746 | bool "Emulate SETEND instruction" | |
1747 | help | |
1748 | The SETEND instruction alters the data-endianness of the | |
1749 | AArch32 EL0, and is deprecated in ARMv8. | |
1750 | ||
1751 | Say Y here to enable software emulation of the instruction | |
dd720784 MB |
1752 | for AArch32 userspace code. This feature can be controlled |
1753 | at runtime with the abi.setend sysctl. | |
2d888f48 SP |
1754 | |
1755 | Note: All the cpus on the system must have mixed endian support at EL0 | |
1756 | for this feature to be enabled. If a new CPU - which doesn't support mixed | |
1757 | endian - is hotplugged in after this feature has been enabled, there could | |
1758 | be unexpected results in the applications. | |
1759 | ||
1760 | If unsure, say Y | |
3cb7e662 | 1761 | endif # ARMV8_DEPRECATED |
1b907f46 | 1762 | |
3cb7e662 | 1763 | endif # COMPAT |
ba42822a | 1764 | |
0e4a0709 WD |
1765 | menu "ARMv8.1 architectural features" |
1766 | ||
1767 | config ARM64_HW_AFDBM | |
1768 | bool "Support for hardware updates of the Access and Dirty page flags" | |
1769 | default y | |
1770 | help | |
1771 | The ARMv8.1 architecture extensions introduce support for | |
1772 | hardware updates of the access and dirty information in page | |
1773 | table entries. When enabled in TCR_EL1 (HA and HD bits) on | |
1774 | capable processors, accesses to pages with PTE_AF cleared will | |
1775 | set this bit instead of raising an access flag fault. | |
1776 | Similarly, writes to read-only pages with the DBM bit set will | |
1777 | clear the read-only bit (AP[2]) instead of raising a | |
1778 | permission fault. | |
1779 | ||
1780 | Kernels built with this configuration option enabled continue | |
1781 | to work on pre-ARMv8.1 hardware and the performance impact is | |
1782 | minimal. If unsure, say Y. | |
1783 | ||
1784 | config ARM64_PAN | |
1785 | bool "Enable support for Privileged Access Never (PAN)" | |
1786 | default y | |
1787 | help | |
3cb7e662 JH |
1788 | Privileged Access Never (PAN; part of the ARMv8.1 Extensions) |
1789 | prevents the kernel or hypervisor from accessing user-space (EL0) | |
1790 | memory directly. | |
0e4a0709 | 1791 | |
3cb7e662 JH |
1792 | Choosing this option will cause any unprotected (not using |
1793 | copy_to_user et al) memory access to fail with a permission fault. | |
0e4a0709 | 1794 | |
3cb7e662 JH |
1795 | The feature is detected at runtime, and will remain as a 'nop' |
1796 | instruction if the cpu does not implement the feature. | |
0e4a0709 | 1797 | |
2decad92 CM |
1798 | config AS_HAS_LSE_ATOMICS |
1799 | def_bool $(as-instr,.arch_extension lse) | |
1800 | ||
0e4a0709 | 1801 | config ARM64_LSE_ATOMICS |
395af861 CM |
1802 | bool |
1803 | default ARM64_USE_LSE_ATOMICS | |
2decad92 | 1804 | depends on AS_HAS_LSE_ATOMICS |
395af861 CM |
1805 | |
1806 | config ARM64_USE_LSE_ATOMICS | |
0e4a0709 | 1807 | bool "Atomic instructions" |
7bd99b40 | 1808 | default y |
0e4a0709 WD |
1809 | help |
1810 | As part of the Large System Extensions, ARMv8.1 introduces new | |
1811 | atomic instructions that are designed specifically to scale in | |
1812 | very large systems. | |
1813 | ||
1814 | Say Y here to make use of these instructions for the in-kernel | |
1815 | atomic routines. This incurs a small overhead on CPUs that do | |
1816 | not support these instructions and requires the kernel to be | |
7bd99b40 WD |
1817 | built with binutils >= 2.25 in order for the new instructions |
1818 | to be used. | |
0e4a0709 | 1819 | |
3cb7e662 | 1820 | endmenu # "ARMv8.1 architectural features" |
0e4a0709 | 1821 | |
f993318b WD |
1822 | menu "ARMv8.2 architectural features" |
1823 | ||
2c54b423 | 1824 | config AS_HAS_ARMV8_2 |
3cb7e662 | 1825 | def_bool $(cc-option,-Wa$(comma)-march=armv8.2-a) |
2c54b423 AB |
1826 | |
1827 | config AS_HAS_SHA3 | |
3cb7e662 | 1828 | def_bool $(as-instr,.arch armv8.2-a+sha3) |
2c54b423 | 1829 | |
d50e071f RM |
1830 | config ARM64_PMEM |
1831 | bool "Enable support for persistent memory" | |
1832 | select ARCH_HAS_PMEM_API | |
5d7bdeb1 | 1833 | select ARCH_HAS_UACCESS_FLUSHCACHE |
d50e071f RM |
1834 | help |
1835 | Say Y to enable support for the persistent memory API based on the | |
1836 | ARMv8.2 DCPoP feature. | |
1837 | ||
1838 | The feature is detected at runtime, and the kernel will use DC CVAC | |
1839 | operations if DC CVAP is not supported (following the behaviour of | |
1840 | DC CVAP itself if the system does not define a point of persistence). | |
1841 | ||
64c02720 XX |
1842 | config ARM64_RAS_EXTN |
1843 | bool "Enable support for RAS CPU Extensions" | |
1844 | default y | |
1845 | help | |
1846 | CPUs that support the Reliability, Availability and Serviceability | |
1847 | (RAS) Extensions, part of ARMv8.2 are able to track faults and | |
1848 | errors, classify them and report them to software. | |
1849 | ||
1850 | On CPUs with these extensions system software can use additional | |
1851 | barriers to determine if faults are pending and read the | |
1852 | classification from a new set of registers. | |
1853 | ||
1854 | Selecting this feature will allow the kernel to use these barriers | |
1855 | and access the new registers if the system supports the extension. | |
1856 | Platform RAS features may additionally depend on firmware support. | |
1857 | ||
5ffdfaed VM |
1858 | config ARM64_CNP |
1859 | bool "Enable support for Common Not Private (CNP) translations" | |
1860 | default y | |
1861 | depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN | |
1862 | help | |
1863 | Common Not Private (CNP) allows translation table entries to | |
1864 | be shared between different PEs in the same inner shareable | |
1865 | domain, so the hardware can use this fact to optimise the | |
1866 | caching of such entries in the TLB. | |
1867 | ||
1868 | Selecting this option allows the CNP feature to be detected | |
1869 | at runtime, and does not affect PEs that do not implement | |
1870 | this feature. | |
1871 | ||
3cb7e662 | 1872 | endmenu # "ARMv8.2 architectural features" |
f993318b | 1873 | |
04ca3204 MR |
1874 | menu "ARMv8.3 architectural features" |
1875 | ||
1876 | config ARM64_PTR_AUTH | |
1877 | bool "Enable support for pointer authentication" | |
1878 | default y | |
1879 | help | |
1880 | Pointer authentication (part of the ARMv8.3 Extensions) provides | |
1881 | instructions for signing and authenticating pointers against secret | |
1882 | keys, which can be used to mitigate Return Oriented Programming (ROP) | |
1883 | and other attacks. | |
1884 | ||
1885 | This option enables these instructions at EL0 (i.e. for userspace). | |
04ca3204 MR |
1886 | Choosing this option will cause the kernel to initialise secret keys |
1887 | for each process at exec() time, with these keys being | |
1888 | context-switched along with the process. | |
1889 | ||
1890 | The feature is detected at runtime. If the feature is not present in | |
384b40ca | 1891 | hardware it will not be advertised to userspace/KVM guest nor will it |
dfb0589c | 1892 | be enabled. |
04ca3204 | 1893 | |
6982934e KM |
1894 | If the feature is present on the boot CPU but not on a late CPU, then |
1895 | the late CPU will be parked. Also, if the boot CPU does not have | |
1896 | address auth and the late CPU has then the late CPU will still boot | |
1897 | but with the feature disabled. On such a system, this option should | |
1898 | not be selected. | |
1899 | ||
b27a9f41 | 1900 | config ARM64_PTR_AUTH_KERNEL |
d053e71a | 1901 | bool "Use pointer authentication for kernel" |
b27a9f41 DK |
1902 | default y |
1903 | depends on ARM64_PTR_AUTH | |
1e249c41 | 1904 | depends on (CC_HAS_SIGN_RETURN_ADDRESS || CC_HAS_BRANCH_PROT_PAC_RET) && AS_HAS_ARMV8_3 |
b27a9f41 DK |
1905 | # Modern compilers insert a .note.gnu.property section note for PAC |
1906 | # which is only understood by binutils starting with version 2.33.1. | |
1907 | depends on LD_IS_LLD || LD_VERSION >= 23301 || (CC_IS_GCC && GCC_VERSION < 90100) | |
1908 | depends on !CC_IS_CLANG || AS_HAS_CFI_NEGATE_RA_STATE | |
26299b3f | 1909 | depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_ARGS) |
b27a9f41 DK |
1910 | help |
1911 | If the compiler supports the -mbranch-protection or | |
1912 | -msign-return-address flag (e.g. GCC 7 or later), then this option | |
1913 | will cause the kernel itself to be compiled with return address | |
1914 | protection. In this case, and if the target hardware is known to | |
1915 | support pointer authentication, then CONFIG_STACKPROTECTOR can be | |
1916 | disabled with minimal loss of protection. | |
1917 | ||
74afda40 | 1918 | This feature works with FUNCTION_GRAPH_TRACER option only if |
26299b3f | 1919 | DYNAMIC_FTRACE_WITH_ARGS is enabled. |
74afda40 KM |
1920 | |
1921 | config CC_HAS_BRANCH_PROT_PAC_RET | |
1922 | # GCC 9 or later, clang 8 or later | |
1923 | def_bool $(cc-option,-mbranch-protection=pac-ret+leaf) | |
1924 | ||
1925 | config CC_HAS_SIGN_RETURN_ADDRESS | |
1926 | # GCC 7, 8 | |
1927 | def_bool $(cc-option,-msign-return-address=all) | |
1928 | ||
1e249c41 | 1929 | config AS_HAS_ARMV8_3 |
4d0831e8 | 1930 | def_bool $(cc-option,-Wa$(comma)-march=armv8.3-a) |
74afda40 | 1931 | |
3b446c7d ND |
1932 | config AS_HAS_CFI_NEGATE_RA_STATE |
1933 | def_bool $(as-instr,.cfi_startproc\n.cfi_negate_ra_state\n.cfi_endproc\n) | |
1934 | ||
64a0b90a ZH |
1935 | config AS_HAS_LDAPR |
1936 | def_bool $(as-instr,.arch_extension rcpc) | |
1937 | ||
3cb7e662 | 1938 | endmenu # "ARMv8.3 architectural features" |
04ca3204 | 1939 | |
2c9d45b4 IV |
1940 | menu "ARMv8.4 architectural features" |
1941 | ||
1942 | config ARM64_AMU_EXTN | |
1943 | bool "Enable support for the Activity Monitors Unit CPU extension" | |
1944 | default y | |
1945 | help | |
1946 | The activity monitors extension is an optional extension introduced | |
1947 | by the ARMv8.4 CPU architecture. This enables support for version 1 | |
1948 | of the activity monitors architecture, AMUv1. | |
1949 | ||
1950 | To enable the use of this extension on CPUs that implement it, say Y. | |
1951 | ||
1952 | Note that for architectural reasons, firmware _must_ implement AMU | |
1953 | support when running on CPUs that present the activity monitors | |
1954 | extension. The required support is present in: | |
1955 | * Version 1.5 and later of the ARM Trusted Firmware | |
1956 | ||
1957 | For kernels that have this configuration enabled but boot with broken | |
1958 | firmware, you may need to say N here until the firmware is fixed. | |
1959 | Otherwise you may experience firmware panics or lockups when | |
1960 | accessing the counter registers. Even if you are not observing these | |
1961 | symptoms, the values returned by the register reads might not | |
1962 | correctly reflect reality. Most commonly, the value read will be 0, | |
1963 | indicating that the counter is not enabled. | |
1964 | ||
7c78f67e ZY |
1965 | config AS_HAS_ARMV8_4 |
1966 | def_bool $(cc-option,-Wa$(comma)-march=armv8.4-a) | |
1967 | ||
1968 | config ARM64_TLB_RANGE | |
1969 | bool "Enable support for tlbi range feature" | |
1970 | default y | |
1971 | depends on AS_HAS_ARMV8_4 | |
1972 | help | |
1973 | ARMv8.4-TLBI provides TLBI invalidation instruction that apply to a | |
1974 | range of input addresses. | |
1975 | ||
1976 | The feature introduces new assembly instructions, and they were | |
1977 | support when binutils >= 2.30. | |
1978 | ||
3cb7e662 | 1979 | endmenu # "ARMv8.4 architectural features" |
04ca3204 | 1980 | |
3e6c69a0 MB |
1981 | menu "ARMv8.5 architectural features" |
1982 | ||
f469c032 VF |
1983 | config AS_HAS_ARMV8_5 |
1984 | def_bool $(cc-option,-Wa$(comma)-march=armv8.5-a) | |
1985 | ||
383499f8 DM |
1986 | config ARM64_BTI |
1987 | bool "Branch Target Identification support" | |
1988 | default y | |
1989 | help | |
1990 | Branch Target Identification (part of the ARMv8.5 Extensions) | |
1991 | provides a mechanism to limit the set of locations to which computed | |
1992 | branch instructions such as BR or BLR can jump. | |
1993 | ||
1994 | To make use of BTI on CPUs that support it, say Y. | |
1995 | ||
1996 | BTI is intended to provide complementary protection to other control | |
1997 | flow integrity protection mechanisms, such as the Pointer | |
1998 | authentication mechanism provided as part of the ARMv8.3 Extensions. | |
1999 | For this reason, it does not make sense to enable this option without | |
2000 | also enabling support for pointer authentication. Thus, when | |
2001 | enabling this option you should also select ARM64_PTR_AUTH=y. | |
2002 | ||
2003 | Userspace binaries must also be specifically compiled to make use of | |
2004 | this mechanism. If you say N here or the hardware does not support | |
2005 | BTI, such binaries can still run, but you get no additional | |
2006 | enforcement of branch destinations. | |
2007 | ||
97fed779 MB |
2008 | config ARM64_BTI_KERNEL |
2009 | bool "Use Branch Target Identification for kernel" | |
2010 | default y | |
2011 | depends on ARM64_BTI | |
b27a9f41 | 2012 | depends on ARM64_PTR_AUTH_KERNEL |
97fed779 | 2013 | depends on CC_HAS_BRANCH_PROT_PAC_RET_BTI |
3a88d7c5 WD |
2014 | # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94697 |
2015 | depends on !CC_IS_GCC || GCC_VERSION >= 100100 | |
c0a454b9 MB |
2016 | # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106671 |
2017 | depends on !CC_IS_GCC | |
8cdd23c2 NC |
2018 | # https://github.com/llvm/llvm-project/commit/a88c722e687e6780dcd6a58718350dc76fcc4cc9 |
2019 | depends on !CC_IS_CLANG || CLANG_VERSION >= 120000 | |
26299b3f | 2020 | depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_ARGS) |
97fed779 MB |
2021 | help |
2022 | Build the kernel with Branch Target Identification annotations | |
2023 | and enable enforcement of this for kernel code. When this option | |
2024 | is enabled and the system supports BTI all kernel code including | |
2025 | modular code must have BTI enabled. | |
2026 | ||
2027 | config CC_HAS_BRANCH_PROT_PAC_RET_BTI | |
2028 | # GCC 9 or later, clang 8 or later | |
2029 | def_bool $(cc-option,-mbranch-protection=pac-ret+leaf+bti) | |
2030 | ||
3e6c69a0 MB |
2031 | config ARM64_E0PD |
2032 | bool "Enable support for E0PD" | |
2033 | default y | |
2034 | help | |
e717d93b WD |
2035 | E0PD (part of the ARMv8.5 extensions) allows us to ensure |
2036 | that EL0 accesses made via TTBR1 always fault in constant time, | |
2037 | providing similar benefits to KASLR as those provided by KPTI, but | |
2038 | with lower overhead and without disrupting legitimate access to | |
2039 | kernel memory such as SPE. | |
3e6c69a0 | 2040 | |
e717d93b | 2041 | This option enables E0PD for TTBR1 where available. |
3e6c69a0 | 2042 | |
89b94df9 VF |
2043 | config ARM64_AS_HAS_MTE |
2044 | # Initial support for MTE went in binutils 2.32.0, checked with | |
2045 | # ".arch armv8.5-a+memtag" below. However, this was incomplete | |
2046 | # as a late addition to the final architecture spec (LDGM/STGM) | |
2047 | # is only supported in the newer 2.32.x and 2.33 binutils | |
2048 | # versions, hence the extra "stgm" instruction check below. | |
2049 | def_bool $(as-instr,.arch armv8.5-a+memtag\nstgm xzr$(comma)[x0]) | |
2050 | ||
2051 | config ARM64_MTE | |
2052 | bool "Memory Tagging Extension support" | |
2053 | default y | |
2054 | depends on ARM64_AS_HAS_MTE && ARM64_TAGGED_ADDR_ABI | |
f469c032 | 2055 | depends on AS_HAS_ARMV8_5 |
2decad92 | 2056 | depends on AS_HAS_LSE_ATOMICS |
98c970da VF |
2057 | # Required for tag checking in the uaccess routines |
2058 | depends on ARM64_PAN | |
f3ba50a7 | 2059 | select ARCH_HAS_SUBPAGE_FAULTS |
89b94df9 | 2060 | select ARCH_USES_HIGH_VMA_FLAGS |
b0284cd2 | 2061 | select ARCH_USES_PG_ARCH_X |
89b94df9 VF |
2062 | help |
2063 | Memory Tagging (part of the ARMv8.5 Extensions) provides | |
2064 | architectural support for run-time, always-on detection of | |
2065 | various classes of memory error to aid with software debugging | |
2066 | to eliminate vulnerabilities arising from memory-unsafe | |
2067 | languages. | |
2068 | ||
2069 | This option enables the support for the Memory Tagging | |
2070 | Extension at EL0 (i.e. for userspace). | |
2071 | ||
2072 | Selecting this option allows the feature to be detected at | |
2073 | runtime. Any secondary CPU not implementing this feature will | |
2074 | not be allowed a late bring-up. | |
2075 | ||
2076 | Userspace binaries that want to use this feature must | |
2077 | explicitly opt in. The mechanism for the userspace is | |
2078 | described in: | |
2079 | ||
6e4596c4 | 2080 | Documentation/arch/arm64/memory-tagging-extension.rst. |
89b94df9 | 2081 | |
3cb7e662 | 2082 | endmenu # "ARMv8.5 architectural features" |
3e6c69a0 | 2083 | |
18107f8a VM |
2084 | menu "ARMv8.7 architectural features" |
2085 | ||
2086 | config ARM64_EPAN | |
2087 | bool "Enable support for Enhanced Privileged Access Never (EPAN)" | |
2088 | default y | |
2089 | depends on ARM64_PAN | |
2090 | help | |
3cb7e662 JH |
2091 | Enhanced Privileged Access Never (EPAN) allows Privileged |
2092 | Access Never to be used with Execute-only mappings. | |
18107f8a | 2093 | |
3cb7e662 JH |
2094 | The feature is detected at runtime, and will remain disabled |
2095 | if the cpu does not implement the feature. | |
2096 | endmenu # "ARMv8.7 architectural features" | |
18107f8a | 2097 | |
ddd25ad1 DM |
2098 | config ARM64_SVE |
2099 | bool "ARM Scalable Vector Extension support" | |
2100 | default y | |
2101 | help | |
2102 | The Scalable Vector Extension (SVE) is an extension to the AArch64 | |
2103 | execution state which complements and extends the SIMD functionality | |
2104 | of the base architecture to support much larger vectors and to enable | |
2105 | additional vectorisation opportunities. | |
2106 | ||
2107 | To enable use of this extension on CPUs that implement it, say Y. | |
2108 | ||
06a916fe DM |
2109 | On CPUs that support the SVE2 extensions, this option will enable |
2110 | those too. | |
2111 | ||
5043694e DM |
2112 | Note that for architectural reasons, firmware _must_ implement SVE |
2113 | support when running on SVE capable hardware. The required support | |
2114 | is present in: | |
2115 | ||
2116 | * version 1.5 and later of the ARM Trusted Firmware | |
2117 | * the AArch64 boot wrapper since commit 5e1261e08abf | |
2118 | ("bootwrapper: SVE: Enable SVE for EL2 and below"). | |
2119 | ||
2120 | For other firmware implementations, consult the firmware documentation | |
2121 | or vendor. | |
2122 | ||
2123 | If you need the kernel to boot on SVE-capable hardware with broken | |
2124 | firmware, you may need to say N here until you get your firmware | |
2125 | fixed. Otherwise, you may experience firmware panics or lockups when | |
2126 | booting the kernel. If unsure and you are not observing these | |
2127 | symptoms, you should assume that it is safe to say Y. | |
fd045f6c | 2128 | |
a1f4ccd2 MB |
2129 | config ARM64_SME |
2130 | bool "ARM Scalable Matrix Extension support" | |
2131 | default y | |
2132 | depends on ARM64_SVE | |
2133 | help | |
2134 | The Scalable Matrix Extension (SME) is an extension to the AArch64 | |
2135 | execution state which utilises a substantial subset of the SVE | |
2136 | instruction set, together with the addition of new architectural | |
2137 | register state capable of holding two dimensional matrix tiles to | |
2138 | enable various matrix operations. | |
2139 | ||
bc3c03cc JT |
2140 | config ARM64_PSEUDO_NMI |
2141 | bool "Support for NMI-like interrupts" | |
3c9c1dcd | 2142 | select ARM_GIC_V3 |
bc3c03cc JT |
2143 | help |
2144 | Adds support for mimicking Non-Maskable Interrupts through the use of | |
2145 | GIC interrupt priority. This support requires version 3 or later of | |
bc15cf70 | 2146 | ARM GIC. |
bc3c03cc JT |
2147 | |
2148 | This high priority configuration for interrupts needs to be | |
2149 | explicitly enabled by setting the kernel parameter | |
2150 | "irqchip.gicv3_pseudo_nmi" to 1. | |
2151 | ||
2152 | If unsure, say N | |
2153 | ||
48ce8f80 JT |
2154 | if ARM64_PSEUDO_NMI |
2155 | config ARM64_DEBUG_PRIORITY_MASKING | |
2156 | bool "Debug interrupt priority masking" | |
2157 | help | |
2158 | This adds runtime checks to functions enabling/disabling | |
2159 | interrupts when using priority masking. The additional checks verify | |
2160 | the validity of ICC_PMR_EL1 when calling concerned functions. | |
2161 | ||
2162 | If unsure, say N | |
3cb7e662 | 2163 | endif # ARM64_PSEUDO_NMI |
48ce8f80 | 2164 | |
1e48ef7f | 2165 | config RELOCATABLE |
dd4bc607 | 2166 | bool "Build a relocatable kernel image" if EXPERT |
5cf896fb | 2167 | select ARCH_HAS_RELR |
dd4bc607 | 2168 | default y |
1e48ef7f AB |
2169 | help |
2170 | This builds the kernel as a Position Independent Executable (PIE), | |
2171 | which retains all relocation metadata required to relocate the | |
2172 | kernel binary at runtime to a different virtual address than the | |
2173 | address it was linked at. | |
2174 | Since AArch64 uses the RELA relocation format, this requires a | |
2175 | relocation pass at runtime even if the kernel is loaded at the | |
2176 | same address it was linked at. | |
2177 | ||
f80fb3a3 AB |
2178 | config RANDOMIZE_BASE |
2179 | bool "Randomize the address of the kernel image" | |
f80fb3a3 AB |
2180 | select RELOCATABLE |
2181 | help | |
2182 | Randomizes the virtual address at which the kernel image is | |
2183 | loaded, as a security feature that deters exploit attempts | |
2184 | relying on knowledge of the location of kernel internals. | |
2185 | ||
2186 | It is the bootloader's job to provide entropy, by passing a | |
2187 | random u64 value in /chosen/kaslr-seed at kernel entry. | |
2188 | ||
2b5fe07a AB |
2189 | When booting via the UEFI stub, it will invoke the firmware's |
2190 | EFI_RNG_PROTOCOL implementation (if available) to supply entropy | |
2191 | to the kernel proper. In addition, it will randomise the physical | |
2192 | location of the kernel Image as well. | |
2193 | ||
f80fb3a3 AB |
2194 | If unsure, say N. |
2195 | ||
2196 | config RANDOMIZE_MODULE_REGION_FULL | |
f9c4ff2a | 2197 | bool "Randomize the module region over a 2 GB range" |
e71a4e1b | 2198 | depends on RANDOMIZE_BASE |
f80fb3a3 AB |
2199 | default y |
2200 | help | |
f9c4ff2a | 2201 | Randomizes the location of the module region inside a 2 GB window |
f2b9ba87 | 2202 | covering the core kernel. This way, it is less likely for modules |
f80fb3a3 AB |
2203 | to leak information about the location of core kernel data structures |
2204 | but it does imply that function calls between modules and the core | |
2205 | kernel will need to be resolved via veneers in the module PLT. | |
2206 | ||
2207 | When this option is not set, the module region will be randomized over | |
2208 | a limited range that contains the [_stext, _etext] interval of the | |
f9c4ff2a | 2209 | core kernel, so branch relocations are almost always in range unless |
ea3752ba MR |
2210 | the region is exhausted. In this particular case of region |
2211 | exhaustion, modules might be able to fall back to a larger 2GB area. | |
f80fb3a3 | 2212 | |
0a1213fa AB |
2213 | config CC_HAVE_STACKPROTECTOR_SYSREG |
2214 | def_bool $(cc-option,-mstack-protector-guard=sysreg -mstack-protector-guard-reg=sp_el0 -mstack-protector-guard-offset=0) | |
2215 | ||
2216 | config STACKPROTECTOR_PER_TASK | |
2217 | def_bool y | |
2218 | depends on STACKPROTECTOR && CC_HAVE_STACKPROTECTOR_SYSREG | |
2219 | ||
3b619e22 AB |
2220 | config UNWIND_PATCH_PAC_INTO_SCS |
2221 | bool "Enable shadow call stack dynamically using code patching" | |
2222 | # needs Clang with https://reviews.llvm.org/D111780 incorporated | |
2223 | depends on CC_IS_CLANG && CLANG_VERSION >= 150000 | |
2224 | depends on ARM64_PTR_AUTH_KERNEL && CC_HAS_BRANCH_PROT_PAC_RET | |
2225 | depends on SHADOW_CALL_STACK | |
2226 | select UNWIND_TABLES | |
2227 | select DYNAMIC_SCS | |
2228 | ||
3cb7e662 | 2229 | endmenu # "Kernel Features" |
8c2c3df3 CM |
2230 | |
2231 | menu "Boot options" | |
2232 | ||
5e89c55e LP |
2233 | config ARM64_ACPI_PARKING_PROTOCOL |
2234 | bool "Enable support for the ARM64 ACPI parking protocol" | |
2235 | depends on ACPI | |
2236 | help | |
2237 | Enable support for the ARM64 ACPI parking protocol. If disabled | |
2238 | the kernel will not allow booting through the ARM64 ACPI parking | |
2239 | protocol even if the corresponding data is present in the ACPI | |
2240 | MADT table. | |
2241 | ||
8c2c3df3 CM |
2242 | config CMDLINE |
2243 | string "Default kernel command string" | |
2244 | default "" | |
2245 | help | |
2246 | Provide a set of default command-line options at build time by | |
2247 | entering them here. As a minimum, you should specify the the | |
2248 | root device (e.g. root=/dev/nfs). | |
2249 | ||
1e40d105 TH |
2250 | choice |
2251 | prompt "Kernel command line type" if CMDLINE != "" | |
2252 | default CMDLINE_FROM_BOOTLOADER | |
2253 | help | |
2254 | Choose how the kernel will handle the provided default kernel | |
2255 | command line string. | |
2256 | ||
2257 | config CMDLINE_FROM_BOOTLOADER | |
2258 | bool "Use bootloader kernel arguments if available" | |
2259 | help | |
2260 | Uses the command-line options passed by the boot loader. If | |
2261 | the boot loader doesn't provide any, the default kernel command | |
2262 | string provided in CMDLINE will be used. | |
2263 | ||
8c2c3df3 CM |
2264 | config CMDLINE_FORCE |
2265 | bool "Always use the default kernel command string" | |
2266 | help | |
2267 | Always use the default kernel command string, even if the boot | |
2268 | loader passes other arguments to the kernel. | |
2269 | This is useful if you cannot or don't want to change the | |
2270 | command-line options your boot loader passes to the kernel. | |
2271 | ||
1e40d105 TH |
2272 | endchoice |
2273 | ||
f4f75ad5 AB |
2274 | config EFI_STUB |
2275 | bool | |
2276 | ||
f84d0275 MS |
2277 | config EFI |
2278 | bool "UEFI runtime support" | |
2279 | depends on OF && !CPU_BIG_ENDIAN | |
b472db6c | 2280 | depends on KERNEL_MODE_NEON |
2c870e61 | 2281 | select ARCH_SUPPORTS_ACPI |
f84d0275 MS |
2282 | select LIBFDT |
2283 | select UCS2_STRING | |
2284 | select EFI_PARAMS_FROM_FDT | |
e15dd494 | 2285 | select EFI_RUNTIME_WRAPPERS |
f4f75ad5 | 2286 | select EFI_STUB |
2e0eb483 | 2287 | select EFI_GENERIC_STUB |
8d39cee0 | 2288 | imply IMA_SECURE_AND_OR_TRUSTED_BOOT |
f84d0275 MS |
2289 | default y |
2290 | help | |
2291 | This option provides support for runtime services provided | |
2292 | by UEFI firmware (such as non-volatile variables, realtime | |
3cb7e662 | 2293 | clock, and platform reset). A UEFI stub is also provided to |
3c7f2550 MS |
2294 | allow the kernel to be booted as an EFI application. This |
2295 | is only useful on systems that have UEFI firmware. | |
f84d0275 | 2296 | |
d1ae8c00 YL |
2297 | config DMI |
2298 | bool "Enable support for SMBIOS (DMI) tables" | |
2299 | depends on EFI | |
2300 | default y | |
2301 | help | |
2302 | This enables SMBIOS/DMI feature for systems. | |
2303 | ||
2304 | This option is only useful on systems that have UEFI firmware. | |
2305 | However, even with this option, the resultant kernel should | |
2306 | continue to boot on existing non-UEFI platforms. | |
2307 | ||
3cb7e662 | 2308 | endmenu # "Boot options" |
8c2c3df3 | 2309 | |
166936ba LP |
2310 | menu "Power management options" |
2311 | ||
2312 | source "kernel/power/Kconfig" | |
2313 | ||
82869ac5 JM |
2314 | config ARCH_HIBERNATION_POSSIBLE |
2315 | def_bool y | |
2316 | depends on CPU_PM | |
2317 | ||
2318 | config ARCH_HIBERNATION_HEADER | |
2319 | def_bool y | |
2320 | depends on HIBERNATION | |
2321 | ||
166936ba LP |
2322 | config ARCH_SUSPEND_POSSIBLE |
2323 | def_bool y | |
2324 | ||
3cb7e662 | 2325 | endmenu # "Power management options" |
166936ba | 2326 | |
1307220d LP |
2327 | menu "CPU Power Management" |
2328 | ||
2329 | source "drivers/cpuidle/Kconfig" | |
2330 | ||
52e7e816 RH |
2331 | source "drivers/cpufreq/Kconfig" |
2332 | ||
3cb7e662 | 2333 | endmenu # "CPU Power Management" |
52e7e816 | 2334 | |
b6a02173 GG |
2335 | source "drivers/acpi/Kconfig" |
2336 | ||
c3eb5b14 MZ |
2337 | source "arch/arm64/kvm/Kconfig" |
2338 |