arm64: psci: factor invocation code to drivers
[linux-2.6-block.git] / arch / arm64 / Kconfig
CommitLineData
8c2c3df3
CM
1config ARM64
2 def_bool y
b6197b93 3 select ACPI_CCA_REQUIRED if ACPI
d8f4f161 4 select ACPI_GENERIC_GSI if ACPI
6933de0c 5 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
8c2c3df3 6 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
2b68f6ca 7 select ARCH_HAS_ELF_RANDOMIZE
957e3fac 8 select ARCH_HAS_GCOV_PROFILE_ALL
308c09f1 9 select ARCH_HAS_SG_CHAIN
1f85008e 10 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
c63c8700 11 select ARCH_USE_CMPXCHG_LOCKREF
4badad35 12 select ARCH_SUPPORTS_ATOMIC_RMW
9170100e 13 select ARCH_WANT_OPTIONAL_GPIOLIB
6212a512 14 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
b6f35981 15 select ARCH_WANT_FRAME_POINTERS
25c92a37 16 select ARM_AMBA
1aee5d7a 17 select ARM_ARCH_TIMER
c4188edc 18 select ARM_GIC
875cbf3e 19 select AUDIT_ARCH_COMPAT_GENERIC
853a33ce 20 select ARM_GIC_V2M if PCI_MSI
021f6537 21 select ARM_GIC_V3
19812729 22 select ARM_GIC_V3_ITS if PCI_MSI
bff60792 23 select ARM_PSCI_FW
adace895 24 select BUILDTIME_EXTABLE_SORT
db2789b5 25 select CLONE_BACKWARDS
7ca2ef33 26 select COMMON_CLK
166936ba 27 select CPU_PM if (SUSPEND || CPU_IDLE)
7bc13fd3 28 select DCACHE_WORD_ACCESS
ef37566c 29 select EDAC_SUPPORT
d4932f9e 30 select GENERIC_ALLOCATOR
8c2c3df3 31 select GENERIC_CLOCKEVENTS
1f85008e 32 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
3be1a5c4 33 select GENERIC_CPU_AUTOPROBE
bf4b558e 34 select GENERIC_EARLY_IOREMAP
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35 select GENERIC_IRQ_PROBE
36 select GENERIC_IRQ_SHOW
6544e67b 37 select GENERIC_IRQ_SHOW_LEVEL
cb61f676 38 select GENERIC_PCI_IOMAP
65cd4f6c 39 select GENERIC_SCHED_CLOCK
8c2c3df3 40 select GENERIC_SMP_IDLE_THREAD
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41 select GENERIC_STRNCPY_FROM_USER
42 select GENERIC_STRNLEN_USER
8c2c3df3 43 select GENERIC_TIME_VSYSCALL
a1ddc74a 44 select HANDLE_DOMAIN_IRQ
8c2c3df3 45 select HARDIRQS_SW_RESEND
5284e1b4 46 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
875cbf3e 47 select HAVE_ARCH_AUDITSYSCALL
8e7a4cef 48 select HAVE_ARCH_BITREVERSE
9732cafd 49 select HAVE_ARCH_JUMP_LABEL
9529247d 50 select HAVE_ARCH_KGDB
a1ae65b2 51 select HAVE_ARCH_SECCOMP_FILTER
8c2c3df3 52 select HAVE_ARCH_TRACEHOOK
e54bcde3 53 select HAVE_BPF_JIT
af64d2aa 54 select HAVE_C_RECORDMCOUNT
c0c264ae 55 select HAVE_CC_STACKPROTECTOR
5284e1b4 56 select HAVE_CMPXCHG_DOUBLE
9b2a60c4 57 select HAVE_DEBUG_BUGVERBOSE
b69ec42b 58 select HAVE_DEBUG_KMEMLEAK
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59 select HAVE_DMA_API_DEBUG
60 select HAVE_DMA_ATTRS
6ac2104d 61 select HAVE_DMA_CONTIGUOUS
bd7d38db 62 select HAVE_DYNAMIC_FTRACE
50afc33a 63 select HAVE_EFFICIENT_UNALIGNED_ACCESS
af64d2aa 64 select HAVE_FTRACE_MCOUNT_RECORD
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65 select HAVE_FUNCTION_TRACER
66 select HAVE_FUNCTION_GRAPH_TRACER
8c2c3df3 67 select HAVE_GENERIC_DMA_COHERENT
8c2c3df3 68 select HAVE_HW_BREAKPOINT if PERF_EVENTS
8c2c3df3 69 select HAVE_MEMBLOCK
55834a77 70 select HAVE_PATA_PLATFORM
8c2c3df3 71 select HAVE_PERF_EVENTS
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72 select HAVE_PERF_REGS
73 select HAVE_PERF_USER_STACK_DUMP
5e5f6dc1 74 select HAVE_RCU_TABLE_FREE
055b1212 75 select HAVE_SYSCALL_TRACEPOINTS
8c2c3df3 76 select IRQ_DOMAIN
e8557d1f 77 select IRQ_FORCED_THREADING
fea2acaa 78 select MODULES_USE_ELF_RELA
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79 select NO_BOOTMEM
80 select OF
81 select OF_EARLY_FLATTREE
9bf14b7c 82 select OF_RESERVED_MEM
8c2c3df3 83 select PERF_USE_VMALLOC
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84 select POWER_RESET
85 select POWER_SUPPLY
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86 select RTC_LIB
87 select SPARSE_IRQ
7ac57a89 88 select SYSCTL_EXCEPTION_TRACE
6c81fe79 89 select HAVE_CONTEXT_TRACKING
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90 help
91 ARM 64-bit (AArch64) Linux support.
92
93config 64BIT
94 def_bool y
95
96config ARCH_PHYS_ADDR_T_64BIT
97 def_bool y
98
99config MMU
100 def_bool y
101
ce816fa8 102config NO_IOPORT_MAP
d1e6dc91 103 def_bool y if !PCI
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104
105config STACKTRACE_SUPPORT
106 def_bool y
107
108config LOCKDEP_SUPPORT
109 def_bool y
110
111config TRACE_IRQFLAGS_SUPPORT
112 def_bool y
113
c209f799 114config RWSEM_XCHGADD_ALGORITHM
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115 def_bool y
116
117config GENERIC_HWEIGHT
118 def_bool y
119
120config GENERIC_CSUM
121 def_bool y
122
123config GENERIC_CALIBRATE_DELAY
124 def_bool y
125
19e7640d 126config ZONE_DMA
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127 def_bool y
128
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129config HAVE_GENERIC_RCU_GUP
130 def_bool y
131
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132config ARCH_DMA_ADDR_T_64BIT
133 def_bool y
134
135config NEED_DMA_MAP_STATE
136 def_bool y
137
138config NEED_SG_DMA_LENGTH
139 def_bool y
140
141config SWIOTLB
142 def_bool y
143
144config IOMMU_HELPER
145 def_bool SWIOTLB
146
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147config KERNEL_MODE_NEON
148 def_bool y
149
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150config FIX_EARLYCON_MEM
151 def_bool y
152
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153config PGTABLE_LEVELS
154 int
155 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
156 default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48
157 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
158 default 4 if ARM64_4K_PAGES && ARM64_VA_BITS_48
159
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160source "init/Kconfig"
161
162source "kernel/Kconfig.freezer"
163
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164menu "Platform selection"
165
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166config ARCH_EXYNOS
167 bool
168 help
169 This enables support for Samsung Exynos SoC family
170
171config ARCH_EXYNOS7
172 bool "ARMv8 based Samsung Exynos7"
173 select ARCH_EXYNOS
174 select COMMON_CLK_SAMSUNG
175 select HAVE_S3C2410_WATCHDOG if WATCHDOG
176 select HAVE_S3C_RTC if RTC_CLASS
177 select PINCTRL
178 select PINCTRL_EXYNOS
179
180 help
181 This enables support for Samsung Exynos7 SoC family
182
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183config ARCH_FSL_LS2085A
184 bool "Freescale LS2085A SOC"
185 help
186 This enables support for Freescale LS2085A SOC.
187
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188config ARCH_HISI
189 bool "Hisilicon SoC Family"
190 help
191 This enables support for Hisilicon ARMv8 SoC family
192
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193config ARCH_MEDIATEK
194 bool "Mediatek MT65xx & MT81xx ARMv8 SoC"
195 select ARM_GIC
0a233cdf 196 select PINCTRL
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197 help
198 Support for Mediatek MT65xx & MT81xx ARMv8 SoCs
199
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200config ARCH_QCOM
201 bool "Qualcomm Platforms"
202 select PINCTRL
203 help
204 This enables support for the ARMv8 based Qualcomm chipsets.
205
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206config ARCH_SEATTLE
207 bool "AMD Seattle SoC Family"
208 help
209 This enables support for AMD Seattle SOC Family
210
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211config ARCH_TEGRA
212 bool "NVIDIA Tegra SoC Family"
213 select ARCH_HAS_RESET_CONTROLLER
214 select ARCH_REQUIRE_GPIOLIB
215 select CLKDEV_LOOKUP
216 select CLKSRC_MMIO
217 select CLKSRC_OF
218 select GENERIC_CLOCKEVENTS
219 select HAVE_CLK
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220 select PINCTRL
221 select RESET_CONTROLLER
222 help
223 This enables support for the NVIDIA Tegra SoC family.
224
225config ARCH_TEGRA_132_SOC
226 bool "NVIDIA Tegra132 SoC"
227 depends on ARCH_TEGRA
228 select PINCTRL_TEGRA124
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229 select USB_ULPI if USB_PHY
230 select USB_ULPI_VIEWPORT if USB_PHY
231 help
232 Enable support for NVIDIA Tegra132 SoC, based on the Denver
233 ARMv8 CPU. The Tegra132 SoC is similar to the Tegra124 SoC,
234 but contains an NVIDIA Denver CPU complex in place of
235 Tegra124's "4+1" Cortex-A15 CPU complex.
236
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237config ARCH_SPRD
238 bool "Spreadtrum SoC platform"
239 help
240 Support for Spreadtrum ARM based SoCs
241
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242config ARCH_THUNDER
243 bool "Cavium Inc. Thunder SoC Family"
244 help
245 This enables support for Cavium's Thunder Family of SoCs.
246
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247config ARCH_VEXPRESS
248 bool "ARMv8 software model (Versatile Express)"
249 select ARCH_REQUIRE_GPIOLIB
250 select COMMON_CLK_VERSATILE
aa1e8ec1 251 select POWER_RESET_VEXPRESS
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252 select VEXPRESS_CONFIG
253 help
254 This enables support for the ARMv8 software model (Versatile
255 Express).
8c2c3df3 256
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257config ARCH_XGENE
258 bool "AppliedMicro X-Gene SOC Family"
259 help
260 This enables support for AppliedMicro X-Gene SOC Family
261
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262config ARCH_ZYNQMP
263 bool "Xilinx ZynqMP Family"
264 help
265 This enables support for Xilinx ZynqMP Family
266
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267endmenu
268
269menu "Bus support"
270
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271config PCI
272 bool "PCI support"
273 help
274 This feature enables support for PCI bus system. If you say Y
275 here, the kernel will include drivers and infrastructure code
276 to support PCI bus devices.
277
278config PCI_DOMAINS
279 def_bool PCI
280
281config PCI_DOMAINS_GENERIC
282 def_bool PCI
283
284config PCI_SYSCALL
285 def_bool PCI
286
287source "drivers/pci/Kconfig"
288source "drivers/pci/pcie/Kconfig"
289source "drivers/pci/hotplug/Kconfig"
290
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291endmenu
292
293menu "Kernel Features"
294
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295menu "ARM errata workarounds via the alternatives framework"
296
297config ARM64_ERRATUM_826319
298 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
299 default y
300 help
301 This option adds an alternative code sequence to work around ARM
302 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
303 AXI master interface and an L2 cache.
304
305 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
306 and is unable to accept a certain write via this interface, it will
307 not progress on read data presented on the read data channel and the
308 system can deadlock.
309
310 The workaround promotes data cache clean instructions to
311 data cache clean-and-invalidate.
312 Please note that this does not necessarily enable the workaround,
313 as it depends on the alternative framework, which will only patch
314 the kernel if an affected CPU is detected.
315
316 If unsure, say Y.
317
318config ARM64_ERRATUM_827319
319 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
320 default y
321 help
322 This option adds an alternative code sequence to work around ARM
323 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
324 master interface and an L2 cache.
325
326 Under certain conditions this erratum can cause a clean line eviction
327 to occur at the same time as another transaction to the same address
328 on the AMBA 5 CHI interface, which can cause data corruption if the
329 interconnect reorders the two transactions.
330
331 The workaround promotes data cache clean instructions to
332 data cache clean-and-invalidate.
333 Please note that this does not necessarily enable the workaround,
334 as it depends on the alternative framework, which will only patch
335 the kernel if an affected CPU is detected.
336
337 If unsure, say Y.
338
339config ARM64_ERRATUM_824069
340 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
341 default y
342 help
343 This option adds an alternative code sequence to work around ARM
344 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
345 to a coherent interconnect.
346
347 If a Cortex-A53 processor is executing a store or prefetch for
348 write instruction at the same time as a processor in another
349 cluster is executing a cache maintenance operation to the same
350 address, then this erratum might cause a clean cache line to be
351 incorrectly marked as dirty.
352
353 The workaround promotes data cache clean instructions to
354 data cache clean-and-invalidate.
355 Please note that this option does not necessarily enable the
356 workaround, as it depends on the alternative framework, which will
357 only patch the kernel if an affected CPU is detected.
358
359 If unsure, say Y.
360
361config ARM64_ERRATUM_819472
362 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
363 default y
364 help
365 This option adds an alternative code sequence to work around ARM
366 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
367 present when it is connected to a coherent interconnect.
368
369 If the processor is executing a load and store exclusive sequence at
370 the same time as a processor in another cluster is executing a cache
371 maintenance operation to the same address, then this erratum might
372 cause data corruption.
373
374 The workaround promotes data cache clean instructions to
375 data cache clean-and-invalidate.
376 Please note that this does not necessarily enable the workaround,
377 as it depends on the alternative framework, which will only patch
378 the kernel if an affected CPU is detected.
379
380 If unsure, say Y.
381
382config ARM64_ERRATUM_832075
383 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
384 default y
385 help
386 This option adds an alternative code sequence to work around ARM
387 erratum 832075 on Cortex-A57 parts up to r1p2.
388
389 Affected Cortex-A57 parts might deadlock when exclusive load/store
390 instructions to Write-Back memory are mixed with Device loads.
391
392 The workaround is to promote device loads to use Load-Acquire
393 semantics.
394 Please note that this does not necessarily enable the workaround,
395 as it depends on the alternative framework, which will only patch
396 the kernel if an affected CPU is detected.
397
398 If unsure, say Y.
399
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400config ARM64_ERRATUM_845719
401 bool "Cortex-A53: 845719: a load might read incorrect data"
402 depends on COMPAT
403 default y
404 help
405 This option adds an alternative code sequence to work around ARM
406 erratum 845719 on Cortex-A53 parts up to r0p4.
407
408 When running a compat (AArch32) userspace on an affected Cortex-A53
409 part, a load at EL0 from a virtual address that matches the bottom 32
410 bits of the virtual address used by a recent load at (AArch64) EL1
411 might return incorrect data.
412
413 The workaround is to write the contextidr_el1 register on exception
414 return to a 32-bit task.
415 Please note that this does not necessarily enable the workaround,
416 as it depends on the alternative framework, which will only patch
417 the kernel if an affected CPU is detected.
418
419 If unsure, say Y.
420
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421endmenu
422
423
e41ceed0
JL
424choice
425 prompt "Page size"
426 default ARM64_4K_PAGES
427 help
428 Page size (translation granule) configuration.
429
430config ARM64_4K_PAGES
431 bool "4KB"
432 help
433 This feature enables 4KB pages support.
434
8c2c3df3 435config ARM64_64K_PAGES
e41ceed0 436 bool "64KB"
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437 help
438 This feature enables 64KB pages support (4KB by default)
439 allowing only two levels of page tables and faster TLB
440 look-up. AArch32 emulation is not available when this feature
441 is enabled.
442
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443endchoice
444
445choice
446 prompt "Virtual address space size"
447 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
448 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
449 help
450 Allows choosing one of multiple possible virtual address
451 space sizes. The level of translation table is determined by
452 a combination of page size and virtual address space size.
453
454config ARM64_VA_BITS_39
455 bool "39-bit"
456 depends on ARM64_4K_PAGES
457
458config ARM64_VA_BITS_42
459 bool "42-bit"
460 depends on ARM64_64K_PAGES
461
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462config ARM64_VA_BITS_48
463 bool "48-bit"
c79b954b 464
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465endchoice
466
467config ARM64_VA_BITS
468 int
469 default 39 if ARM64_VA_BITS_39
470 default 42 if ARM64_VA_BITS_42
c79b954b 471 default 48 if ARM64_VA_BITS_48
e41ceed0 472
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473config CPU_BIG_ENDIAN
474 bool "Build big-endian kernel"
475 help
476 Say Y if you plan on running a kernel in big-endian mode.
477
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478config SMP
479 bool "Symmetric Multi-Processing"
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480 help
481 This enables support for systems with more than one CPU. If
482 you say N here, the kernel will run on single and
483 multiprocessor machines, but will use only one CPU of a
484 multiprocessor machine. If you say Y here, the kernel will run
485 on many, but not all, single processor machines. On a single
486 processor machine, the kernel will run faster if you say N
487 here.
488
489 If you don't know what to do here, say N.
490
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491config SCHED_MC
492 bool "Multi-core scheduler support"
493 depends on SMP
494 help
495 Multi-core scheduler support improves the CPU scheduler's decision
496 making when dealing with multi-core CPU chips at a cost of slightly
497 increased overhead in some places. If unsure say N here.
498
499config SCHED_SMT
500 bool "SMT scheduler support"
501 depends on SMP
502 help
503 Improves the CPU scheduler's decision making when dealing with
504 MultiThreading at a cost of slightly increased overhead in some
505 places. If unsure say N here.
506
8c2c3df3 507config NR_CPUS
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508 int "Maximum number of CPUs (2-4096)"
509 range 2 4096
8c2c3df3 510 depends on SMP
15942853 511 # These have to remain sorted largest to smallest
e3672649 512 default "64"
8c2c3df3 513
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514config HOTPLUG_CPU
515 bool "Support for hot-pluggable CPUs"
516 depends on SMP
517 help
518 Say Y here to experiment with turning CPUs off and on. CPUs
519 can be controlled through /sys/devices/system/cpu.
520
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521source kernel/Kconfig.preempt
522
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523config UP_LATE_INIT
524 def_bool y
525 depends on !SMP
526
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527config HZ
528 int
529 default 100
530
531config ARCH_HAS_HOLES_MEMORYMODEL
532 def_bool y if SPARSEMEM
533
534config ARCH_SPARSEMEM_ENABLE
535 def_bool y
536 select SPARSEMEM_VMEMMAP_ENABLE
537
538config ARCH_SPARSEMEM_DEFAULT
539 def_bool ARCH_SPARSEMEM_ENABLE
540
541config ARCH_SELECT_MEMORY_MODEL
542 def_bool ARCH_SPARSEMEM_ENABLE
543
544config HAVE_ARCH_PFN_VALID
545 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
546
547config HW_PERF_EVENTS
548 bool "Enable hardware performance counter support for perf events"
549 depends on PERF_EVENTS
550 default y
551 help
552 Enable hardware performance counter support for perf events. If
553 disabled, perf events will use software events only.
554
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555config SYS_SUPPORTS_HUGETLBFS
556 def_bool y
557
558config ARCH_WANT_GENERAL_HUGETLB
559 def_bool y
560
561config ARCH_WANT_HUGE_PMD_SHARE
562 def_bool y if !ARM64_64K_PAGES
563
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564config HAVE_ARCH_TRANSPARENT_HUGEPAGE
565 def_bool y
566
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567config ARCH_HAS_CACHE_LINE_SIZE
568 def_bool y
569
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570source "mm/Kconfig"
571
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572config SECCOMP
573 bool "Enable seccomp to safely compute untrusted bytecode"
574 ---help---
575 This kernel feature is useful for number crunching applications
576 that may need to compute untrusted bytecode during their
577 execution. By using pipes or other transports made available to
578 the process as file descriptors supporting the read/write
579 syscalls, it's possible to isolate those applications in
580 their own address space using seccomp. Once seccomp is
581 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
582 and the task is only allowed to execute a few safe syscalls
583 defined by each seccomp mode.
584
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585config XEN_DOM0
586 def_bool y
587 depends on XEN
588
589config XEN
c2ba1f7d 590 bool "Xen guest support on ARM64"
aa42aa13 591 depends on ARM64 && OF
83862ccf 592 select SWIOTLB_XEN
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593 help
594 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
595
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596config FORCE_MAX_ZONEORDER
597 int
598 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
599 default "11"
600
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601menuconfig ARMV8_DEPRECATED
602 bool "Emulate deprecated/obsolete ARMv8 instructions"
603 depends on COMPAT
604 help
605 Legacy software support may require certain instructions
606 that have been deprecated or obsoleted in the architecture.
607
608 Enable this config to enable selective emulation of these
609 features.
610
611 If unsure, say Y
612
613if ARMV8_DEPRECATED
614
615config SWP_EMULATION
616 bool "Emulate SWP/SWPB instructions"
617 help
618 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
619 they are always undefined. Say Y here to enable software
620 emulation of these instructions for userspace using LDXR/STXR.
621
622 In some older versions of glibc [<=2.8] SWP is used during futex
623 trylock() operations with the assumption that the code will not
624 be preempted. This invalid assumption may be more likely to fail
625 with SWP emulation enabled, leading to deadlock of the user
626 application.
627
628 NOTE: when accessing uncached shared regions, LDXR/STXR rely
629 on an external transaction monitoring block called a global
630 monitor to maintain update atomicity. If your system does not
631 implement a global monitor, this option can cause programs that
632 perform SWP operations to uncached memory to deadlock.
633
634 If unsure, say Y
635
636config CP15_BARRIER_EMULATION
637 bool "Emulate CP15 Barrier instructions"
638 help
639 The CP15 barrier instructions - CP15ISB, CP15DSB, and
640 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
641 strongly recommended to use the ISB, DSB, and DMB
642 instructions instead.
643
644 Say Y here to enable software emulation of these
645 instructions for AArch32 userspace code. When this option is
646 enabled, CP15 barrier usage is traced which can help
647 identify software that needs updating.
648
649 If unsure, say Y
650
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651config SETEND_EMULATION
652 bool "Emulate SETEND instruction"
653 help
654 The SETEND instruction alters the data-endianness of the
655 AArch32 EL0, and is deprecated in ARMv8.
656
657 Say Y here to enable software emulation of the instruction
658 for AArch32 userspace code.
659
660 Note: All the cpus on the system must have mixed endian support at EL0
661 for this feature to be enabled. If a new CPU - which doesn't support mixed
662 endian - is hotplugged in after this feature has been enabled, there could
663 be unexpected results in the applications.
664
665 If unsure, say Y
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666endif
667
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668endmenu
669
670menu "Boot options"
671
672config CMDLINE
673 string "Default kernel command string"
674 default ""
675 help
676 Provide a set of default command-line options at build time by
677 entering them here. As a minimum, you should specify the the
678 root device (e.g. root=/dev/nfs).
679
680config CMDLINE_FORCE
681 bool "Always use the default kernel command string"
682 help
683 Always use the default kernel command string, even if the boot
684 loader passes other arguments to the kernel.
685 This is useful if you cannot or don't want to change the
686 command-line options your boot loader passes to the kernel.
687
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688config EFI_STUB
689 bool
690
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691config EFI
692 bool "UEFI runtime support"
693 depends on OF && !CPU_BIG_ENDIAN
694 select LIBFDT
695 select UCS2_STRING
696 select EFI_PARAMS_FROM_FDT
e15dd494 697 select EFI_RUNTIME_WRAPPERS
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698 select EFI_STUB
699 select EFI_ARMSTUB
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700 default y
701 help
702 This option provides support for runtime services provided
703 by UEFI firmware (such as non-volatile variables, realtime
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704 clock, and platform reset). A UEFI stub is also provided to
705 allow the kernel to be booted as an EFI application. This
706 is only useful on systems that have UEFI firmware.
f84d0275 707
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708config DMI
709 bool "Enable support for SMBIOS (DMI) tables"
710 depends on EFI
711 default y
712 help
713 This enables SMBIOS/DMI feature for systems.
714
715 This option is only useful on systems that have UEFI firmware.
716 However, even with this option, the resultant kernel should
717 continue to boot on existing non-UEFI platforms.
718
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719endmenu
720
721menu "Userspace binary formats"
722
723source "fs/Kconfig.binfmt"
724
725config COMPAT
726 bool "Kernel support for 32-bit EL0"
a8fcd8b1 727 depends on !ARM64_64K_PAGES || EXPERT
8c2c3df3 728 select COMPAT_BINFMT_ELF
af1839eb 729 select HAVE_UID16
84b9e9b4 730 select OLD_SIGSUSPEND3
51682036 731 select COMPAT_OLD_SIGACTION
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732 help
733 This option enables support for a 32-bit EL0 running under a 64-bit
734 kernel at EL1. AArch32-specific components such as system calls,
735 the user helper functions, VFP support and the ptrace interface are
736 handled appropriately by the kernel.
737
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738 If you also enabled CONFIG_ARM64_64K_PAGES, please be aware that you
739 will only be able to execute AArch32 binaries that were compiled with
740 64k aligned segments.
741
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742 If you want to execute 32-bit userspace applications, say Y.
743
744config SYSVIPC_COMPAT
745 def_bool y
746 depends on COMPAT && SYSVIPC
747
748endmenu
749
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750menu "Power management options"
751
752source "kernel/power/Kconfig"
753
754config ARCH_SUSPEND_POSSIBLE
755 def_bool y
756
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757endmenu
758
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759menu "CPU Power Management"
760
761source "drivers/cpuidle/Kconfig"
762
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763source "drivers/cpufreq/Kconfig"
764
765endmenu
766
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767source "net/Kconfig"
768
769source "drivers/Kconfig"
770
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771source "drivers/firmware/Kconfig"
772
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773source "drivers/acpi/Kconfig"
774
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775source "fs/Kconfig"
776
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777source "arch/arm64/kvm/Kconfig"
778
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779source "arch/arm64/Kconfig.debug"
780
781source "security/Kconfig"
782
783source "crypto/Kconfig"
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784if CRYPTO
785source "arch/arm64/crypto/Kconfig"
786endif
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787
788source "lib/Kconfig"