Merge tag 'v3.20-next-arm64' of https://github.com/mbgg/linux-mediatek into next...
[linux-2.6-block.git] / arch / arm64 / Kconfig
CommitLineData
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1config ARM64
2 def_bool y
92980405 3 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
8c2c3df3 4 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
957e3fac 5 select ARCH_HAS_GCOV_PROFILE_ALL
308c09f1 6 select ARCH_HAS_SG_CHAIN
1f85008e 7 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
c63c8700 8 select ARCH_USE_CMPXCHG_LOCKREF
4badad35 9 select ARCH_SUPPORTS_ATOMIC_RMW
9170100e 10 select ARCH_WANT_OPTIONAL_GPIOLIB
6212a512 11 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
b6f35981 12 select ARCH_WANT_FRAME_POINTERS
25c92a37 13 select ARM_AMBA
1aee5d7a 14 select ARM_ARCH_TIMER
c4188edc 15 select ARM_GIC
875cbf3e 16 select AUDIT_ARCH_COMPAT_GENERIC
853a33ce 17 select ARM_GIC_V2M if PCI_MSI
021f6537 18 select ARM_GIC_V3
19812729 19 select ARM_GIC_V3_ITS if PCI_MSI
adace895 20 select BUILDTIME_EXTABLE_SORT
db2789b5 21 select CLONE_BACKWARDS
7ca2ef33 22 select COMMON_CLK
166936ba 23 select CPU_PM if (SUSPEND || CPU_IDLE)
7bc13fd3 24 select DCACHE_WORD_ACCESS
d4932f9e 25 select GENERIC_ALLOCATOR
8c2c3df3 26 select GENERIC_CLOCKEVENTS
1f85008e 27 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
3be1a5c4 28 select GENERIC_CPU_AUTOPROBE
bf4b558e 29 select GENERIC_EARLY_IOREMAP
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30 select GENERIC_IRQ_PROBE
31 select GENERIC_IRQ_SHOW
cb61f676 32 select GENERIC_PCI_IOMAP
65cd4f6c 33 select GENERIC_SCHED_CLOCK
8c2c3df3 34 select GENERIC_SMP_IDLE_THREAD
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35 select GENERIC_STRNCPY_FROM_USER
36 select GENERIC_STRNLEN_USER
8c2c3df3 37 select GENERIC_TIME_VSYSCALL
a1ddc74a 38 select HANDLE_DOMAIN_IRQ
8c2c3df3 39 select HARDIRQS_SW_RESEND
5284e1b4 40 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
875cbf3e 41 select HAVE_ARCH_AUDITSYSCALL
9732cafd 42 select HAVE_ARCH_JUMP_LABEL
9529247d 43 select HAVE_ARCH_KGDB
a1ae65b2 44 select HAVE_ARCH_SECCOMP_FILTER
8c2c3df3 45 select HAVE_ARCH_TRACEHOOK
e54bcde3 46 select HAVE_BPF_JIT
af64d2aa 47 select HAVE_C_RECORDMCOUNT
c0c264ae 48 select HAVE_CC_STACKPROTECTOR
5284e1b4 49 select HAVE_CMPXCHG_DOUBLE
9b2a60c4 50 select HAVE_DEBUG_BUGVERBOSE
b69ec42b 51 select HAVE_DEBUG_KMEMLEAK
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52 select HAVE_DMA_API_DEBUG
53 select HAVE_DMA_ATTRS
6ac2104d 54 select HAVE_DMA_CONTIGUOUS
bd7d38db 55 select HAVE_DYNAMIC_FTRACE
50afc33a 56 select HAVE_EFFICIENT_UNALIGNED_ACCESS
af64d2aa 57 select HAVE_FTRACE_MCOUNT_RECORD
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58 select HAVE_FUNCTION_TRACER
59 select HAVE_FUNCTION_GRAPH_TRACER
8c2c3df3 60 select HAVE_GENERIC_DMA_COHERENT
8c2c3df3 61 select HAVE_HW_BREAKPOINT if PERF_EVENTS
8c2c3df3 62 select HAVE_MEMBLOCK
55834a77 63 select HAVE_PATA_PLATFORM
8c2c3df3 64 select HAVE_PERF_EVENTS
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65 select HAVE_PERF_REGS
66 select HAVE_PERF_USER_STACK_DUMP
5e5f6dc1 67 select HAVE_RCU_TABLE_FREE
055b1212 68 select HAVE_SYSCALL_TRACEPOINTS
8c2c3df3 69 select IRQ_DOMAIN
fea2acaa 70 select MODULES_USE_ELF_RELA
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71 select NO_BOOTMEM
72 select OF
73 select OF_EARLY_FLATTREE
9bf14b7c 74 select OF_RESERVED_MEM
8c2c3df3 75 select PERF_USE_VMALLOC
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76 select POWER_RESET
77 select POWER_SUPPLY
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78 select RTC_LIB
79 select SPARSE_IRQ
7ac57a89 80 select SYSCTL_EXCEPTION_TRACE
6c81fe79 81 select HAVE_CONTEXT_TRACKING
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82 help
83 ARM 64-bit (AArch64) Linux support.
84
85config 64BIT
86 def_bool y
87
88config ARCH_PHYS_ADDR_T_64BIT
89 def_bool y
90
91config MMU
92 def_bool y
93
ce816fa8 94config NO_IOPORT_MAP
d1e6dc91 95 def_bool y if !PCI
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96
97config STACKTRACE_SUPPORT
98 def_bool y
99
100config LOCKDEP_SUPPORT
101 def_bool y
102
103config TRACE_IRQFLAGS_SUPPORT
104 def_bool y
105
c209f799 106config RWSEM_XCHGADD_ALGORITHM
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107 def_bool y
108
109config GENERIC_HWEIGHT
110 def_bool y
111
112config GENERIC_CSUM
113 def_bool y
114
115config GENERIC_CALIBRATE_DELAY
116 def_bool y
117
19e7640d 118config ZONE_DMA
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119 def_bool y
120
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121config HAVE_GENERIC_RCU_GUP
122 def_bool y
123
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124config ARCH_DMA_ADDR_T_64BIT
125 def_bool y
126
127config NEED_DMA_MAP_STATE
128 def_bool y
129
130config NEED_SG_DMA_LENGTH
131 def_bool y
132
133config SWIOTLB
134 def_bool y
135
136config IOMMU_HELPER
137 def_bool SWIOTLB
138
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139config KERNEL_MODE_NEON
140 def_bool y
141
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142config FIX_EARLYCON_MEM
143 def_bool y
144
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145source "init/Kconfig"
146
147source "kernel/Kconfig.freezer"
148
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149menu "Platform selection"
150
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151config ARCH_EXYNOS
152 bool
153 help
154 This enables support for Samsung Exynos SoC family
155
156config ARCH_EXYNOS7
157 bool "ARMv8 based Samsung Exynos7"
158 select ARCH_EXYNOS
159 select COMMON_CLK_SAMSUNG
160 select HAVE_S3C2410_WATCHDOG if WATCHDOG
161 select HAVE_S3C_RTC if RTC_CLASS
162 select PINCTRL
163 select PINCTRL_EXYNOS
164
165 help
166 This enables support for Samsung Exynos7 SoC family
167
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168config ARCH_MEDIATEK
169 bool "Mediatek MT65xx & MT81xx ARMv8 SoC"
170 select ARM_GIC
171 help
172 Support for Mediatek MT65xx & MT81xx ARMv8 SoCs
173
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174config ARCH_SEATTLE
175 bool "AMD Seattle SoC Family"
176 help
177 This enables support for AMD Seattle SOC Family
178
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179config ARCH_TEGRA
180 bool "NVIDIA Tegra SoC Family"
181 select ARCH_HAS_RESET_CONTROLLER
182 select ARCH_REQUIRE_GPIOLIB
183 select CLKDEV_LOOKUP
184 select CLKSRC_MMIO
185 select CLKSRC_OF
186 select GENERIC_CLOCKEVENTS
187 select HAVE_CLK
188 select HAVE_SMP
189 select PINCTRL
190 select RESET_CONTROLLER
191 help
192 This enables support for the NVIDIA Tegra SoC family.
193
194config ARCH_TEGRA_132_SOC
195 bool "NVIDIA Tegra132 SoC"
196 depends on ARCH_TEGRA
197 select PINCTRL_TEGRA124
198 select USB_ARCH_HAS_EHCI if USB_SUPPORT
199 select USB_ULPI if USB_PHY
200 select USB_ULPI_VIEWPORT if USB_PHY
201 help
202 Enable support for NVIDIA Tegra132 SoC, based on the Denver
203 ARMv8 CPU. The Tegra132 SoC is similar to the Tegra124 SoC,
204 but contains an NVIDIA Denver CPU complex in place of
205 Tegra124's "4+1" Cortex-A15 CPU complex.
206
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207config ARCH_FSL_LS2085A
208 bool "Freescale LS2085A SOC"
209 help
210 This enables support for Freescale LS2085A SOC.
211
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212config ARCH_THUNDER
213 bool "Cavium Inc. Thunder SoC Family"
214 help
215 This enables support for Cavium's Thunder Family of SoCs.
216
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217config ARCH_VEXPRESS
218 bool "ARMv8 software model (Versatile Express)"
219 select ARCH_REQUIRE_GPIOLIB
220 select COMMON_CLK_VERSATILE
aa1e8ec1 221 select POWER_RESET_VEXPRESS
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222 select VEXPRESS_CONFIG
223 help
224 This enables support for the ARMv8 software model (Versatile
225 Express).
8c2c3df3 226
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227config ARCH_XGENE
228 bool "AppliedMicro X-Gene SOC Family"
229 help
230 This enables support for AppliedMicro X-Gene SOC Family
231
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232endmenu
233
234menu "Bus support"
235
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236config PCI
237 bool "PCI support"
238 help
239 This feature enables support for PCI bus system. If you say Y
240 here, the kernel will include drivers and infrastructure code
241 to support PCI bus devices.
242
243config PCI_DOMAINS
244 def_bool PCI
245
246config PCI_DOMAINS_GENERIC
247 def_bool PCI
248
249config PCI_SYSCALL
250 def_bool PCI
251
252source "drivers/pci/Kconfig"
253source "drivers/pci/pcie/Kconfig"
254source "drivers/pci/hotplug/Kconfig"
255
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256endmenu
257
258menu "Kernel Features"
259
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260menu "ARM errata workarounds via the alternatives framework"
261
262config ARM64_ERRATUM_826319
263 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
264 default y
265 help
266 This option adds an alternative code sequence to work around ARM
267 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
268 AXI master interface and an L2 cache.
269
270 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
271 and is unable to accept a certain write via this interface, it will
272 not progress on read data presented on the read data channel and the
273 system can deadlock.
274
275 The workaround promotes data cache clean instructions to
276 data cache clean-and-invalidate.
277 Please note that this does not necessarily enable the workaround,
278 as it depends on the alternative framework, which will only patch
279 the kernel if an affected CPU is detected.
280
281 If unsure, say Y.
282
283config ARM64_ERRATUM_827319
284 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
285 default y
286 help
287 This option adds an alternative code sequence to work around ARM
288 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
289 master interface and an L2 cache.
290
291 Under certain conditions this erratum can cause a clean line eviction
292 to occur at the same time as another transaction to the same address
293 on the AMBA 5 CHI interface, which can cause data corruption if the
294 interconnect reorders the two transactions.
295
296 The workaround promotes data cache clean instructions to
297 data cache clean-and-invalidate.
298 Please note that this does not necessarily enable the workaround,
299 as it depends on the alternative framework, which will only patch
300 the kernel if an affected CPU is detected.
301
302 If unsure, say Y.
303
304config ARM64_ERRATUM_824069
305 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
306 default y
307 help
308 This option adds an alternative code sequence to work around ARM
309 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
310 to a coherent interconnect.
311
312 If a Cortex-A53 processor is executing a store or prefetch for
313 write instruction at the same time as a processor in another
314 cluster is executing a cache maintenance operation to the same
315 address, then this erratum might cause a clean cache line to be
316 incorrectly marked as dirty.
317
318 The workaround promotes data cache clean instructions to
319 data cache clean-and-invalidate.
320 Please note that this option does not necessarily enable the
321 workaround, as it depends on the alternative framework, which will
322 only patch the kernel if an affected CPU is detected.
323
324 If unsure, say Y.
325
326config ARM64_ERRATUM_819472
327 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
328 default y
329 help
330 This option adds an alternative code sequence to work around ARM
331 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
332 present when it is connected to a coherent interconnect.
333
334 If the processor is executing a load and store exclusive sequence at
335 the same time as a processor in another cluster is executing a cache
336 maintenance operation to the same address, then this erratum might
337 cause data corruption.
338
339 The workaround promotes data cache clean instructions to
340 data cache clean-and-invalidate.
341 Please note that this does not necessarily enable the workaround,
342 as it depends on the alternative framework, which will only patch
343 the kernel if an affected CPU is detected.
344
345 If unsure, say Y.
346
347config ARM64_ERRATUM_832075
348 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
349 default y
350 help
351 This option adds an alternative code sequence to work around ARM
352 erratum 832075 on Cortex-A57 parts up to r1p2.
353
354 Affected Cortex-A57 parts might deadlock when exclusive load/store
355 instructions to Write-Back memory are mixed with Device loads.
356
357 The workaround is to promote device loads to use Load-Acquire
358 semantics.
359 Please note that this does not necessarily enable the workaround,
360 as it depends on the alternative framework, which will only patch
361 the kernel if an affected CPU is detected.
362
363 If unsure, say Y.
364
365endmenu
366
367
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368choice
369 prompt "Page size"
370 default ARM64_4K_PAGES
371 help
372 Page size (translation granule) configuration.
373
374config ARM64_4K_PAGES
375 bool "4KB"
376 help
377 This feature enables 4KB pages support.
378
8c2c3df3 379config ARM64_64K_PAGES
e41ceed0 380 bool "64KB"
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381 help
382 This feature enables 64KB pages support (4KB by default)
383 allowing only two levels of page tables and faster TLB
384 look-up. AArch32 emulation is not available when this feature
385 is enabled.
386
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387endchoice
388
389choice
390 prompt "Virtual address space size"
391 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
392 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
393 help
394 Allows choosing one of multiple possible virtual address
395 space sizes. The level of translation table is determined by
396 a combination of page size and virtual address space size.
397
398config ARM64_VA_BITS_39
399 bool "39-bit"
400 depends on ARM64_4K_PAGES
401
402config ARM64_VA_BITS_42
403 bool "42-bit"
404 depends on ARM64_64K_PAGES
405
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406config ARM64_VA_BITS_48
407 bool "48-bit"
04f905a9 408 depends on !ARM_SMMU
c79b954b 409
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410endchoice
411
412config ARM64_VA_BITS
413 int
414 default 39 if ARM64_VA_BITS_39
415 default 42 if ARM64_VA_BITS_42
c79b954b 416 default 48 if ARM64_VA_BITS_48
e41ceed0 417
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418config ARM64_PGTABLE_LEVELS
419 int
420 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
383c2799 421 default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48
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422 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
423 default 4 if ARM64_4K_PAGES && ARM64_VA_BITS_48
c79b954b 424
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425config CPU_BIG_ENDIAN
426 bool "Build big-endian kernel"
427 help
428 Say Y if you plan on running a kernel in big-endian mode.
429
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430config SMP
431 bool "Symmetric Multi-Processing"
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432 help
433 This enables support for systems with more than one CPU. If
434 you say N here, the kernel will run on single and
435 multiprocessor machines, but will use only one CPU of a
436 multiprocessor machine. If you say Y here, the kernel will run
437 on many, but not all, single processor machines. On a single
438 processor machine, the kernel will run faster if you say N
439 here.
440
441 If you don't know what to do here, say N.
442
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443config SCHED_MC
444 bool "Multi-core scheduler support"
445 depends on SMP
446 help
447 Multi-core scheduler support improves the CPU scheduler's decision
448 making when dealing with multi-core CPU chips at a cost of slightly
449 increased overhead in some places. If unsure say N here.
450
451config SCHED_SMT
452 bool "SMT scheduler support"
453 depends on SMP
454 help
455 Improves the CPU scheduler's decision making when dealing with
456 MultiThreading at a cost of slightly increased overhead in some
457 places. If unsure say N here.
458
8c2c3df3 459config NR_CPUS
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460 int "Maximum number of CPUs (2-64)"
461 range 2 64
8c2c3df3 462 depends on SMP
15942853 463 # These have to remain sorted largest to smallest
e3672649 464 default "64"
8c2c3df3 465
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466config HOTPLUG_CPU
467 bool "Support for hot-pluggable CPUs"
468 depends on SMP
469 help
470 Say Y here to experiment with turning CPUs off and on. CPUs
471 can be controlled through /sys/devices/system/cpu.
472
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473source kernel/Kconfig.preempt
474
475config HZ
476 int
477 default 100
478
479config ARCH_HAS_HOLES_MEMORYMODEL
480 def_bool y if SPARSEMEM
481
482config ARCH_SPARSEMEM_ENABLE
483 def_bool y
484 select SPARSEMEM_VMEMMAP_ENABLE
485
486config ARCH_SPARSEMEM_DEFAULT
487 def_bool ARCH_SPARSEMEM_ENABLE
488
489config ARCH_SELECT_MEMORY_MODEL
490 def_bool ARCH_SPARSEMEM_ENABLE
491
492config HAVE_ARCH_PFN_VALID
493 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
494
495config HW_PERF_EVENTS
496 bool "Enable hardware performance counter support for perf events"
497 depends on PERF_EVENTS
498 default y
499 help
500 Enable hardware performance counter support for perf events. If
501 disabled, perf events will use software events only.
502
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503config SYS_SUPPORTS_HUGETLBFS
504 def_bool y
505
506config ARCH_WANT_GENERAL_HUGETLB
507 def_bool y
508
509config ARCH_WANT_HUGE_PMD_SHARE
510 def_bool y if !ARM64_64K_PAGES
511
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512config HAVE_ARCH_TRANSPARENT_HUGEPAGE
513 def_bool y
514
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515config ARCH_HAS_CACHE_LINE_SIZE
516 def_bool y
517
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518source "mm/Kconfig"
519
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520config SECCOMP
521 bool "Enable seccomp to safely compute untrusted bytecode"
522 ---help---
523 This kernel feature is useful for number crunching applications
524 that may need to compute untrusted bytecode during their
525 execution. By using pipes or other transports made available to
526 the process as file descriptors supporting the read/write
527 syscalls, it's possible to isolate those applications in
528 their own address space using seccomp. Once seccomp is
529 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
530 and the task is only allowed to execute a few safe syscalls
531 defined by each seccomp mode.
532
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533config XEN_DOM0
534 def_bool y
535 depends on XEN
536
537config XEN
c2ba1f7d 538 bool "Xen guest support on ARM64"
aa42aa13 539 depends on ARM64 && OF
83862ccf 540 select SWIOTLB_XEN
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541 help
542 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
543
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544config FORCE_MAX_ZONEORDER
545 int
546 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
547 default "11"
548
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549menuconfig ARMV8_DEPRECATED
550 bool "Emulate deprecated/obsolete ARMv8 instructions"
551 depends on COMPAT
552 help
553 Legacy software support may require certain instructions
554 that have been deprecated or obsoleted in the architecture.
555
556 Enable this config to enable selective emulation of these
557 features.
558
559 If unsure, say Y
560
561if ARMV8_DEPRECATED
562
563config SWP_EMULATION
564 bool "Emulate SWP/SWPB instructions"
565 help
566 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
567 they are always undefined. Say Y here to enable software
568 emulation of these instructions for userspace using LDXR/STXR.
569
570 In some older versions of glibc [<=2.8] SWP is used during futex
571 trylock() operations with the assumption that the code will not
572 be preempted. This invalid assumption may be more likely to fail
573 with SWP emulation enabled, leading to deadlock of the user
574 application.
575
576 NOTE: when accessing uncached shared regions, LDXR/STXR rely
577 on an external transaction monitoring block called a global
578 monitor to maintain update atomicity. If your system does not
579 implement a global monitor, this option can cause programs that
580 perform SWP operations to uncached memory to deadlock.
581
582 If unsure, say Y
583
584config CP15_BARRIER_EMULATION
585 bool "Emulate CP15 Barrier instructions"
586 help
587 The CP15 barrier instructions - CP15ISB, CP15DSB, and
588 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
589 strongly recommended to use the ISB, DSB, and DMB
590 instructions instead.
591
592 Say Y here to enable software emulation of these
593 instructions for AArch32 userspace code. When this option is
594 enabled, CP15 barrier usage is traced which can help
595 identify software that needs updating.
596
597 If unsure, say Y
598
599endif
600
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601endmenu
602
603menu "Boot options"
604
605config CMDLINE
606 string "Default kernel command string"
607 default ""
608 help
609 Provide a set of default command-line options at build time by
610 entering them here. As a minimum, you should specify the the
611 root device (e.g. root=/dev/nfs).
612
613config CMDLINE_FORCE
614 bool "Always use the default kernel command string"
615 help
616 Always use the default kernel command string, even if the boot
617 loader passes other arguments to the kernel.
618 This is useful if you cannot or don't want to change the
619 command-line options your boot loader passes to the kernel.
620
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621config EFI_STUB
622 bool
623
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624config EFI
625 bool "UEFI runtime support"
626 depends on OF && !CPU_BIG_ENDIAN
627 select LIBFDT
628 select UCS2_STRING
629 select EFI_PARAMS_FROM_FDT
e15dd494 630 select EFI_RUNTIME_WRAPPERS
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631 select EFI_STUB
632 select EFI_ARMSTUB
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633 default y
634 help
635 This option provides support for runtime services provided
636 by UEFI firmware (such as non-volatile variables, realtime
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637 clock, and platform reset). A UEFI stub is also provided to
638 allow the kernel to be booted as an EFI application. This
639 is only useful on systems that have UEFI firmware.
f84d0275 640
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641config DMI
642 bool "Enable support for SMBIOS (DMI) tables"
643 depends on EFI
644 default y
645 help
646 This enables SMBIOS/DMI feature for systems.
647
648 This option is only useful on systems that have UEFI firmware.
649 However, even with this option, the resultant kernel should
650 continue to boot on existing non-UEFI platforms.
651
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652endmenu
653
654menu "Userspace binary formats"
655
656source "fs/Kconfig.binfmt"
657
658config COMPAT
659 bool "Kernel support for 32-bit EL0"
660 depends on !ARM64_64K_PAGES
661 select COMPAT_BINFMT_ELF
af1839eb 662 select HAVE_UID16
84b9e9b4 663 select OLD_SIGSUSPEND3
51682036 664 select COMPAT_OLD_SIGACTION
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665 help
666 This option enables support for a 32-bit EL0 running under a 64-bit
667 kernel at EL1. AArch32-specific components such as system calls,
668 the user helper functions, VFP support and the ptrace interface are
669 handled appropriately by the kernel.
670
671 If you want to execute 32-bit userspace applications, say Y.
672
673config SYSVIPC_COMPAT
674 def_bool y
675 depends on COMPAT && SYSVIPC
676
677endmenu
678
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679menu "Power management options"
680
681source "kernel/power/Kconfig"
682
683config ARCH_SUSPEND_POSSIBLE
684 def_bool y
685
686config ARM64_CPU_SUSPEND
687 def_bool PM_SLEEP
688
689endmenu
690
1307220d
LP
691menu "CPU Power Management"
692
693source "drivers/cpuidle/Kconfig"
694
52e7e816
RH
695source "drivers/cpufreq/Kconfig"
696
697endmenu
698
8c2c3df3
CM
699source "net/Kconfig"
700
701source "drivers/Kconfig"
702
f84d0275
MS
703source "drivers/firmware/Kconfig"
704
8c2c3df3
CM
705source "fs/Kconfig"
706
c3eb5b14
MZ
707source "arch/arm64/kvm/Kconfig"
708
8c2c3df3
CM
709source "arch/arm64/Kconfig.debug"
710
711source "security/Kconfig"
712
713source "crypto/Kconfig"
2c98833a
AB
714if CRYPTO
715source "arch/arm64/crypto/Kconfig"
716endif
8c2c3df3
CM
717
718source "lib/Kconfig"