[linux-2.6-block.git] / arch / arm / plat-versatile / platsmp.c

/*
 *  linux/arch/arm/plat-versatile/platsmp.c
 *
 *  Copyright (C) 2002 ARM Ltd.
 *  All Rights Reserved
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
#include <linux/init.h>
#include <linux/errno.h>
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/jiffies.h>
#include <linux/smp.h>

#include <asm/cacheflush.h>
#include <asm/smp_plat.h>

#include <plat/platsmp.h>

/*
 * Write pen_release in a way that is guaranteed to be visible to all
 * observers, irrespective of whether they're taking part in coherency
 * or not.  This is necessary for the hotplug code to work reliably.
 */
static void write_pen_release(int val)
{
	pen_release = val;
	smp_wmb();
	sync_cache_w(&pen_release);
}

static DEFINE_SPINLOCK(boot_lock);

void versatile_secondary_init(unsigned int cpu)
{
	/*
	 * let the primary processor know we're out of the
	 * pen, then head off into the C entry point
	 */
	write_pen_release(-1);

	/*
	 * Synchronise with the boot thread.
	 */
	spin_lock(&boot_lock);
	spin_unlock(&boot_lock);
}

int versatile_boot_secondary(unsigned int cpu, struct task_struct *idle)
{
	unsigned long timeout;

	/*
	 * Set synchronisation state between this boot processor
	 * and the secondary one
	 */
	spin_lock(&boot_lock);

	/*
	 * This is really belt and braces; we hold unintended secondary
	 * CPUs in the holding pen until we're ready for them.  However,
	 * since we haven't sent them a soft interrupt, they shouldn't
	 * be there.
	 */
	write_pen_release(cpu_logical_map(cpu));

	/*
	 * Send the secondary CPU a soft interrupt, thereby causing
	 * the boot monitor to read the system wide flags register,
	 * and branch to the address found there.
	 */
	arch_send_wakeup_ipi_mask(cpumask_of(cpu));

	timeout = jiffies + (1 * HZ);
	while (time_before(jiffies, timeout)) {
		smp_rmb();
		if (pen_release == -1)
			break;

		udelay(10);
	}

	/*
	 * now the secondary core is starting up let it run its
	 * calibrations, then wait for it to finish
	 */
	spin_unlock(&boot_lock);

	return pen_release != -1 ? -ENOSYS : 0;
}
Commit	Line	Data
0462b447 RK	1	/*
	2	* linux/arch/arm/plat-versatile/platsmp.c
	3	*
	4	* Copyright (C) 2002 ARM Ltd.
	5	* All Rights Reserved
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*/
	11	#include <linux/init.h>
	12	#include <linux/errno.h>
	13	#include <linux/delay.h>
	14	#include <linux/device.h>
	15	#include <linux/jiffies.h>
	16	#include <linux/smp.h>
	17
	18	#include <asm/cacheflush.h>
eb50439b	19	#include <asm/smp_plat.h>
0462b447	20
4091af6b BD	21	#include <plat/platsmp.h>
4091af6b BD	22
0462b447 RK	23	/*
	24	* Write pen_release in a way that is guaranteed to be visible to all
	25	* observers, irrespective of whether they're taking part in coherency
	26	* or not. This is necessary for the hotplug code to work reliably.
	27	*/
8bd26e3a	28	static void write_pen_release(int val)
0462b447 RK	29	{
	30	pen_release = val;
	31	smp_wmb();
f45913fd	32	sync_cache_w(&pen_release);
0462b447 RK	33	}
	34
	35	static DEFINE_SPINLOCK(boot_lock);
	36
8bd26e3a	37	void versatile_secondary_init(unsigned int cpu)
0462b447	38	{
0462b447 RK	39	/*
	40	* let the primary processor know we're out of the
	41	* pen, then head off into the C entry point
	42	*/
	43	write_pen_release(-1);
	44
	45	/*
	46	* Synchronise with the boot thread.
	47	*/
	48	spin_lock(&boot_lock);
	49	spin_unlock(&boot_lock);
	50	}
	51
8bd26e3a	52	int versatile_boot_secondary(unsigned int cpu, struct task_struct *idle)
0462b447 RK	53	{
	54	unsigned long timeout;
	55
	56	/*
	57	* Set synchronisation state between this boot processor
	58	* and the secondary one
	59	*/
	60	spin_lock(&boot_lock);
	61
	62	/*
	63	* This is really belt and braces; we hold unintended secondary
	64	* CPUs in the holding pen until we're ready for them. However,
	65	* since we haven't sent them a soft interrupt, they shouldn't
	66	* be there.
	67	*/
4a139b64	68	write_pen_release(cpu_logical_map(cpu));
0462b447 RK	69
	70	/*
	71	* Send the secondary CPU a soft interrupt, thereby causing
	72	* the boot monitor to read the system wide flags register,
	73	* and branch to the address found there.
	74	*/
b1cffebf	75	arch_send_wakeup_ipi_mask(cpumask_of(cpu));
0462b447 RK	76
	77	timeout = jiffies + (1 * HZ);
	78	while (time_before(jiffies, timeout)) {
	79	smp_rmb();
	80	if (pen_release == -1)
	81	break;
	82
	83	udelay(10);
	84	}
	85
	86	/*
	87	* now the secondary core is starting up let it run its
	88	* calibrations, then wait for it to finish
	89	*/
	90	spin_unlock(&boot_lock);
	91
	92	return pen_release != -1 ? -ENOSYS : 0;
	93	}