[linux-2.6-block.git] / arch / arm / plat-samsung / setup-mipiphy.c

/*
 * Copyright (C) 2011 Samsung Electronics Co., Ltd.
 *
 * S5P - Helper functions for MIPI-CSIS and MIPI-DSIM D-PHY control
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/spinlock.h>
#include <mach/regs-clock.h>

static int __s5p_mipi_phy_control(int id, bool on, u32 reset)
{
	static DEFINE_SPINLOCK(lock);
	void __iomem *addr;
	unsigned long flags;
	u32 cfg;

	id = max(0, id);
	if (id > 1)
		return -EINVAL;

	addr = S5P_MIPI_DPHY_CONTROL(id);

	spin_lock_irqsave(&lock, flags);

	cfg = __raw_readl(addr);
	cfg = on ? (cfg | reset) : (cfg & ~reset);
	__raw_writel(cfg, addr);

	if (on) {
		cfg |= S5P_MIPI_DPHY_ENABLE;
	} else if (!(cfg & (S5P_MIPI_DPHY_SRESETN |
			    S5P_MIPI_DPHY_MRESETN) & ~reset)) {
		cfg &= ~S5P_MIPI_DPHY_ENABLE;
	}

	__raw_writel(cfg, addr);
	spin_unlock_irqrestore(&lock, flags);

	return 0;
}

int s5p_csis_phy_enable(int id, bool on)
{
	return __s5p_mipi_phy_control(id, on, S5P_MIPI_DPHY_SRESETN);
}

int s5p_dsim_phy_enable(struct platform_device *pdev, bool on)
{
	return __s5p_mipi_phy_control(pdev->id, on, S5P_MIPI_DPHY_MRESETN);
}
Commit	Line	Data
1d45ac49 SN	1	/*
	2	* Copyright (C) 2011 Samsung Electronics Co., Ltd.
	3	*
	4	* S5P - Helper functions for MIPI-CSIS and MIPI-DSIM D-PHY control
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*/
	10
	11	#include <linux/kernel.h>
	12	#include <linux/platform_device.h>
	13	#include <linux/io.h>
	14	#include <linux/spinlock.h>
	15	#include <mach/regs-clock.h>
	16
69a3d4f7	17	static int __s5p_mipi_phy_control(int id, bool on, u32 reset)
1d45ac49 SN	18	{
	19	static DEFINE_SPINLOCK(lock);
	20	void __iomem *addr;
	21	unsigned long flags;
1d45ac49 SN	22	u32 cfg;
1d45ac49 SN	23
69a3d4f7 SN	24	id = max(0, id);
69a3d4f7 SN	25	if (id > 1)
1d45ac49 SN	26	return -EINVAL;
1d45ac49 SN	27
69a3d4f7	28	addr = S5P_MIPI_DPHY_CONTROL(id);
1d45ac49 SN	29
	30	spin_lock_irqsave(&lock, flags);
	31
	32	cfg = __raw_readl(addr);
	33	cfg = on ? (cfg \| reset) : (cfg & ~reset);
	34	__raw_writel(cfg, addr);
	35
	36	if (on) {
	37	cfg \|= S5P_MIPI_DPHY_ENABLE;
	38	} else if (!(cfg & (S5P_MIPI_DPHY_SRESETN \|
	39	S5P_MIPI_DPHY_MRESETN) & ~reset)) {
	40	cfg &= ~S5P_MIPI_DPHY_ENABLE;
	41	}
	42
	43	__raw_writel(cfg, addr);
	44	spin_unlock_irqrestore(&lock, flags);
	45
	46	return 0;
	47	}
	48
69a3d4f7	49	int s5p_csis_phy_enable(int id, bool on)
1d45ac49	50	{
69a3d4f7	51	return __s5p_mipi_phy_control(id, on, S5P_MIPI_DPHY_SRESETN);
1d45ac49 SN	52	}
	53
	54	int s5p_dsim_phy_enable(struct platform_device *pdev, bool on)
	55	{
69a3d4f7	56	return __s5p_mipi_phy_control(pdev->id, on, S5P_MIPI_DPHY_MRESETN);
1d45ac49	57	}