projects / linux-2.6-block.git / blame
| Commit | Line | Data |
|---|---|---|
| 8eadcf74 | 1 | /* |
| 1663895c JL |
2 | * Copyright (c) 2011 Samsung Electronics Co., Ltd. |
| 3 | * http://www.samsung.com | |
| 4 | * | |
| e2e13621 AK |
5 | * Common S5P Sleep Code |
| 6 | * Based on S3C64XX sleep code by: | |
| 7 | * Ben Dooks, (c) 2008 Simtec Electronics | |
| 1663895c JL |
8 | * |
| 9 | * This program is free software; you can redistribute it and/or modify | |
| 10 | * it under the terms of the GNU General Public License as published by | |
| 11 | * the Free Software Foundation; either version 2 of the License, or | |
| 12 | * (at your option) any later version. | |
| 13 | * | |
| 14 | * This program is distributed in the hope that it will be useful, | |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 17 | * GNU General Public License for more details. | |
| 18 | * | |
| 19 | * You should have received a copy of the GNU General Public License | |
| 20 | * along with this program; if not, write to the Free Software | |
| 21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
| 22 | */ | |
| 23 | ||
| 24 | #include <linux/linkage.h> | |
| 7c6035b6 ADK |
25 | #include <asm/asm-offsets.h> |
| 26 | #include <asm/hardware/cache-l2x0.h> | |
| 1663895c | 27 | |
| 7c6035b6 ADK |
28 | /* |
| 29 | * The following code is located into the .data section. This is to | |
| 30 | * allow l2x0_regs_phys to be accessed with a relative load while we | |
| 31 | * can't rely on any MMU translation. We could have put l2x0_regs_phys | |
| 32 | * in the .text section as well, but some setups might insist on it to | |
| 33 | * be truly read-only. (Reference from: arch/arm/kernel/sleep.S) | |
| 34 | */ | |
| 35 | .data | |
| 36 | .align | |
| 1663895c | 37 | |
| 1663895c JL |
38 | /* |
| 39 | * sleep magic, to allow the bootloader to check for an valid | |
| 40 | * image to resume to. Must be the first word before the | |
| 41 | * s3c_cpu_resume entry. | |
| 42 | */ | |
| 43 | ||
| 44 | .word 0x2bedf00d | |
| 45 | ||
| 46 | /* | |
| 47 | * s3c_cpu_resume | |
| 48 | * | |
| 49 | * resume code entry for bootloader to call | |
| 1663895c JL |
50 | */ |
| 51 | ||
| 52 | ENTRY(s3c_cpu_resume) | |
| 7c6035b6 ADK |
53 | #ifdef CONFIG_CACHE_L2X0 |
| 54 | adr r0, l2x0_regs_phys | |
| 55 | ldr r0, [r0] | |
| 56 | ldr r1, [r0, #L2X0_R_PHY_BASE] | |
| 57 | ldr r2, [r1, #L2X0_CTRL] | |
| 58 | tst r2, #0x1 | |
| 59 | bne resume_l2on | |
| 60 | ldr r2, [r0, #L2X0_R_AUX_CTRL] | |
| 61 | str r2, [r1, #L2X0_AUX_CTRL] | |
| 62 | ldr r2, [r0, #L2X0_R_TAG_LATENCY] | |
| 63 | str r2, [r1, #L2X0_TAG_LATENCY_CTRL] | |
| 64 | ldr r2, [r0, #L2X0_R_DATA_LATENCY] | |
| 65 | str r2, [r1, #L2X0_DATA_LATENCY_CTRL] | |
| 66 | ldr r2, [r0, #L2X0_R_PREFETCH_CTRL] | |
| 67 | str r2, [r1, #L2X0_PREFETCH_CTRL] | |
| 68 | ldr r2, [r0, #L2X0_R_PWR_CTRL] | |
| 69 | str r2, [r1, #L2X0_POWER_CTRL] | |
| 70 | mov r2, #1 | |
| 71 | str r2, [r1, #L2X0_CTRL] | |
| 72 | resume_l2on: | |
| 73 | #endif | |
| 1663895c | 74 | b cpu_resume |
| 7c6035b6 ADK |
75 | ENDPROC(s3c_cpu_resume) |
| 76 | #ifdef CONFIG_CACHE_L2X0 | |
| 77 | .globl l2x0_regs_phys | |
| 78 | l2x0_regs_phys: | |
| 79 | .long 0 | |
| 80 | #endif |