[linux-2.6-block.git] / arch / arm / plat-samsung / s5p-irq-eint.c

/*
 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
 *		http://www.samsung.com
 *
 * S5P - IRQ EINT support
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
*/

#include <linux/kernel.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <linux/device.h>
#include <linux/gpio.h>
#include <linux/irqchip/arm-vic.h>

#include <plat/regs-irqtype.h>

#include <mach/map.h>
#include <plat/cpu.h>
#include <plat/pm.h>

#include <plat/gpio-cfg.h>
#include <mach/regs-gpio.h>

static inline void s5p_irq_eint_mask(struct irq_data *data)
{
	u32 mask;

	mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(data->irq)));
	mask |= eint_irq_to_bit(data->irq);
	__raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(data->irq)));
}

static void s5p_irq_eint_unmask(struct irq_data *data)
{
	u32 mask;

	mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(data->irq)));
	mask &= ~(eint_irq_to_bit(data->irq));
	__raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(data->irq)));
}

static inline void s5p_irq_eint_ack(struct irq_data *data)
{
	__raw_writel(eint_irq_to_bit(data->irq),
		     S5P_EINT_PEND(EINT_REG_NR(data->irq)));
}

static void s5p_irq_eint_maskack(struct irq_data *data)
{
	/* compiler should in-line these */
	s5p_irq_eint_mask(data);
	s5p_irq_eint_ack(data);
}

static int s5p_irq_eint_set_type(struct irq_data *data, unsigned int type)
{
	int offs = EINT_OFFSET(data->irq);
	int shift;
	u32 ctrl, mask;
	u32 newvalue = 0;

	switch (type) {
	case IRQ_TYPE_EDGE_RISING:
		newvalue = S5P_IRQ_TYPE_EDGE_RISING;
		break;

	case IRQ_TYPE_EDGE_FALLING:
		newvalue = S5P_IRQ_TYPE_EDGE_FALLING;
		break;

	case IRQ_TYPE_EDGE_BOTH:
		newvalue = S5P_IRQ_TYPE_EDGE_BOTH;
		break;

	case IRQ_TYPE_LEVEL_LOW:
		newvalue = S5P_IRQ_TYPE_LEVEL_LOW;
		break;

	case IRQ_TYPE_LEVEL_HIGH:
		newvalue = S5P_IRQ_TYPE_LEVEL_HIGH;
		break;

	default:
		printk(KERN_ERR "No such irq type %d", type);
		return -EINVAL;
	}

	shift = (offs & 0x7) * 4;
	mask = 0x7 << shift;

	ctrl = __raw_readl(S5P_EINT_CON(EINT_REG_NR(data->irq)));
	ctrl &= ~mask;
	ctrl |= newvalue << shift;
	__raw_writel(ctrl, S5P_EINT_CON(EINT_REG_NR(data->irq)));

	if ((0 <= offs) && (offs < 8))
		s3c_gpio_cfgpin(EINT_GPIO_0(offs & 0x7), EINT_MODE);

	else if ((8 <= offs) && (offs < 16))
		s3c_gpio_cfgpin(EINT_GPIO_1(offs & 0x7), EINT_MODE);

	else if ((16 <= offs) && (offs < 24))
		s3c_gpio_cfgpin(EINT_GPIO_2(offs & 0x7), EINT_MODE);

	else if ((24 <= offs) && (offs < 32))
		s3c_gpio_cfgpin(EINT_GPIO_3(offs & 0x7), EINT_MODE);

	else
		printk(KERN_ERR "No such irq number %d", offs);

	return 0;
}

static struct irq_chip s5p_irq_eint = {
	.name		= "s5p-eint",
	.irq_mask	= s5p_irq_eint_mask,
	.irq_unmask	= s5p_irq_eint_unmask,
	.irq_mask_ack	= s5p_irq_eint_maskack,
	.irq_ack	= s5p_irq_eint_ack,
	.irq_set_type	= s5p_irq_eint_set_type,
#ifdef CONFIG_PM
	.irq_set_wake	= s3c_irqext_wake,
#endif
};

/* s5p_irq_demux_eint
 *
 * This function demuxes the IRQ from the group0 external interrupts,
 * from EINTs 16 to 31. It is designed to be inlined into the specific
 * handler s5p_irq_demux_eintX_Y.
 *
 * Each EINT pend/mask registers handle eight of them.
 */
static inline void s5p_irq_demux_eint(unsigned int start)
{
	u32 status = __raw_readl(S5P_EINT_PEND(EINT_REG_NR(start)));
	u32 mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(start)));
	unsigned int irq;

	status &= ~mask;
	status &= 0xff;

	while (status) {
		irq = fls(status) - 1;
		generic_handle_irq(irq + start);
		status &= ~(1 << irq);
	}
}

static void s5p_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
{
	s5p_irq_demux_eint(IRQ_EINT(16));
	s5p_irq_demux_eint(IRQ_EINT(24));
}

static inline void s5p_irq_vic_eint_mask(struct irq_data *data)
{
	void __iomem *base = irq_data_get_irq_chip_data(data);

	s5p_irq_eint_mask(data);
	writel(1 << EINT_OFFSET(data->irq), base + VIC_INT_ENABLE_CLEAR);
}

static void s5p_irq_vic_eint_unmask(struct irq_data *data)
{
	void __iomem *base = irq_data_get_irq_chip_data(data);

	s5p_irq_eint_unmask(data);
	writel(1 << EINT_OFFSET(data->irq), base + VIC_INT_ENABLE);
}

static inline void s5p_irq_vic_eint_ack(struct irq_data *data)
{
	__raw_writel(eint_irq_to_bit(data->irq),
		     S5P_EINT_PEND(EINT_REG_NR(data->irq)));
}

static void s5p_irq_vic_eint_maskack(struct irq_data *data)
{
	s5p_irq_vic_eint_mask(data);
	s5p_irq_vic_eint_ack(data);
}

static struct irq_chip s5p_irq_vic_eint = {
	.name		= "s5p_vic_eint",
	.irq_mask	= s5p_irq_vic_eint_mask,
	.irq_unmask	= s5p_irq_vic_eint_unmask,
	.irq_mask_ack	= s5p_irq_vic_eint_maskack,
	.irq_ack	= s5p_irq_vic_eint_ack,
	.irq_set_type	= s5p_irq_eint_set_type,
#ifdef CONFIG_PM
	.irq_set_wake	= s3c_irqext_wake,
#endif
};

static int __init s5p_init_irq_eint(void)
{
	int irq;

	for (irq = IRQ_EINT(0); irq <= IRQ_EINT(15); irq++)
		irq_set_chip(irq, &s5p_irq_vic_eint);

	for (irq = IRQ_EINT(16); irq <= IRQ_EINT(31); irq++) {
		irq_set_chip_and_handler(irq, &s5p_irq_eint, handle_level_irq);
		set_irq_flags(irq, IRQF_VALID);
	}

	irq_set_chained_handler(IRQ_EINT16_31, s5p_irq_demux_eint16_31);
	return 0;
}

arch_initcall(s5p_init_irq_eint);
Commit	Line	Data
68ae8998	1	/*
0df04f82 JL	2	* Copyright (c) 2010 Samsung Electronics Co., Ltd.
	3	* http://www.samsung.com
	4	*
	5	* S5P - IRQ EINT support
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*/
	11
	12	#include <linux/kernel.h>
	13	#include <linux/interrupt.h>
	14	#include <linux/irq.h>
	15	#include <linux/io.h>
edbaa603	16	#include <linux/device.h>
0df04f82	17	#include <linux/gpio.h>
9e47b8bf	18	#include <linux/irqchip/arm-vic.h>
0df04f82 JL	19
	20	#include <plat/regs-irqtype.h>
	21
	22	#include <mach/map.h>
	23	#include <plat/cpu.h>
	24	#include <plat/pm.h>
	25
	26	#include <plat/gpio-cfg.h>
	27	#include <mach/regs-gpio.h>
	28
bb0b2374	29	static inline void s5p_irq_eint_mask(struct irq_data *data)
0df04f82 JL	30	{
	31	u32 mask;
	32
bb0b2374 LB	33	mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(data->irq)));
	34	mask \|= eint_irq_to_bit(data->irq);
	35	__raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(data->irq)));
0df04f82 JL	36	}
0df04f82 JL	37
bb0b2374	38	static void s5p_irq_eint_unmask(struct irq_data *data)
0df04f82 JL	39	{
	40	u32 mask;
	41
bb0b2374 LB	42	mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(data->irq)));
	43	mask &= ~(eint_irq_to_bit(data->irq));
	44	__raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(data->irq)));
0df04f82 JL	45	}
0df04f82 JL	46
bb0b2374	47	static inline void s5p_irq_eint_ack(struct irq_data *data)
0df04f82	48	{
bb0b2374 LB	49	__raw_writel(eint_irq_to_bit(data->irq),
bb0b2374 LB	50	S5P_EINT_PEND(EINT_REG_NR(data->irq)));
0df04f82 JL	51	}
0df04f82 JL	52
bb0b2374	53	static void s5p_irq_eint_maskack(struct irq_data *data)
0df04f82 JL	54	{
0df04f82 JL	55	/* compiler should in-line these */
bb0b2374 LB	56	s5p_irq_eint_mask(data);
bb0b2374 LB	57	s5p_irq_eint_ack(data);
0df04f82 JL	58	}
0df04f82 JL	59
bb0b2374	60	static int s5p_irq_eint_set_type(struct irq_data *data, unsigned int type)
0df04f82	61	{
bb0b2374	62	int offs = EINT_OFFSET(data->irq);
0df04f82 JL	63	int shift;
	64	u32 ctrl, mask;
	65	u32 newvalue = 0;
	66
	67	switch (type) {
	68	case IRQ_TYPE_EDGE_RISING:
9adf5d22	69	newvalue = S5P_IRQ_TYPE_EDGE_RISING;
0df04f82 JL	70	break;
	71
	72	case IRQ_TYPE_EDGE_FALLING:
9adf5d22	73	newvalue = S5P_IRQ_TYPE_EDGE_FALLING;
0df04f82 JL	74	break;
	75
	76	case IRQ_TYPE_EDGE_BOTH:
9adf5d22	77	newvalue = S5P_IRQ_TYPE_EDGE_BOTH;
0df04f82 JL	78	break;
	79
	80	case IRQ_TYPE_LEVEL_LOW:
9adf5d22	81	newvalue = S5P_IRQ_TYPE_LEVEL_LOW;
0df04f82 JL	82	break;
	83
	84	case IRQ_TYPE_LEVEL_HIGH:
9adf5d22	85	newvalue = S5P_IRQ_TYPE_LEVEL_HIGH;
0df04f82 JL	86	break;
	87
	88	default:
	89	printk(KERN_ERR "No such irq type %d", type);
	90	return -EINVAL;
	91	}
	92
	93	shift = (offs & 0x7) * 4;
	94	mask = 0x7 << shift;
	95
bb0b2374	96	ctrl = __raw_readl(S5P_EINT_CON(EINT_REG_NR(data->irq)));
0df04f82 JL	97	ctrl &= ~mask;
0df04f82 JL	98	ctrl \|= newvalue << shift;
bb0b2374	99	__raw_writel(ctrl, S5P_EINT_CON(EINT_REG_NR(data->irq)));
0df04f82 JL	100
	101	if ((0 <= offs) && (offs < 8))
	102	s3c_gpio_cfgpin(EINT_GPIO_0(offs & 0x7), EINT_MODE);
	103
	104	else if ((8 <= offs) && (offs < 16))
	105	s3c_gpio_cfgpin(EINT_GPIO_1(offs & 0x7), EINT_MODE);
	106
	107	else if ((16 <= offs) && (offs < 24))
	108	s3c_gpio_cfgpin(EINT_GPIO_2(offs & 0x7), EINT_MODE);
	109
	110	else if ((24 <= offs) && (offs < 32))
	111	s3c_gpio_cfgpin(EINT_GPIO_3(offs & 0x7), EINT_MODE);
	112
	113	else
	114	printk(KERN_ERR "No such irq number %d", offs);
	115
	116	return 0;
	117	}
	118
	119	static struct irq_chip s5p_irq_eint = {
	120	.name = "s5p-eint",
bb0b2374 LB	121	.irq_mask = s5p_irq_eint_mask,
	122	.irq_unmask = s5p_irq_eint_unmask,
	123	.irq_mask_ack = s5p_irq_eint_maskack,
	124	.irq_ack = s5p_irq_eint_ack,
	125	.irq_set_type = s5p_irq_eint_set_type,
0df04f82	126	#ifdef CONFIG_PM
f5aeffb7	127	.irq_set_wake = s3c_irqext_wake,
0df04f82 JL	128	#endif
	129	};
	130
	131	/* s5p_irq_demux_eint
	132	*
	133	* This function demuxes the IRQ from the group0 external interrupts,
	134	* from EINTs 16 to 31. It is designed to be inlined into the specific
	135	* handler s5p_irq_demux_eintX_Y.
	136	*
	137	* Each EINT pend/mask registers handle eight of them.
	138	*/
	139	static inline void s5p_irq_demux_eint(unsigned int start)
	140	{
5fae4058	141	u32 status = __raw_readl(S5P_EINT_PEND(EINT_REG_NR(start)));
0df04f82 JL	142	u32 mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(start)));
	143	unsigned int irq;
	144
0df04f82 JL	145	status &= ~mask;
	146	status &= 0xff;
	147
	148	while (status) {
5fae4058 PB	149	irq = fls(status) - 1;
5fae4058 PB	150	generic_handle_irq(irq + start);
0df04f82 JL	151	status &= ~(1 << irq);
	152	}
	153	}
	154
	155	static void s5p_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
	156	{
	157	s5p_irq_demux_eint(IRQ_EINT(16));
	158	s5p_irq_demux_eint(IRQ_EINT(24));
	159	}
	160
bb0b2374	161	static inline void s5p_irq_vic_eint_mask(struct irq_data *data)
0df04f82	162	{
bb0b2374	163	void __iomem *base = irq_data_get_irq_chip_data(data);
5fae4058	164
bb0b2374 LB	165	s5p_irq_eint_mask(data);
bb0b2374 LB	166	writel(1 << EINT_OFFSET(data->irq), base + VIC_INT_ENABLE_CLEAR);
0df04f82 JL	167	}
0df04f82 JL	168
bb0b2374	169	static void s5p_irq_vic_eint_unmask(struct irq_data *data)
0df04f82	170	{
bb0b2374	171	void __iomem *base = irq_data_get_irq_chip_data(data);
5fae4058	172
bb0b2374 LB	173	s5p_irq_eint_unmask(data);
bb0b2374 LB	174	writel(1 << EINT_OFFSET(data->irq), base + VIC_INT_ENABLE);
0df04f82 JL	175	}
0df04f82 JL	176
bb0b2374	177	static inline void s5p_irq_vic_eint_ack(struct irq_data *data)
0df04f82	178	{
bb0b2374 LB	179	__raw_writel(eint_irq_to_bit(data->irq),
bb0b2374 LB	180	S5P_EINT_PEND(EINT_REG_NR(data->irq)));
0df04f82 JL	181	}
0df04f82 JL	182
bb0b2374	183	static void s5p_irq_vic_eint_maskack(struct irq_data *data)
0df04f82	184	{
bb0b2374 LB	185	s5p_irq_vic_eint_mask(data);
bb0b2374 LB	186	s5p_irq_vic_eint_ack(data);
0df04f82 JL	187	}
	188
	189	static struct irq_chip s5p_irq_vic_eint = {
	190	.name = "s5p_vic_eint",
bb0b2374 LB	191	.irq_mask = s5p_irq_vic_eint_mask,
	192	.irq_unmask = s5p_irq_vic_eint_unmask,
	193	.irq_mask_ack = s5p_irq_vic_eint_maskack,
	194	.irq_ack = s5p_irq_vic_eint_ack,
	195	.irq_set_type = s5p_irq_eint_set_type,
0df04f82	196	#ifdef CONFIG_PM
f5aeffb7	197	.irq_set_wake = s3c_irqext_wake,
0df04f82 JL	198	#endif
	199	};
	200
6d259a25	201	static int __init s5p_init_irq_eint(void)
0df04f82 JL	202	{
	203	int irq;
	204
	205	for (irq = IRQ_EINT(0); irq <= IRQ_EINT(15); irq++)
6845664a	206	irq_set_chip(irq, &s5p_irq_vic_eint);
0df04f82 JL	207
0df04f82 JL	208	for (irq = IRQ_EINT(16); irq <= IRQ_EINT(31); irq++) {
f38c02f3	209	irq_set_chip_and_handler(irq, &s5p_irq_eint, handle_level_irq);
0df04f82 JL	210	set_irq_flags(irq, IRQF_VALID);
	211	}
	212
6845664a	213	irq_set_chained_handler(IRQ_EINT16_31, s5p_irq_demux_eint16_31);
0df04f82 JL	214	return 0;
	215	}
	216
	217	arch_initcall(s5p_init_irq_eint);