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7db6c82a BD |
1 | /* linux/arch/arm/plat-s3c/include/plat/gpio-core.h |
2 | * | |
3 | * Copyright 2008 Simtec Electronics | |
4 | * http://armlinux.simtec.co.uk/ | |
5 | * Ben Dooks <ben@simtec.co.uk> | |
6 | * | |
7 | * S3C Platform - GPIO core | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | */ | |
13 | ||
1f323cfd KK |
14 | #define GPIOCON_OFF (0x00) |
15 | #define GPIODAT_OFF (0x04) | |
16 | ||
17 | #define con_4bit_shift(__off) ((__off) * 4) | |
18 | ||
7db6c82a BD |
19 | /* Define the core gpiolib support functions that the s3c platforms may |
20 | * need to extend or change depending on the hardware and the s3c chip | |
21 | * selected at build or found at run time. | |
22 | * | |
23 | * These definitions are not intended for driver inclusion, there is | |
24 | * nothing here that should not live outside the platform and core | |
25 | * specific code. | |
26 | */ | |
27 | ||
d87964c4 BD |
28 | struct s3c_gpio_chip; |
29 | ||
30 | /** | |
31 | * struct s3c_gpio_pm - power management (suspend/resume) information | |
32 | * @save: Routine to save the state of the GPIO block | |
33 | * @resume: Routine to resume the GPIO block. | |
34 | */ | |
35 | struct s3c_gpio_pm { | |
36 | void (*save)(struct s3c_gpio_chip *chip); | |
37 | void (*resume)(struct s3c_gpio_chip *chip); | |
38 | }; | |
39 | ||
21b23664 BD |
40 | struct s3c_gpio_cfg; |
41 | ||
7db6c82a BD |
42 | /** |
43 | * struct s3c_gpio_chip - wrapper for specific implementation of gpio | |
44 | * @chip: The chip structure to be exported via gpiolib. | |
45 | * @base: The base pointer to the gpio configuration registers. | |
170a4617 MS |
46 | * @group: The group register number for gpio interrupt support. |
47 | * @irq_base: The base irq number. | |
21b23664 | 48 | * @config: special function and pull-resistor control information. |
fcef85c0 | 49 | * @lock: Lock for exclusive access to this gpio bank. |
d87964c4 | 50 | * @pm_save: Save information for suspend/resume support. |
7db6c82a BD |
51 | * |
52 | * This wrapper provides the necessary information for the Samsung | |
53 | * specific gpios being registered with gpiolib. | |
fcef85c0 BD |
54 | * |
55 | * The lock protects each gpio bank from multiple access of the shared | |
56 | * configuration registers, or from reading of data whilst another thread | |
57 | * is writing to the register set. | |
58 | * | |
59 | * Each chip has its own lock to avoid any contention between different | |
60 | * CPU cores trying to get one lock for different GPIO banks, where each | |
61 | * bank of GPIO has its own register space and configuration registers. | |
7db6c82a BD |
62 | */ |
63 | struct s3c_gpio_chip { | |
64 | struct gpio_chip chip; | |
21b23664 | 65 | struct s3c_gpio_cfg *config; |
d87964c4 | 66 | struct s3c_gpio_pm *pm; |
7db6c82a | 67 | void __iomem *base; |
170a4617 MS |
68 | int irq_base; |
69 | int group; | |
fcef85c0 | 70 | spinlock_t lock; |
d87964c4 BD |
71 | #ifdef CONFIG_PM |
72 | u32 pm_save[4]; | |
73 | #endif | |
7db6c82a BD |
74 | }; |
75 | ||
76 | static inline struct s3c_gpio_chip *to_s3c_gpio(struct gpio_chip *gpc) | |
77 | { | |
78 | return container_of(gpc, struct s3c_gpio_chip, chip); | |
79 | } | |
80 | ||
81 | /** s3c_gpiolib_add() - add the s3c specific version of a gpio_chip. | |
82 | * @chip: The chip to register | |
83 | * | |
84 | * This is a wrapper to gpiochip_add() that takes our specific gpio chip | |
85 | * information and makes the necessary alterations for the platform and | |
86 | * notes the information for use with the configuration systems and any | |
87 | * other parts of the system. | |
88 | */ | |
89 | extern void s3c_gpiolib_add(struct s3c_gpio_chip *chip); | |
8a53bdb9 | 90 | |
8a53bdb9 BD |
91 | /* CONFIG_S3C_GPIO_TRACK enables the tracking of the s3c specific gpios |
92 | * for use with the configuration calls, and other parts of the s3c gpiolib | |
93 | * support code. | |
94 | * | |
95 | * Not all s3c support code will need this, as some configurations of cpu | |
96 | * may only support one or two different configuration options and have an | |
97 | * easy gpio to s3c_gpio_chip mapping function. If this is the case, then | |
98 | * the machine support file should provide its own s3c_gpiolib_getchip() | |
99 | * and any other necessary functions. | |
100 | */ | |
101 | ||
1f323cfd KK |
102 | /** |
103 | * samsung_gpiolib_add_4bit_chips - 4bit single register GPIO config. | |
104 | * @chip: The gpio chip that is being configured. | |
105 | * @nr_chips: The no of chips (gpio ports) for the GPIO being configured. | |
106 | * | |
107 | * This helper deal with the GPIO cases where the control register has 4 bits | |
108 | * of control per GPIO, generally in the form of: | |
109 | * 0000 = Input | |
110 | * 0001 = Output | |
111 | * others = Special functions (dependant on bank) | |
112 | * | |
113 | * Note, since the code to deal with the case where there are two control | |
a8cd4561 | 114 | * registers instead of one, we do not have a separate set of function |
1f323cfd KK |
115 | * (samsung_gpiolib_add_4bit2_chips)for each case. |
116 | */ | |
117 | extern void samsung_gpiolib_add_4bit_chips(struct s3c_gpio_chip *chip, | |
118 | int nr_chips); | |
119 | extern void samsung_gpiolib_add_4bit2_chips(struct s3c_gpio_chip *chip, | |
120 | int nr_chips); | |
121 | ||
122 | extern void samsung_gpiolib_add_4bit(struct s3c_gpio_chip *chip); | |
123 | extern void samsung_gpiolib_add_4bit2(struct s3c_gpio_chip *chip); | |
124 | ||
8ce14a22 JS |
125 | |
126 | /** | |
127 | * samsung_gpiolib_to_irq - convert gpio pin to irq number | |
128 | * @chip: The gpio chip that the pin belongs to. | |
129 | * @offset: The offset of the pin in the chip. | |
130 | * | |
131 | * This helper returns the irq number calculated from the chip->irq_base and | |
132 | * the provided offset. | |
133 | */ | |
134 | extern int samsung_gpiolib_to_irq(struct gpio_chip *chip, unsigned int offset); | |
135 | ||
9bbb851c BD |
136 | /* exported for core SoC support to change */ |
137 | extern struct s3c_gpio_cfg s3c24xx_gpiocfg_default; | |
138 | ||
8a53bdb9 BD |
139 | #ifdef CONFIG_S3C_GPIO_TRACK |
140 | extern struct s3c_gpio_chip *s3c_gpios[S3C_GPIO_END]; | |
141 | ||
142 | static inline struct s3c_gpio_chip *s3c_gpiolib_getchip(unsigned int chip) | |
143 | { | |
21b23664 | 144 | return (chip < S3C_GPIO_END) ? s3c_gpios[chip] : NULL; |
8a53bdb9 BD |
145 | } |
146 | #else | |
21b23664 BD |
147 | /* machine specific code should provide s3c_gpiolib_getchip */ |
148 | ||
e856bb1f BD |
149 | #include <mach/gpio-track.h> |
150 | ||
8a53bdb9 BD |
151 | static inline void s3c_gpiolib_track(struct s3c_gpio_chip *chip) { } |
152 | #endif | |
d87964c4 BD |
153 | |
154 | #ifdef CONFIG_PM | |
155 | extern struct s3c_gpio_pm s3c_gpio_pm_1bit; | |
156 | extern struct s3c_gpio_pm s3c_gpio_pm_2bit; | |
157 | extern struct s3c_gpio_pm s3c_gpio_pm_4bit; | |
158 | #define __gpio_pm(x) x | |
159 | #else | |
160 | #define s3c_gpio_pm_1bit NULL | |
161 | #define s3c_gpio_pm_2bit NULL | |
162 | #define s3c_gpio_pm_4bit NULL | |
163 | #define __gpio_pm(x) NULL | |
164 | ||
165 | #endif /* CONFIG_PM */ | |
fcef85c0 BD |
166 | |
167 | /* locking wrappers to deal with multiple access to the same gpio bank */ | |
168 | #define s3c_gpio_lock(_oc, _fl) spin_lock_irqsave(&(_oc)->lock, _fl) | |
169 | #define s3c_gpio_unlock(_oc, _fl) spin_unlock_irqrestore(&(_oc)->lock, _fl) |