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1a0e8a52 KK |
1 | /* linux/arch/arm/plat-s5p/clock.c |
2 | * | |
3 | * Copyright 2009 Samsung Electronics Co., Ltd. | |
4 | * http://www.samsung.com/ | |
5 | * | |
6 | * S5P - Common clock support | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
12 | ||
13 | #include <linux/init.h> | |
14 | #include <linux/module.h> | |
15 | #include <linux/kernel.h> | |
16 | #include <linux/list.h> | |
17 | #include <linux/errno.h> | |
18 | #include <linux/err.h> | |
19 | #include <linux/clk.h> | |
20 | #include <linux/sysdev.h> | |
21 | #include <linux/io.h> | |
22 | #include <asm/div64.h> | |
23 | ||
24 | #include <plat/clock.h> | |
25 | #include <plat/clock-clksrc.h> | |
26 | #include <plat/s5p-clock.h> | |
27 | ||
28 | /* fin_apll, fin_mpll and fin_epll are all the same clock, which we call | |
29 | * clk_ext_xtal_mux. | |
30 | */ | |
31 | struct clk clk_ext_xtal_mux = { | |
32 | .name = "ext_xtal", | |
33 | .id = -1, | |
34 | }; | |
35 | ||
f001d5b2 TA |
36 | struct clk clk_xusbxti = { |
37 | .name = "xusbxti", | |
38 | .id = -1, | |
39 | }; | |
40 | ||
a443a637 | 41 | struct clk s5p_clk_27m = { |
0c1945d3 KK |
42 | .name = "clk_27m", |
43 | .id = -1, | |
44 | .rate = 27000000, | |
45 | }; | |
46 | ||
1a0e8a52 KK |
47 | /* 48MHz USB Phy clock output */ |
48 | struct clk clk_48m = { | |
49 | .name = "clk_48m", | |
50 | .id = -1, | |
51 | .rate = 48000000, | |
52 | }; | |
53 | ||
54 | /* APLL clock output | |
55 | * No need .ctrlbit, this is always on | |
56 | */ | |
57 | struct clk clk_fout_apll = { | |
58 | .name = "fout_apll", | |
59 | .id = -1, | |
60 | }; | |
61 | ||
62 | /* MPLL clock output | |
63 | * No need .ctrlbit, this is always on | |
64 | */ | |
65 | struct clk clk_fout_mpll = { | |
66 | .name = "fout_mpll", | |
67 | .id = -1, | |
68 | }; | |
69 | ||
70 | /* EPLL clock output */ | |
71 | struct clk clk_fout_epll = { | |
72 | .name = "fout_epll", | |
73 | .id = -1, | |
74 | .ctrlbit = (1 << 31), | |
75 | }; | |
76 | ||
f445dbd5 TA |
77 | /* VPLL clock output */ |
78 | struct clk clk_fout_vpll = { | |
79 | .name = "fout_vpll", | |
80 | .id = -1, | |
81 | .ctrlbit = (1 << 31), | |
82 | }; | |
83 | ||
1a0e8a52 KK |
84 | /* ARM clock */ |
85 | struct clk clk_arm = { | |
86 | .name = "armclk", | |
87 | .id = -1, | |
88 | .rate = 0, | |
89 | .ctrlbit = 0, | |
90 | }; | |
91 | ||
92 | /* Possible clock sources for APLL Mux */ | |
93 | static struct clk *clk_src_apll_list[] = { | |
94 | [0] = &clk_fin_apll, | |
95 | [1] = &clk_fout_apll, | |
96 | }; | |
97 | ||
98 | struct clksrc_sources clk_src_apll = { | |
99 | .sources = clk_src_apll_list, | |
100 | .nr_sources = ARRAY_SIZE(clk_src_apll_list), | |
101 | }; | |
102 | ||
103 | /* Possible clock sources for MPLL Mux */ | |
104 | static struct clk *clk_src_mpll_list[] = { | |
105 | [0] = &clk_fin_mpll, | |
106 | [1] = &clk_fout_mpll, | |
107 | }; | |
108 | ||
109 | struct clksrc_sources clk_src_mpll = { | |
110 | .sources = clk_src_mpll_list, | |
111 | .nr_sources = ARRAY_SIZE(clk_src_mpll_list), | |
112 | }; | |
113 | ||
114 | /* Possible clock sources for EPLL Mux */ | |
115 | static struct clk *clk_src_epll_list[] = { | |
116 | [0] = &clk_fin_epll, | |
117 | [1] = &clk_fout_epll, | |
118 | }; | |
119 | ||
120 | struct clksrc_sources clk_src_epll = { | |
121 | .sources = clk_src_epll_list, | |
122 | .nr_sources = ARRAY_SIZE(clk_src_epll_list), | |
123 | }; | |
124 | ||
0c1945d3 KK |
125 | struct clk clk_vpll = { |
126 | .name = "vpll", | |
127 | .id = -1, | |
128 | }; | |
129 | ||
1a0e8a52 KK |
130 | int s5p_gatectrl(void __iomem *reg, struct clk *clk, int enable) |
131 | { | |
132 | unsigned int ctrlbit = clk->ctrlbit; | |
133 | u32 con; | |
134 | ||
135 | con = __raw_readl(reg); | |
136 | con = enable ? (con | ctrlbit) : (con & ~ctrlbit); | |
137 | __raw_writel(con, reg); | |
138 | return 0; | |
139 | } | |
140 | ||
141 | static struct clk *s5p_clks[] __initdata = { | |
142 | &clk_ext_xtal_mux, | |
143 | &clk_48m, | |
0c1945d3 | 144 | &s5p_clk_27m, |
1a0e8a52 KK |
145 | &clk_fout_apll, |
146 | &clk_fout_mpll, | |
147 | &clk_fout_epll, | |
f445dbd5 | 148 | &clk_fout_vpll, |
1a0e8a52 | 149 | &clk_arm, |
0c1945d3 | 150 | &clk_vpll, |
1a0e8a52 KK |
151 | }; |
152 | ||
153 | void __init s5p_register_clocks(unsigned long xtal_freq) | |
154 | { | |
155 | int ret; | |
156 | ||
157 | clk_ext_xtal_mux.rate = xtal_freq; | |
158 | ||
159 | ret = s3c24xx_register_clocks(s5p_clks, ARRAY_SIZE(s5p_clks)); | |
160 | if (ret > 0) | |
161 | printk(KERN_ERR "Failed to register s5p clocks\n"); | |
162 | } |