[linux-2.6-block.git] / arch / arm / plat-s3c24xx / pm.c

/* linux/arch/arm/plat-s3c24xx/pm.c
 *
 * Copyright (c) 2004,2006 Simtec Electronics
 *	Ben Dooks <ben@simtec.co.uk>
 *
 * S3C24XX Power Manager (Suspend-To-RAM) support
 *
 * See Documentation/arm/Samsung-S3C24XX/Suspend.txt for more information
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 *
 * Parts based on arch/arm/mach-pxa/pm.c
 *
 * Thanks to Dimitry Andric for debugging
*/

#include <linux/init.h>
#include <linux/suspend.h>
#include <linux/errno.h>
#include <linux/time.h>
#include <linux/interrupt.h>
#include <linux/serial_core.h>
#include <linux/io.h>

#include <asm/cacheflush.h>
#include <mach/hardware.h>

#include <plat/regs-serial.h>
#include <mach/regs-clock.h>
#include <mach/regs-gpio.h>
#include <mach/regs-mem.h>
#include <mach/regs-irq.h>

#include <asm/mach/time.h>

#include <plat/pm.h>


#define PFX "s3c24xx-pm: "

static struct sleep_save core_save[] = {
	SAVE_ITEM(S3C2410_LOCKTIME),
	SAVE_ITEM(S3C2410_CLKCON),

	/* we restore the timings here, with the proviso that the board
	 * brings the system up in an slower, or equal frequency setting
	 * to the original system.
	 *
	 * if we cannot guarantee this, then things are going to go very
	 * wrong here, as we modify the refresh and both pll settings.
	 */

	SAVE_ITEM(S3C2410_BWSCON),
	SAVE_ITEM(S3C2410_BANKCON0),
	SAVE_ITEM(S3C2410_BANKCON1),
	SAVE_ITEM(S3C2410_BANKCON2),
	SAVE_ITEM(S3C2410_BANKCON3),
	SAVE_ITEM(S3C2410_BANKCON4),
	SAVE_ITEM(S3C2410_BANKCON5),

#ifndef CONFIG_CPU_FREQ
	SAVE_ITEM(S3C2410_CLKDIVN),
	SAVE_ITEM(S3C2410_MPLLCON),
	SAVE_ITEM(S3C2410_REFRESH),
#endif
	SAVE_ITEM(S3C2410_UPLLCON),
	SAVE_ITEM(S3C2410_CLKSLOW),
};

static struct gpio_sleep {
	void __iomem	*base;
	unsigned int	 gpcon;
	unsigned int	 gpdat;
	unsigned int	 gpup;
} gpio_save[] = {
	[0] = {
		.base	= S3C2410_GPACON,
	},
	[1] = {
		.base	= S3C2410_GPBCON,
	},
	[2] = {
		.base	= S3C2410_GPCCON,
	},
	[3] = {
		.base	= S3C2410_GPDCON,
	},
	[4] = {
		.base	= S3C2410_GPECON,
	},
	[5] = {
		.base	= S3C2410_GPFCON,
	},
	[6] = {
		.base	= S3C2410_GPGCON,
	},
	[7] = {
		.base	= S3C2410_GPHCON,
	},
};

static struct sleep_save misc_save[] = {
	SAVE_ITEM(S3C2410_DCLKCON),
};

#ifdef CONFIG_S3C2410_PM_DEBUG

#define SAVE_UART(va) \
	SAVE_ITEM((va) + S3C2410_ULCON), \
	SAVE_ITEM((va) + S3C2410_UCON), \
	SAVE_ITEM((va) + S3C2410_UFCON), \
	SAVE_ITEM((va) + S3C2410_UMCON), \
	SAVE_ITEM((va) + S3C2410_UBRDIV)

static struct sleep_save uart_save[] = {
	SAVE_UART(S3C24XX_VA_UART0),
	SAVE_UART(S3C24XX_VA_UART1),
#ifndef CONFIG_CPU_S3C2400
	SAVE_UART(S3C24XX_VA_UART2),
#endif
};

/* debug
 *
 * we send the debug to printascii() to allow it to be seen if the
 * system never wakes up from the sleep
*/

static void s3c2410_pm_debug_init(void)
{
	unsigned long tmp = __raw_readl(S3C2410_CLKCON);

	/* re-start uart clocks */
	tmp |= S3C2410_CLKCON_UART0;
	tmp |= S3C2410_CLKCON_UART1;
	tmp |= S3C2410_CLKCON_UART2;

	__raw_writel(tmp, S3C2410_CLKCON);
	udelay(10);
}

#else
#define s3c2410_pm_debug_init() do { } while(0)

static struct sleep_save uart_save[] = {};
#endif

/* s3c2410_pm_show_resume_irqs
 *
 * print any IRQs asserted at resume time (ie, we woke from)
*/

static void s3c2410_pm_show_resume_irqs(int start, unsigned long which,
					unsigned long mask)
{
	int i;

	which &= ~mask;

	for (i = 0; i <= 31; i++) {
		if ((which) & (1L<<i)) {
			S3C_PMDBG("IRQ %d asserted at resume\n", start+i);
		}
	}
}

/* s3c_pm_check_resume_pin
 *
 * check to see if the pin is configured correctly for sleep mode, and
 * make any necessary adjustments if it is not
*/

static void s3c_pm_check_resume_pin(unsigned int pin, unsigned int irqoffs)
{
	unsigned long irqstate;
	unsigned long pinstate;
	int irq = s3c2410_gpio_getirq(pin);

	if (irqoffs < 4)
		irqstate = s3c_irqwake_intmask & (1L<<irqoffs);
	else
		irqstate = s3c_irqwake_eintmask & (1L<<irqoffs);

	pinstate = s3c2410_gpio_getcfg(pin);

	if (!irqstate) {
		if (pinstate == S3C2410_GPIO_IRQ)
			S3C_PMDBG("Leaving IRQ %d (pin %d) enabled\n", irq, pin);
	} else {
		if (pinstate == S3C2410_GPIO_IRQ) {
			S3C_PMDBG("Disabling IRQ %d (pin %d)\n", irq, pin);
			s3c2410_gpio_cfgpin(pin, S3C2410_GPIO_INPUT);
		}
	}
}

/* s3c2410_pm_configure_extint
 *
 * configure all external interrupt pins
*/

static void s3c2410_pm_configure_extint(void)
{
	int pin;

	/* for each of the external interrupts (EINT0..EINT15) we
	 * need to check wether it is an external interrupt source,
	 * and then configure it as an input if it is not
	*/

	for (pin = S3C2410_GPF0; pin <= S3C2410_GPF7; pin++) {
		s3c_pm_check_resume_pin(pin, pin - S3C2410_GPF0);
	}

	for (pin = S3C2410_GPG0; pin <= S3C2410_GPG7; pin++) {
		s3c_pm_check_resume_pin(pin, (pin - S3C2410_GPG0)+8);
	}
}

/* offsets for CON/DAT/UP registers */

#define OFFS_CON	(S3C2410_GPACON - S3C2410_GPACON)
#define OFFS_DAT	(S3C2410_GPADAT - S3C2410_GPACON)
#define OFFS_UP		(S3C2410_GPBUP  - S3C2410_GPBCON)

/* s3c2410_pm_save_gpios()
 *
 * Save the state of the GPIOs
 */

static void s3c2410_pm_save_gpios(void)
{
	struct gpio_sleep *gps = gpio_save;
	unsigned int gpio;

	for (gpio = 0; gpio < ARRAY_SIZE(gpio_save); gpio++, gps++) {
		void __iomem *base = gps->base;

		gps->gpcon = __raw_readl(base + OFFS_CON);
		gps->gpdat = __raw_readl(base + OFFS_DAT);

		if (gpio > 0)
			gps->gpup = __raw_readl(base + OFFS_UP);

	}
}

/* Test whether the given masked+shifted bits of an GPIO configuration
 * are one of the SFN (special function) modes. */

static inline int is_sfn(unsigned long con)
{
	return (con == 2 || con == 3);
}

/* Test if the given masked+shifted GPIO configuration is an input */

static inline int is_in(unsigned long con)
{
	return con == 0;
}

/* Test if the given masked+shifted GPIO configuration is an output */

static inline int is_out(unsigned long con)
{
	return con == 1;
}

/* s3c2410_pm_restore_gpio()
 *
 * Restore one of the GPIO banks that was saved during suspend. This is
 * not as simple as once thought, due to the possibility of glitches
 * from the order that the CON and DAT registers are set in.
 *
 * The three states the pin can be are {IN,OUT,SFN} which gives us 9
 * combinations of changes to check. Three of these, if the pin stays
 * in the same configuration can be discounted. This leaves us with
 * the following:
 *
 * { IN => OUT }  Change DAT first
 * { IN => SFN }  Change CON first
 * { OUT => SFN } Change CON first, so new data will not glitch
 * { OUT => IN }  Change CON first, so new data will not glitch
 * { SFN => IN }  Change CON first
 * { SFN => OUT } Change DAT first, so new data will not glitch [1]
 *
 * We do not currently deal with the UP registers as these control
 * weak resistors, so a small delay in change should not need to bring
 * these into the calculations.
 *
 * [1] this assumes that writing to a pin DAT whilst in SFN will set the
 *     state for when it is next output.
 */

static void s3c2410_pm_restore_gpio(int index, struct gpio_sleep *gps)
{
	void __iomem *base = gps->base;
	unsigned long gps_gpcon = gps->gpcon;
	unsigned long gps_gpdat = gps->gpdat;
	unsigned long old_gpcon;
	unsigned long old_gpdat;
	unsigned long old_gpup = 0x0;
	unsigned long gpcon;
	int nr;

	old_gpcon = __raw_readl(base + OFFS_CON);
	old_gpdat = __raw_readl(base + OFFS_DAT);

	if (base == S3C2410_GPACON) {
		/* GPACON only has one bit per control / data and no PULLUPs.
		 * GPACON[x] = 0 => Output, 1 => SFN */

		/* first set all SFN bits to SFN */

		gpcon = old_gpcon | gps->gpcon;
		__raw_writel(gpcon, base + OFFS_CON);

		/* now set all the other bits */

		__raw_writel(gps_gpdat, base + OFFS_DAT);
		__raw_writel(gps_gpcon, base + OFFS_CON);
	} else {
		unsigned long old, new, mask;
		unsigned long change_mask = 0x0;

		old_gpup = __raw_readl(base + OFFS_UP);

		/* Create a change_mask of all the items that need to have
		 * their CON value changed before their DAT value, so that
		 * we minimise the work between the two settings.
		 */

		for (nr = 0, mask = 0x03; nr < 32; nr += 2, mask <<= 2) {
			old = (old_gpcon & mask) >> nr;
			new = (gps_gpcon & mask) >> nr;

			/* If there is no change, then skip */

			if (old == new)
				continue;

			/* If both are special function, then skip */

			if (is_sfn(old) && is_sfn(new))
				continue;

			/* Change is IN => OUT, do not change now */

			if (is_in(old) && is_out(new))
				continue;

			/* Change is SFN => OUT, do not change now */

			if (is_sfn(old) && is_out(new))
				continue;

			/* We should now be at the case of IN=>SFN,
			 * OUT=>SFN, OUT=>IN, SFN=>IN. */

			change_mask |= mask;
		}

		/* Write the new CON settings */

		gpcon = old_gpcon & ~change_mask;
		gpcon |= gps_gpcon & change_mask;

		__raw_writel(gpcon, base + OFFS_CON);

		/* Now change any items that require DAT,CON */

		__raw_writel(gps_gpdat, base + OFFS_DAT);
		__raw_writel(gps_gpcon, base + OFFS_CON);
		__raw_writel(gps->gpup, base + OFFS_UP);
	}

	S3C_PMDBG("GPIO[%d] CON %08lx => %08lx, DAT %08lx => %08lx\n",
		  index, old_gpcon, gps_gpcon, old_gpdat, gps_gpdat);
}


/** s3c2410_pm_restore_gpios()
 *
 * Restore the state of the GPIOs
 */

static void s3c2410_pm_restore_gpios(void)
{
	struct gpio_sleep *gps = gpio_save;
	int gpio;

	for (gpio = 0; gpio < ARRAY_SIZE(gpio_save); gpio++, gps++) {
		s3c2410_pm_restore_gpio(gpio, gps);
	}
}

void (*pm_cpu_prep)(void);
void (*pm_cpu_sleep)(void);

#define any_allowed(mask, allow) (((mask) & (allow)) != (allow))

/* s3c2410_pm_enter
 *
 * central control for sleep/resume process
*/

static int s3c2410_pm_enter(suspend_state_t state)
{
	unsigned long regs_save[16];

	/* ensure the debug is initialised (if enabled) */

	s3c2410_pm_debug_init();

	S3C_PMDBG("s3c2410_pm_enter(%d)\n", state);

	if (pm_cpu_prep == NULL || pm_cpu_sleep == NULL) {
		printk(KERN_ERR PFX "error: no cpu sleep functions set\n");
		return -EINVAL;
	}

	/* check if we have anything to wake-up with... bad things seem
	 * to happen if you suspend with no wakeup (system will often
	 * require a full power-cycle)
	*/

	if (!any_allowed(s3c_irqwake_intmask, s3c_irqwake_intallow) &&
	    !any_allowed(s3c_irqwake_eintmask, s3c_irqwake_eintallow)) {
		printk(KERN_ERR PFX "No sources enabled for wake-up!\n");
		printk(KERN_ERR PFX "Aborting sleep\n");
		return -EINVAL;
	}

	/* prepare check area if configured */

	s3c_pm_check_prepare();

	/* store the physical address of the register recovery block */

	s3c_sleep_save_phys = virt_to_phys(regs_save);

	S3C_PMDBG("s3c_sleep_save_phys=0x%08lx\n", s3c_sleep_save_phys);

	/* save all necessary core registers not covered by the drivers */

	s3c2410_pm_save_gpios();
	s3c_pm_do_save(misc_save, ARRAY_SIZE(misc_save));
	s3c_pm_do_save(core_save, ARRAY_SIZE(core_save));
	s3c_pm_do_save(uart_save, ARRAY_SIZE(uart_save));

	/* set the irq configuration for wake */

	s3c2410_pm_configure_extint();

	S3C_PMDBG("sleep: irq wakeup masks: %08lx,%08lx\n",
	    s3c_irqwake_intmask, s3c_irqwake_eintmask);

	__raw_writel(s3c_irqwake_intmask, S3C2410_INTMSK);
	__raw_writel(s3c_irqwake_eintmask, S3C2410_EINTMASK);

	/* ack any outstanding external interrupts before we go to sleep */

	__raw_writel(__raw_readl(S3C2410_EINTPEND), S3C2410_EINTPEND);
	__raw_writel(__raw_readl(S3C2410_INTPND), S3C2410_INTPND);
	__raw_writel(__raw_readl(S3C2410_SRCPND), S3C2410_SRCPND);

	/* call cpu specific preparation */

	pm_cpu_prep();

	/* flush cache back to ram */

	flush_cache_all();

	s3c_pm_check_store();

	/* send the cpu to sleep... */

	__raw_writel(0x00, S3C2410_CLKCON);  /* turn off clocks over sleep */

	/* s3c2410_cpu_save will also act as our return point from when
	 * we resume as it saves its own register state, so use the return
	 * code to differentiate return from save and return from sleep */

	if (s3c2410_cpu_save(regs_save) == 0) {
		flush_cache_all();
		pm_cpu_sleep();
	}

	/* restore the cpu state */

	cpu_init();

	/* restore the system state */

	s3c_pm_do_restore_core(core_save, ARRAY_SIZE(core_save));
	s3c_pm_do_restore(misc_save, ARRAY_SIZE(misc_save));
	s3c_pm_do_restore(uart_save, ARRAY_SIZE(uart_save));
	s3c2410_pm_restore_gpios();

	s3c2410_pm_debug_init();

	/* check what irq (if any) restored the system */

	S3C_PMDBG("post sleep: IRQs 0x%08x, 0x%08x\n",
	    __raw_readl(S3C2410_SRCPND),
	    __raw_readl(S3C2410_EINTPEND));

	s3c2410_pm_show_resume_irqs(IRQ_EINT0, __raw_readl(S3C2410_SRCPND),
				    s3c_irqwake_intmask);

	s3c2410_pm_show_resume_irqs(IRQ_EINT4-4, __raw_readl(S3C2410_EINTPEND),
				    s3c_irqwake_eintmask);

	S3C_PMDBG("post sleep, preparing to return\n");

	s3c_pm_check_restore();

	/* ok, let's return from sleep */

	S3C_PMDBG("S3C2410 PM Resume (post-restore)\n");
	return 0;
}

static struct platform_suspend_ops s3c2410_pm_ops = {
	.enter		= s3c2410_pm_enter,
	.valid		= suspend_valid_only_mem,
};

/* s3c2410_pm_init
 *
 * Attach the power management functions. This should be called
 * from the board specific initialisation if the board supports
 * it.
*/

int __init s3c2410_pm_init(void)
{
	printk("S3C2410 Power Management, (c) 2004 Simtec Electronics\n");

	suspend_set_ops(&s3c2410_pm_ops);
	return 0;
}
Commit	Line	Data
a21765a7 BD	1	/* linux/arch/arm/plat-s3c24xx/pm.c
	2	*
	3	* Copyright (c) 2004,2006 Simtec Electronics
	4	* Ben Dooks <ben@simtec.co.uk>
	5	*
	6	* S3C24XX Power Manager (Suspend-To-RAM) support
	7	*
	8	* See Documentation/arm/Samsung-S3C24XX/Suspend.txt for more information
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License as published by
	12	* the Free Software Foundation; either version 2 of the License, or
	13	* (at your option) any later version.
	14	*
	15	* This program is distributed in the hope that it will be useful,
	16	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	18	* GNU General Public License for more details.
	19	*
	20	* You should have received a copy of the GNU General Public License
	21	* along with this program; if not, write to the Free Software
	22	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	23	*
	24	* Parts based on arch/arm/mach-pxa/pm.c
	25	*
	26	* Thanks to Dimitry Andric for debugging
	27	*/
	28
	29	#include <linux/init.h>
	30	#include <linux/suspend.h>
	31	#include <linux/errno.h>
	32	#include <linux/time.h>
	33	#include <linux/interrupt.h>
a21765a7	34	#include <linux/serial_core.h>
fced80c7	35	#include <linux/io.h>
a21765a7 BD	36
a21765a7 BD	37	#include <asm/cacheflush.h>
a09e64fb	38	#include <mach/hardware.h>
a21765a7	39
a2b7ba9c	40	#include <plat/regs-serial.h>
a09e64fb RK	41	#include <mach/regs-clock.h>
	42	#include <mach/regs-gpio.h>
	43	#include <mach/regs-mem.h>
	44	#include <mach/regs-irq.h>
a21765a7 BD	45
	46	#include <asm/mach/time.h>
	47
a2b7ba9c	48	#include <plat/pm.h>
a21765a7	49
a21765a7 BD	50
	51	#define PFX "s3c24xx-pm: "
	52
	53	static struct sleep_save core_save[] = {
	54	SAVE_ITEM(S3C2410_LOCKTIME),
	55	SAVE_ITEM(S3C2410_CLKCON),
	56
	57	/* we restore the timings here, with the proviso that the board
	58	* brings the system up in an slower, or equal frequency setting
	59	* to the original system.
	60	*
	61	* if we cannot guarantee this, then things are going to go very
	62	* wrong here, as we modify the refresh and both pll settings.
	63	*/
	64
	65	SAVE_ITEM(S3C2410_BWSCON),
	66	SAVE_ITEM(S3C2410_BANKCON0),
	67	SAVE_ITEM(S3C2410_BANKCON1),
	68	SAVE_ITEM(S3C2410_BANKCON2),
	69	SAVE_ITEM(S3C2410_BANKCON3),
	70	SAVE_ITEM(S3C2410_BANKCON4),
	71	SAVE_ITEM(S3C2410_BANKCON5),
	72
e425382e	73	#ifndef CONFIG_CPU_FREQ
a21765a7 BD	74	SAVE_ITEM(S3C2410_CLKDIVN),
a21765a7 BD	75	SAVE_ITEM(S3C2410_MPLLCON),
e425382e BD	76	SAVE_ITEM(S3C2410_REFRESH),
e425382e BD	77	#endif
a21765a7 BD	78	SAVE_ITEM(S3C2410_UPLLCON),
a21765a7 BD	79	SAVE_ITEM(S3C2410_CLKSLOW),
a21765a7 BD	80	};
a21765a7 BD	81
62feee64 BD	82	static struct gpio_sleep {
	83	void __iomem *base;
	84	unsigned int gpcon;
	85	unsigned int gpdat;
	86	unsigned int gpup;
	87	} gpio_save[] = {
	88	[0] = {
	89	.base = S3C2410_GPACON,
	90	},
	91	[1] = {
	92	.base = S3C2410_GPBCON,
	93	},
	94	[2] = {
	95	.base = S3C2410_GPCCON,
	96	},
	97	[3] = {
	98	.base = S3C2410_GPDCON,
	99	},
	100	[4] = {
	101	.base = S3C2410_GPECON,
	102	},
	103	[5] = {
	104	.base = S3C2410_GPFCON,
	105	},
	106	[6] = {
	107	.base = S3C2410_GPGCON,
	108	},
	109	[7] = {
	110	.base = S3C2410_GPHCON,
	111	},
	112	};
a21765a7	113
62feee64	114	static struct sleep_save misc_save[] = {
a21765a7 BD	115	SAVE_ITEM(S3C2410_DCLKCON),
	116	};
	117
	118	#ifdef CONFIG_S3C2410_PM_DEBUG
	119
	120	#define SAVE_UART(va) \
	121	SAVE_ITEM((va) + S3C2410_ULCON), \
	122	SAVE_ITEM((va) + S3C2410_UCON), \
	123	SAVE_ITEM((va) + S3C2410_UFCON), \
	124	SAVE_ITEM((va) + S3C2410_UMCON), \
	125	SAVE_ITEM((va) + S3C2410_UBRDIV)
	126
	127	static struct sleep_save uart_save[] = {
	128	SAVE_UART(S3C24XX_VA_UART0),
	129	SAVE_UART(S3C24XX_VA_UART1),
	130	#ifndef CONFIG_CPU_S3C2400
	131	SAVE_UART(S3C24XX_VA_UART2),
	132	#endif
	133	};
	134
	135	/* debug
	136	*
	137	* we send the debug to printascii() to allow it to be seen if the
	138	* system never wakes up from the sleep
	139	*/
	140
a21765a7 BD	141	static void s3c2410_pm_debug_init(void)
	142	{
	143	unsigned long tmp = __raw_readl(S3C2410_CLKCON);
	144
	145	/* re-start uart clocks */
	146	tmp \|= S3C2410_CLKCON_UART0;
	147	tmp \|= S3C2410_CLKCON_UART1;
	148	tmp \|= S3C2410_CLKCON_UART2;
	149
	150	__raw_writel(tmp, S3C2410_CLKCON);
	151	udelay(10);
	152	}
	153
a21765a7	154	#else
a21765a7 BD	155	#define s3c2410_pm_debug_init() do { } while(0)
	156
	157	static struct sleep_save uart_save[] = {};
	158	#endif
	159
a21765a7 BD	160	/* s3c2410_pm_show_resume_irqs
	161	*
	162	* print any IRQs asserted at resume time (ie, we woke from)
	163	*/
	164
	165	static void s3c2410_pm_show_resume_irqs(int start, unsigned long which,
	166	unsigned long mask)
	167	{
	168	int i;
	169
	170	which &= ~mask;
	171
	172	for (i = 0; i <= 31; i++) {
	173	if ((which) & (1L<<i)) {
6419711a	174	S3C_PMDBG("IRQ %d asserted at resume\n", start+i);
a21765a7 BD	175	}
	176	}
	177	}
	178
549c7e33	179	/* s3c_pm_check_resume_pin
a21765a7 BD	180	*
	181	* check to see if the pin is configured correctly for sleep mode, and
	182	* make any necessary adjustments if it is not
	183	*/
	184
549c7e33	185	static void s3c_pm_check_resume_pin(unsigned int pin, unsigned int irqoffs)
a21765a7 BD	186	{
	187	unsigned long irqstate;
	188	unsigned long pinstate;
	189	int irq = s3c2410_gpio_getirq(pin);
	190
	191	if (irqoffs < 4)
	192	irqstate = s3c_irqwake_intmask & (1L<<irqoffs);
	193	else
	194	irqstate = s3c_irqwake_eintmask & (1L<<irqoffs);
	195
	196	pinstate = s3c2410_gpio_getcfg(pin);
	197
	198	if (!irqstate) {
	199	if (pinstate == S3C2410_GPIO_IRQ)
6419711a	200	S3C_PMDBG("Leaving IRQ %d (pin %d) enabled\n", irq, pin);
a21765a7 BD	201	} else {
a21765a7 BD	202	if (pinstate == S3C2410_GPIO_IRQ) {
6419711a	203	S3C_PMDBG("Disabling IRQ %d (pin %d)\n", irq, pin);
a21765a7 BD	204	s3c2410_gpio_cfgpin(pin, S3C2410_GPIO_INPUT);
	205	}
	206	}
	207	}
	208
	209	/* s3c2410_pm_configure_extint
	210	*
	211	* configure all external interrupt pins
	212	*/
	213
	214	static void s3c2410_pm_configure_extint(void)
	215	{
	216	int pin;
	217
	218	/* for each of the external interrupts (EINT0..EINT15) we
	219	* need to check wether it is an external interrupt source,
	220	* and then configure it as an input if it is not
	221	*/
	222
	223	for (pin = S3C2410_GPF0; pin <= S3C2410_GPF7; pin++) {
549c7e33	224	s3c_pm_check_resume_pin(pin, pin - S3C2410_GPF0);
a21765a7 BD	225	}
	226
	227	for (pin = S3C2410_GPG0; pin <= S3C2410_GPG7; pin++) {
549c7e33	228	s3c_pm_check_resume_pin(pin, (pin - S3C2410_GPG0)+8);
a21765a7 BD	229	}
	230	}
	231
62feee64 BD	232	/* offsets for CON/DAT/UP registers */
	233
	234	#define OFFS_CON (S3C2410_GPACON - S3C2410_GPACON)
	235	#define OFFS_DAT (S3C2410_GPADAT - S3C2410_GPACON)
	236	#define OFFS_UP (S3C2410_GPBUP - S3C2410_GPBCON)
	237
	238	/* s3c2410_pm_save_gpios()
	239	*
	240	* Save the state of the GPIOs
	241	*/
	242
	243	static void s3c2410_pm_save_gpios(void)
	244	{
	245	struct gpio_sleep *gps = gpio_save;
	246	unsigned int gpio;
	247
	248	for (gpio = 0; gpio < ARRAY_SIZE(gpio_save); gpio++, gps++) {
	249	void __iomem *base = gps->base;
	250
	251	gps->gpcon = __raw_readl(base + OFFS_CON);
	252	gps->gpdat = __raw_readl(base + OFFS_DAT);
	253
	254	if (gpio > 0)
	255	gps->gpup = __raw_readl(base + OFFS_UP);
	256
	257	}
	258	}
	259
	260	/* Test whether the given masked+shifted bits of an GPIO configuration
	261	* are one of the SFN (special function) modes. */
	262
	263	static inline int is_sfn(unsigned long con)
	264	{
	265	return (con == 2 \|\| con == 3);
	266	}
	267
	268	/* Test if the given masked+shifted GPIO configuration is an input */
	269
	270	static inline int is_in(unsigned long con)
	271	{
	272	return con == 0;
	273	}
	274
	275	/* Test if the given masked+shifted GPIO configuration is an output */
	276
	277	static inline int is_out(unsigned long con)
	278	{
	279	return con == 1;
	280	}
	281
	282	/* s3c2410_pm_restore_gpio()
	283	*
	284	* Restore one of the GPIO banks that was saved during suspend. This is
	285	* not as simple as once thought, due to the possibility of glitches
	286	* from the order that the CON and DAT registers are set in.
	287	*
	288	* The three states the pin can be are {IN,OUT,SFN} which gives us 9
	289	* combinations of changes to check. Three of these, if the pin stays
	290	* in the same configuration can be discounted. This leaves us with
	291	* the following:
	292	*
	293	* { IN => OUT } Change DAT first
	294	* { IN => SFN } Change CON first
	295	* { OUT => SFN } Change CON first, so new data will not glitch
296	* { OUT => IN } Change CON first, so new data will not glitch
297	* { SFN => IN } Change CON first
298	* { SFN => OUT } Change DAT first, so new data will not glitch [1]
299	*
300	* We do not currently deal with the UP registers as these control
301	* weak resistors, so a small delay in change should not need to bring
302	* these into the calculations.
303	*
304	* [1] this assumes that writing to a pin DAT whilst in SFN will set the
305	* state for when it is next output.
306	*/
307
308	static void s3c2410_pm_restore_gpio(int index, struct gpio_sleep *gps)
309	{
310	void __iomem *base = gps->base;
311	unsigned long gps_gpcon = gps->gpcon;
312	unsigned long gps_gpdat = gps->gpdat;
313	unsigned long old_gpcon;
314	unsigned long old_gpdat;
315	unsigned long old_gpup = 0x0;
316	unsigned long gpcon;
317	int nr;
318
319	old_gpcon = __raw_readl(base + OFFS_CON);
320	old_gpdat = __raw_readl(base + OFFS_DAT);
321
322	if (base == S3C2410_GPACON) {
323	/* GPACON only has one bit per control / data and no PULLUPs.
324	* GPACON[x] = 0 => Output, 1 => SFN */
325
326	/* first set all SFN bits to SFN */
327
328	gpcon = old_gpcon \| gps->gpcon;
329	__raw_writel(gpcon, base + OFFS_CON);
330
331	/* now set all the other bits */
332
333	__raw_writel(gps_gpdat, base + OFFS_DAT);
334	__raw_writel(gps_gpcon, base + OFFS_CON);
335	} else {
336	unsigned long old, new, mask;
337	unsigned long change_mask = 0x0;
338
339	old_gpup = __raw_readl(base + OFFS_UP);
340
341	/* Create a change_mask of all the items that need to have
342	* their CON value changed before their DAT value, so that
343	* we minimise the work between the two settings.
344	*/
345
346	for (nr = 0, mask = 0x03; nr < 32; nr += 2, mask <<= 2) {
347	old = (old_gpcon & mask) >> nr;
348	new = (gps_gpcon & mask) >> nr;
349
350	/* If there is no change, then skip */
351
352	if (old == new)
353	continue;
354
355	/* If both are special function, then skip */
356
357	if (is_sfn(old) && is_sfn(new))
358	continue;
359
360	/* Change is IN => OUT, do not change now */
361
362	if (is_in(old) && is_out(new))
363	continue;
364
365	/* Change is SFN => OUT, do not change now */
366
367	if (is_sfn(old) && is_out(new))
368	continue;
369
370	/* We should now be at the case of IN=>SFN,
371	* OUT=>SFN, OUT=>IN, SFN=>IN. */
372
373	change_mask \|= mask;
374	}
375
376	/* Write the new CON settings */
377
378	gpcon = old_gpcon & ~change_mask;
379	gpcon \|= gps_gpcon & change_mask;
380
381	__raw_writel(gpcon, base + OFFS_CON);
382
383	/* Now change any items that require DAT,CON */
384
385	__raw_writel(gps_gpdat, base + OFFS_DAT);
386	__raw_writel(gps_gpcon, base + OFFS_CON);
387	__raw_writel(gps->gpup, base + OFFS_UP);
388	}
389
6419711a BD	390	S3C_PMDBG("GPIO[%d] CON %08lx => %08lx, DAT %08lx => %08lx\n",
6419711a BD	391	index, old_gpcon, gps_gpcon, old_gpdat, gps_gpdat);
62feee64 BD	392	}
	393
	394
	395	/** s3c2410_pm_restore_gpios()
	396	*
	397	* Restore the state of the GPIOs
	398	*/
	399
	400	static void s3c2410_pm_restore_gpios(void)
	401	{
	402	struct gpio_sleep *gps = gpio_save;
	403	int gpio;
	404
	405	for (gpio = 0; gpio < ARRAY_SIZE(gpio_save); gpio++, gps++) {
	406	s3c2410_pm_restore_gpio(gpio, gps);
	407	}
	408	}
	409
a21765a7 BD	410	void (*pm_cpu_prep)(void);
	411	void (*pm_cpu_sleep)(void);
	412
	413	#define any_allowed(mask, allow) (((mask) & (allow)) != (allow))
	414
	415	/* s3c2410_pm_enter
	416	*
	417	* central control for sleep/resume process
	418	*/
	419
	420	static int s3c2410_pm_enter(suspend_state_t state)
	421	{
	422	unsigned long regs_save[16];
	423
	424	/* ensure the debug is initialised (if enabled) */
	425
	426	s3c2410_pm_debug_init();
	427
6419711a	428	S3C_PMDBG("s3c2410_pm_enter(%d)\n", state);
a21765a7 BD	429
	430	if (pm_cpu_prep == NULL \|\| pm_cpu_sleep == NULL) {
	431	printk(KERN_ERR PFX "error: no cpu sleep functions set\n");
	432	return -EINVAL;
	433	}
	434
a21765a7 BD	435	/* check if we have anything to wake-up with... bad things seem
	436	* to happen if you suspend with no wakeup (system will often
	437	* require a full power-cycle)
	438	*/
	439
	440	if (!any_allowed(s3c_irqwake_intmask, s3c_irqwake_intallow) &&
	441	!any_allowed(s3c_irqwake_eintmask, s3c_irqwake_eintallow)) {
	442	printk(KERN_ERR PFX "No sources enabled for wake-up!\n");
	443	printk(KERN_ERR PFX "Aborting sleep\n");
	444	return -EINVAL;
	445	}
	446
	447	/* prepare check area if configured */
	448
549c7e33	449	s3c_pm_check_prepare();
a21765a7 BD	450
	451	/* store the physical address of the register recovery block */
	452
6419711a	453	s3c_sleep_save_phys = virt_to_phys(regs_save);
a21765a7	454
6419711a	455	S3C_PMDBG("s3c_sleep_save_phys=0x%08lx\n", s3c_sleep_save_phys);
a21765a7 BD	456
	457	/* save all necessary core registers not covered by the drivers */
	458
62feee64	459	s3c2410_pm_save_gpios();
6419711a BD	460	s3c_pm_do_save(misc_save, ARRAY_SIZE(misc_save));
	461	s3c_pm_do_save(core_save, ARRAY_SIZE(core_save));
	462	s3c_pm_do_save(uart_save, ARRAY_SIZE(uart_save));
a21765a7 BD	463
	464	/* set the irq configuration for wake */
	465
	466	s3c2410_pm_configure_extint();
	467
6419711a	468	S3C_PMDBG("sleep: irq wakeup masks: %08lx,%08lx\n",
a21765a7 BD	469	s3c_irqwake_intmask, s3c_irqwake_eintmask);
	470
	471	__raw_writel(s3c_irqwake_intmask, S3C2410_INTMSK);
	472	__raw_writel(s3c_irqwake_eintmask, S3C2410_EINTMASK);
	473
	474	/* ack any outstanding external interrupts before we go to sleep */
	475
	476	__raw_writel(__raw_readl(S3C2410_EINTPEND), S3C2410_EINTPEND);
	477	__raw_writel(__raw_readl(S3C2410_INTPND), S3C2410_INTPND);
	478	__raw_writel(__raw_readl(S3C2410_SRCPND), S3C2410_SRCPND);
	479
6cbdc8c5	480	/* call cpu specific preparation */
a21765a7 BD	481
	482	pm_cpu_prep();
	483
	484	/* flush cache back to ram */
	485
	486	flush_cache_all();
	487
549c7e33	488	s3c_pm_check_store();
a21765a7 BD	489
	490	/* send the cpu to sleep... */
	491
	492	__raw_writel(0x00, S3C2410_CLKCON); /* turn off clocks over sleep */
	493
	494	/* s3c2410_cpu_save will also act as our return point from when
	495	* we resume as it saves its own register state, so use the return
	496	* code to differentiate return from save and return from sleep */
	497
	498	if (s3c2410_cpu_save(regs_save) == 0) {
	499	flush_cache_all();
	500	pm_cpu_sleep();
	501	}
	502
	503	/* restore the cpu state */
	504
	505	cpu_init();
	506
	507	/* restore the system state */
	508
6419711a BD	509	s3c_pm_do_restore_core(core_save, ARRAY_SIZE(core_save));
	510	s3c_pm_do_restore(misc_save, ARRAY_SIZE(misc_save));
	511	s3c_pm_do_restore(uart_save, ARRAY_SIZE(uart_save));
62feee64	512	s3c2410_pm_restore_gpios();
a21765a7 BD	513
	514	s3c2410_pm_debug_init();
	515
	516	/* check what irq (if any) restored the system */
	517
6419711a	518	S3C_PMDBG("post sleep: IRQs 0x%08x, 0x%08x\n",
a21765a7 BD	519	__raw_readl(S3C2410_SRCPND),
	520	__raw_readl(S3C2410_EINTPEND));
	521
	522	s3c2410_pm_show_resume_irqs(IRQ_EINT0, __raw_readl(S3C2410_SRCPND),
	523	s3c_irqwake_intmask);
	524
	525	s3c2410_pm_show_resume_irqs(IRQ_EINT4-4, __raw_readl(S3C2410_EINTPEND),
	526	s3c_irqwake_eintmask);
	527
6419711a	528	S3C_PMDBG("post sleep, preparing to return\n");
a21765a7	529
549c7e33	530	s3c_pm_check_restore();
a21765a7 BD	531
	532	/* ok, let's return from sleep */
	533
6419711a	534	S3C_PMDBG("S3C2410 PM Resume (post-restore)\n");
a21765a7 BD	535	return 0;
	536	}
	537
26398a70	538	static struct platform_suspend_ops s3c2410_pm_ops = {
a21765a7	539	.enter = s3c2410_pm_enter,
26398a70	540	.valid = suspend_valid_only_mem,
a21765a7 BD	541	};
	542
	543	/* s3c2410_pm_init
	544	*
	545	* Attach the power management functions. This should be called
	546	* from the board specific initialisation if the board supports
	547	* it.
	548	*/
	549
	550	int __init s3c2410_pm_init(void)
	551	{
	552	printk("S3C2410 Power Management, (c) 2004 Simtec Electronics\n");
	553
26398a70	554	suspend_set_ops(&s3c2410_pm_ops);
a21765a7 BD	555	return 0;
a21765a7 BD	556	}