[linux-2.6-block.git] / arch / arm / plat-s3c24xx / irq.c

/* linux/arch/arm/plat-s3c24xx/irq.c
 *
 * Copyright (c) 2003-2004 Simtec Electronics
 *	Ben Dooks <ben@simtec.co.uk>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
*/

#include <linux/init.h>
#include <linux/module.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/device.h>
#include <linux/syscore_ops.h>

#include <asm/irq.h>
#include <asm/mach/irq.h>

#include <plat/regs-irqtype.h>

#include <plat/cpu.h>
#include <plat/pm.h>
#include <plat/irq.h>

static void
s3c_irq_mask(struct irq_data *data)
{
	unsigned int irqno = data->irq - IRQ_EINT0;
	unsigned long mask;

	mask = __raw_readl(S3C2410_INTMSK);
	mask |= 1UL << irqno;
	__raw_writel(mask, S3C2410_INTMSK);
}

static inline void
s3c_irq_ack(struct irq_data *data)
{
	unsigned long bitval = 1UL << (data->irq - IRQ_EINT0);

	__raw_writel(bitval, S3C2410_SRCPND);
	__raw_writel(bitval, S3C2410_INTPND);
}

static inline void
s3c_irq_maskack(struct irq_data *data)
{
	unsigned long bitval = 1UL << (data->irq - IRQ_EINT0);
	unsigned long mask;

	mask = __raw_readl(S3C2410_INTMSK);
	__raw_writel(mask|bitval, S3C2410_INTMSK);

	__raw_writel(bitval, S3C2410_SRCPND);
	__raw_writel(bitval, S3C2410_INTPND);
}


static void
s3c_irq_unmask(struct irq_data *data)
{
	unsigned int irqno = data->irq;
	unsigned long mask;

	if (irqno != IRQ_TIMER4 && irqno != IRQ_EINT8t23)
		irqdbf2("s3c_irq_unmask %d\n", irqno);

	irqno -= IRQ_EINT0;

	mask = __raw_readl(S3C2410_INTMSK);
	mask &= ~(1UL << irqno);
	__raw_writel(mask, S3C2410_INTMSK);
}

struct irq_chip s3c_irq_level_chip = {
	.name		= "s3c-level",
	.irq_ack	= s3c_irq_maskack,
	.irq_mask	= s3c_irq_mask,
	.irq_unmask	= s3c_irq_unmask,
	.irq_set_wake	= s3c_irq_wake
};

struct irq_chip s3c_irq_chip = {
	.name		= "s3c",
	.irq_ack	= s3c_irq_ack,
	.irq_mask	= s3c_irq_mask,
	.irq_unmask	= s3c_irq_unmask,
	.irq_set_wake	= s3c_irq_wake
};

static void
s3c_irqext_mask(struct irq_data *data)
{
	unsigned int irqno = data->irq - EXTINT_OFF;
	unsigned long mask;

	mask = __raw_readl(S3C24XX_EINTMASK);
	mask |= ( 1UL << irqno);
	__raw_writel(mask, S3C24XX_EINTMASK);
}

static void
s3c_irqext_ack(struct irq_data *data)
{
	unsigned long req;
	unsigned long bit;
	unsigned long mask;

	bit = 1UL << (data->irq - EXTINT_OFF);

	mask = __raw_readl(S3C24XX_EINTMASK);

	__raw_writel(bit, S3C24XX_EINTPEND);

	req = __raw_readl(S3C24XX_EINTPEND);
	req &= ~mask;

	/* not sure if we should be acking the parent irq... */

	if (data->irq <= IRQ_EINT7) {
		if ((req & 0xf0) == 0)
			s3c_irq_ack(irq_get_irq_data(IRQ_EINT4t7));
	} else {
		if ((req >> 8) == 0)
			s3c_irq_ack(irq_get_irq_data(IRQ_EINT8t23));
	}
}

static void
s3c_irqext_unmask(struct irq_data *data)
{
	unsigned int irqno = data->irq - EXTINT_OFF;
	unsigned long mask;

	mask = __raw_readl(S3C24XX_EINTMASK);
	mask &= ~(1UL << irqno);
	__raw_writel(mask, S3C24XX_EINTMASK);
}

int
s3c_irqext_type(struct irq_data *data, unsigned int type)
{
	void __iomem *extint_reg;
	void __iomem *gpcon_reg;
	unsigned long gpcon_offset, extint_offset;
	unsigned long newvalue = 0, value;

	if ((data->irq >= IRQ_EINT0) && (data->irq <= IRQ_EINT3)) {
		gpcon_reg = S3C2410_GPFCON;
		extint_reg = S3C24XX_EXTINT0;
		gpcon_offset = (data->irq - IRQ_EINT0) * 2;
		extint_offset = (data->irq - IRQ_EINT0) * 4;
	} else if ((data->irq >= IRQ_EINT4) && (data->irq <= IRQ_EINT7)) {
		gpcon_reg = S3C2410_GPFCON;
		extint_reg = S3C24XX_EXTINT0;
		gpcon_offset = (data->irq - (EXTINT_OFF)) * 2;
		extint_offset = (data->irq - (EXTINT_OFF)) * 4;
	} else if ((data->irq >= IRQ_EINT8) && (data->irq <= IRQ_EINT15)) {
		gpcon_reg = S3C2410_GPGCON;
		extint_reg = S3C24XX_EXTINT1;
		gpcon_offset = (data->irq - IRQ_EINT8) * 2;
		extint_offset = (data->irq - IRQ_EINT8) * 4;
	} else if ((data->irq >= IRQ_EINT16) && (data->irq <= IRQ_EINT23)) {
		gpcon_reg = S3C2410_GPGCON;
		extint_reg = S3C24XX_EXTINT2;
		gpcon_offset = (data->irq - IRQ_EINT8) * 2;
		extint_offset = (data->irq - IRQ_EINT16) * 4;
	} else {
		return -1;
	}

	/* Set the GPIO to external interrupt mode */
	value = __raw_readl(gpcon_reg);
	value = (value & ~(3 << gpcon_offset)) | (0x02 << gpcon_offset);
	__raw_writel(value, gpcon_reg);

	/* Set the external interrupt to pointed trigger type */
	switch (type)
	{
		case IRQ_TYPE_NONE:
			printk(KERN_WARNING "No edge setting!\n");
			break;

		case IRQ_TYPE_EDGE_RISING:
			newvalue = S3C2410_EXTINT_RISEEDGE;
			break;

		case IRQ_TYPE_EDGE_FALLING:
			newvalue = S3C2410_EXTINT_FALLEDGE;
			break;

		case IRQ_TYPE_EDGE_BOTH:
			newvalue = S3C2410_EXTINT_BOTHEDGE;
			break;

		case IRQ_TYPE_LEVEL_LOW:
			newvalue = S3C2410_EXTINT_LOWLEV;
			break;

		case IRQ_TYPE_LEVEL_HIGH:
			newvalue = S3C2410_EXTINT_HILEV;
			break;

		default:
			printk(KERN_ERR "No such irq type %d", type);
			return -1;
	}

	value = __raw_readl(extint_reg);
	value = (value & ~(7 << extint_offset)) | (newvalue << extint_offset);
	__raw_writel(value, extint_reg);

	return 0;
}

static struct irq_chip s3c_irqext_chip = {
	.name		= "s3c-ext",
	.irq_mask	= s3c_irqext_mask,
	.irq_unmask	= s3c_irqext_unmask,
	.irq_ack	= s3c_irqext_ack,
	.irq_set_type	= s3c_irqext_type,
	.irq_set_wake	= s3c_irqext_wake
};

static struct irq_chip s3c_irq_eint0t4 = {
	.name		= "s3c-ext0",
	.irq_ack	= s3c_irq_ack,
	.irq_mask	= s3c_irq_mask,
	.irq_unmask	= s3c_irq_unmask,
	.irq_set_wake	= s3c_irq_wake,
	.irq_set_type	= s3c_irqext_type,
};

/* mask values for the parent registers for each of the interrupt types */

#define INTMSK_UART0	 (1UL << (IRQ_UART0 - IRQ_EINT0))
#define INTMSK_UART1	 (1UL << (IRQ_UART1 - IRQ_EINT0))
#define INTMSK_UART2	 (1UL << (IRQ_UART2 - IRQ_EINT0))
#define INTMSK_ADCPARENT (1UL << (IRQ_ADCPARENT - IRQ_EINT0))


/* UART0 */

static void
s3c_irq_uart0_mask(struct irq_data *data)
{
	s3c_irqsub_mask(data->irq, INTMSK_UART0, 7);
}

static void
s3c_irq_uart0_unmask(struct irq_data *data)
{
	s3c_irqsub_unmask(data->irq, INTMSK_UART0);
}

static void
s3c_irq_uart0_ack(struct irq_data *data)
{
	s3c_irqsub_maskack(data->irq, INTMSK_UART0, 7);
}

static struct irq_chip s3c_irq_uart0 = {
	.name		= "s3c-uart0",
	.irq_mask	= s3c_irq_uart0_mask,
	.irq_unmask	= s3c_irq_uart0_unmask,
	.irq_ack	= s3c_irq_uart0_ack,
};

/* UART1 */

static void
s3c_irq_uart1_mask(struct irq_data *data)
{
	s3c_irqsub_mask(data->irq, INTMSK_UART1, 7 << 3);
}

static void
s3c_irq_uart1_unmask(struct irq_data *data)
{
	s3c_irqsub_unmask(data->irq, INTMSK_UART1);
}

static void
s3c_irq_uart1_ack(struct irq_data *data)
{
	s3c_irqsub_maskack(data->irq, INTMSK_UART1, 7 << 3);
}

static struct irq_chip s3c_irq_uart1 = {
	.name		= "s3c-uart1",
	.irq_mask	= s3c_irq_uart1_mask,
	.irq_unmask	= s3c_irq_uart1_unmask,
	.irq_ack	= s3c_irq_uart1_ack,
};

/* UART2 */

static void
s3c_irq_uart2_mask(struct irq_data *data)
{
	s3c_irqsub_mask(data->irq, INTMSK_UART2, 7 << 6);
}

static void
s3c_irq_uart2_unmask(struct irq_data *data)
{
	s3c_irqsub_unmask(data->irq, INTMSK_UART2);
}

static void
s3c_irq_uart2_ack(struct irq_data *data)
{
	s3c_irqsub_maskack(data->irq, INTMSK_UART2, 7 << 6);
}

static struct irq_chip s3c_irq_uart2 = {
	.name		= "s3c-uart2",
	.irq_mask	= s3c_irq_uart2_mask,
	.irq_unmask	= s3c_irq_uart2_unmask,
	.irq_ack	= s3c_irq_uart2_ack,
};

/* ADC and Touchscreen */

static void
s3c_irq_adc_mask(struct irq_data *d)
{
	s3c_irqsub_mask(d->irq, INTMSK_ADCPARENT, 3 << 9);
}

static void
s3c_irq_adc_unmask(struct irq_data *d)
{
	s3c_irqsub_unmask(d->irq, INTMSK_ADCPARENT);
}

static void
s3c_irq_adc_ack(struct irq_data *d)
{
	s3c_irqsub_ack(d->irq, INTMSK_ADCPARENT, 3 << 9);
}

static struct irq_chip s3c_irq_adc = {
	.name		= "s3c-adc",
	.irq_mask	= s3c_irq_adc_mask,
	.irq_unmask	= s3c_irq_adc_unmask,
	.irq_ack	= s3c_irq_adc_ack,
};

/* irq demux for adc */
static void s3c_irq_demux_adc(unsigned int irq,
			      struct irq_desc *desc)
{
	unsigned int subsrc, submsk;
	unsigned int offset = 9;

	/* read the current pending interrupts, and the mask
	 * for what it is available */

	subsrc = __raw_readl(S3C2410_SUBSRCPND);
	submsk = __raw_readl(S3C2410_INTSUBMSK);

	subsrc &= ~submsk;
	subsrc >>= offset;
	subsrc &= 3;

	if (subsrc != 0) {
		if (subsrc & 1) {
			generic_handle_irq(IRQ_TC);
		}
		if (subsrc & 2) {
			generic_handle_irq(IRQ_ADC);
		}
	}
}

static void s3c_irq_demux_uart(unsigned int start)
{
	unsigned int subsrc, submsk;
	unsigned int offset = start - IRQ_S3CUART_RX0;

	/* read the current pending interrupts, and the mask
	 * for what it is available */

	subsrc = __raw_readl(S3C2410_SUBSRCPND);
	submsk = __raw_readl(S3C2410_INTSUBMSK);

	irqdbf2("s3c_irq_demux_uart: start=%d (%d), subsrc=0x%08x,0x%08x\n",
		start, offset, subsrc, submsk);

	subsrc &= ~submsk;
	subsrc >>= offset;
	subsrc &= 7;

	if (subsrc != 0) {
		if (subsrc & 1)
			generic_handle_irq(start);

		if (subsrc & 2)
			generic_handle_irq(start+1);

		if (subsrc & 4)
			generic_handle_irq(start+2);
	}
}

/* uart demux entry points */

static void
s3c_irq_demux_uart0(unsigned int irq,
		    struct irq_desc *desc)
{
	irq = irq;
	s3c_irq_demux_uart(IRQ_S3CUART_RX0);
}

static void
s3c_irq_demux_uart1(unsigned int irq,
		    struct irq_desc *desc)
{
	irq = irq;
	s3c_irq_demux_uart(IRQ_S3CUART_RX1);
}

static void
s3c_irq_demux_uart2(unsigned int irq,
		    struct irq_desc *desc)
{
	irq = irq;
	s3c_irq_demux_uart(IRQ_S3CUART_RX2);
}

static void
s3c_irq_demux_extint8(unsigned int irq,
		      struct irq_desc *desc)
{
	unsigned long eintpnd = __raw_readl(S3C24XX_EINTPEND);
	unsigned long eintmsk = __raw_readl(S3C24XX_EINTMASK);

	eintpnd &= ~eintmsk;
	eintpnd &= ~0xff;	/* ignore lower irqs */

	/* we may as well handle all the pending IRQs here */

	while (eintpnd) {
		irq = __ffs(eintpnd);
		eintpnd &= ~(1<<irq);

		irq += (IRQ_EINT4 - 4);
		generic_handle_irq(irq);
	}

}

static void
s3c_irq_demux_extint4t7(unsigned int irq,
			struct irq_desc *desc)
{
	unsigned long eintpnd = __raw_readl(S3C24XX_EINTPEND);
	unsigned long eintmsk = __raw_readl(S3C24XX_EINTMASK);

	eintpnd &= ~eintmsk;
	eintpnd &= 0xff;	/* only lower irqs */

	/* we may as well handle all the pending IRQs here */

	while (eintpnd) {
		irq = __ffs(eintpnd);
		eintpnd &= ~(1<<irq);

		irq += (IRQ_EINT4 - 4);

		generic_handle_irq(irq);
	}
}

#ifdef CONFIG_FIQ
/**
 * s3c24xx_set_fiq - set the FIQ routing
 * @irq: IRQ number to route to FIQ on processor.
 * @on: Whether to route @irq to the FIQ, or to remove the FIQ routing.
 *
 * Change the state of the IRQ to FIQ routing depending on @irq and @on. If
 * @on is true, the @irq is checked to see if it can be routed and the
 * interrupt controller updated to route the IRQ. If @on is false, the FIQ
 * routing is cleared, regardless of which @irq is specified.
 */
int s3c24xx_set_fiq(unsigned int irq, bool on)
{
	u32 intmod;
	unsigned offs;

	if (on) {
		offs = irq - FIQ_START;
		if (offs > 31)
			return -EINVAL;

		intmod = 1 << offs;
	} else {
		intmod = 0;
	}

	__raw_writel(intmod, S3C2410_INTMOD);
	return 0;
}

EXPORT_SYMBOL_GPL(s3c24xx_set_fiq);
#endif


/* s3c24xx_init_irq
 *
 * Initialise S3C2410 IRQ system
*/

void __init s3c24xx_init_irq(void)
{
	unsigned long pend;
	unsigned long last;
	int irqno;
	int i;

#ifdef CONFIG_FIQ
	init_FIQ(FIQ_START);
#endif

	irqdbf("s3c2410_init_irq: clearing interrupt status flags\n");

	/* first, clear all interrupts pending... */

	last = 0;
	for (i = 0; i < 4; i++) {
		pend = __raw_readl(S3C24XX_EINTPEND);

		if (pend == 0 || pend == last)
			break;

		__raw_writel(pend, S3C24XX_EINTPEND);
		printk("irq: clearing pending ext status %08x\n", (int)pend);
		last = pend;
	}

	last = 0;
	for (i = 0; i < 4; i++) {
		pend = __raw_readl(S3C2410_INTPND);

		if (pend == 0 || pend == last)
			break;

		__raw_writel(pend, S3C2410_SRCPND);
		__raw_writel(pend, S3C2410_INTPND);
		printk("irq: clearing pending status %08x\n", (int)pend);
		last = pend;
	}

	last = 0;
	for (i = 0; i < 4; i++) {
		pend = __raw_readl(S3C2410_SUBSRCPND);

		if (pend == 0 || pend == last)
			break;

		printk("irq: clearing subpending status %08x\n", (int)pend);
		__raw_writel(pend, S3C2410_SUBSRCPND);
		last = pend;
	}

	/* register the main interrupts */

	irqdbf("s3c2410_init_irq: registering s3c2410 interrupt handlers\n");

	for (irqno = IRQ_EINT4t7; irqno <= IRQ_ADCPARENT; irqno++) {
		/* set all the s3c2410 internal irqs */

		switch (irqno) {
			/* deal with the special IRQs (cascaded) */

		case IRQ_EINT4t7:
		case IRQ_EINT8t23:
		case IRQ_UART0:
		case IRQ_UART1:
		case IRQ_UART2:
		case IRQ_ADCPARENT:
			irq_set_chip_and_handler(irqno, &s3c_irq_level_chip,
						 handle_level_irq);
			break;

		case IRQ_RESERVED6:
		case IRQ_RESERVED24:
			/* no IRQ here */
			break;

		default:
			//irqdbf("registering irq %d (s3c irq)\n", irqno);
			irq_set_chip_and_handler(irqno, &s3c_irq_chip,
						 handle_edge_irq);
			set_irq_flags(irqno, IRQF_VALID);
		}
	}

	/* setup the cascade irq handlers */

	irq_set_chained_handler(IRQ_EINT4t7, s3c_irq_demux_extint4t7);
	irq_set_chained_handler(IRQ_EINT8t23, s3c_irq_demux_extint8);

	irq_set_chained_handler(IRQ_UART0, s3c_irq_demux_uart0);
	irq_set_chained_handler(IRQ_UART1, s3c_irq_demux_uart1);
	irq_set_chained_handler(IRQ_UART2, s3c_irq_demux_uart2);
	irq_set_chained_handler(IRQ_ADCPARENT, s3c_irq_demux_adc);

	/* external interrupts */

	for (irqno = IRQ_EINT0; irqno <= IRQ_EINT3; irqno++) {
		irqdbf("registering irq %d (ext int)\n", irqno);
		irq_set_chip_and_handler(irqno, &s3c_irq_eint0t4,
					 handle_edge_irq);
		set_irq_flags(irqno, IRQF_VALID);
	}

	for (irqno = IRQ_EINT4; irqno <= IRQ_EINT23; irqno++) {
		irqdbf("registering irq %d (extended s3c irq)\n", irqno);
		irq_set_chip_and_handler(irqno, &s3c_irqext_chip,
					 handle_edge_irq);
		set_irq_flags(irqno, IRQF_VALID);
	}

	/* register the uart interrupts */

	irqdbf("s3c2410: registering external interrupts\n");

	for (irqno = IRQ_S3CUART_RX0; irqno <= IRQ_S3CUART_ERR0; irqno++) {
		irqdbf("registering irq %d (s3c uart0 irq)\n", irqno);
		irq_set_chip_and_handler(irqno, &s3c_irq_uart0,
					 handle_level_irq);
		set_irq_flags(irqno, IRQF_VALID);
	}

	for (irqno = IRQ_S3CUART_RX1; irqno <= IRQ_S3CUART_ERR1; irqno++) {
		irqdbf("registering irq %d (s3c uart1 irq)\n", irqno);
		irq_set_chip_and_handler(irqno, &s3c_irq_uart1,
					 handle_level_irq);
		set_irq_flags(irqno, IRQF_VALID);
	}

	for (irqno = IRQ_S3CUART_RX2; irqno <= IRQ_S3CUART_ERR2; irqno++) {
		irqdbf("registering irq %d (s3c uart2 irq)\n", irqno);
		irq_set_chip_and_handler(irqno, &s3c_irq_uart2,
					 handle_level_irq);
		set_irq_flags(irqno, IRQF_VALID);
	}

	for (irqno = IRQ_TC; irqno <= IRQ_ADC; irqno++) {
		irqdbf("registering irq %d (s3c adc irq)\n", irqno);
		irq_set_chip_and_handler(irqno, &s3c_irq_adc, handle_edge_irq);
		set_irq_flags(irqno, IRQF_VALID);
	}

	irqdbf("s3c2410: registered interrupt handlers\n");
}

struct syscore_ops s3c24xx_irq_syscore_ops = {
	.suspend	= s3c24xx_irq_suspend,
	.resume		= s3c24xx_irq_resume,
};
Commit	Line	Data
a21765a7 BD	1	/* linux/arch/arm/plat-s3c24xx/irq.c
a21765a7 BD	2	*
e02f8664	3	* Copyright (c) 2003-2004 Simtec Electronics
a21765a7 BD	4	* Ben Dooks <ben@simtec.co.uk>
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License, or
	9	* (at your option) any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program; if not, write to the Free Software
	18	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
a21765a7 BD	19	*/
	20
	21	#include <linux/init.h>
	22	#include <linux/module.h>
	23	#include <linux/interrupt.h>
	24	#include <linux/ioport.h>
edbaa603	25	#include <linux/device.h>
de11c585	26	#include <linux/syscore_ops.h>
a21765a7	27
a21765a7	28	#include <asm/irq.h>
a21765a7 BD	29	#include <asm/mach/irq.h>
a21765a7 BD	30
6af0e929	31	#include <plat/regs-irqtype.h>
a21765a7	32
a2b7ba9c BD	33	#include <plat/cpu.h>
	34	#include <plat/pm.h>
	35	#include <plat/irq.h>
a21765a7	36
a21765a7	37	static void
57436c2d	38	s3c_irq_mask(struct irq_data *data)
a21765a7	39	{
57436c2d	40	unsigned int irqno = data->irq - IRQ_EINT0;
a21765a7 BD	41	unsigned long mask;
a21765a7 BD	42
a21765a7 BD	43	mask = __raw_readl(S3C2410_INTMSK);
	44	mask \|= 1UL << irqno;
	45	__raw_writel(mask, S3C2410_INTMSK);
	46	}
	47
	48	static inline void
57436c2d	49	s3c_irq_ack(struct irq_data *data)
a21765a7	50	{
57436c2d	51	unsigned long bitval = 1UL << (data->irq - IRQ_EINT0);
a21765a7 BD	52
	53	__raw_writel(bitval, S3C2410_SRCPND);
	54	__raw_writel(bitval, S3C2410_INTPND);
	55	}
	56
	57	static inline void
57436c2d	58	s3c_irq_maskack(struct irq_data *data)
a21765a7	59	{
57436c2d	60	unsigned long bitval = 1UL << (data->irq - IRQ_EINT0);
a21765a7 BD	61	unsigned long mask;
	62
	63	mask = __raw_readl(S3C2410_INTMSK);
	64	__raw_writel(mask\|bitval, S3C2410_INTMSK);
	65
	66	__raw_writel(bitval, S3C2410_SRCPND);
	67	__raw_writel(bitval, S3C2410_INTPND);
	68	}
	69
	70
	71	static void
57436c2d	72	s3c_irq_unmask(struct irq_data *data)
a21765a7	73	{
57436c2d	74	unsigned int irqno = data->irq;
a21765a7 BD	75	unsigned long mask;
	76
	77	if (irqno != IRQ_TIMER4 && irqno != IRQ_EINT8t23)
	78	irqdbf2("s3c_irq_unmask %d\n", irqno);
	79
	80	irqno -= IRQ_EINT0;
	81
	82	mask = __raw_readl(S3C2410_INTMSK);
	83	mask &= ~(1UL << irqno);
	84	__raw_writel(mask, S3C2410_INTMSK);
	85	}
	86
	87	struct irq_chip s3c_irq_level_chip = {
	88	.name = "s3c-level",
57436c2d LB	89	.irq_ack = s3c_irq_maskack,
	90	.irq_mask = s3c_irq_mask,
	91	.irq_unmask = s3c_irq_unmask,
	92	.irq_set_wake = s3c_irq_wake
a21765a7 BD	93	};
a21765a7 BD	94
0baada27	95	struct irq_chip s3c_irq_chip = {
a21765a7	96	.name = "s3c",
57436c2d LB	97	.irq_ack = s3c_irq_ack,
	98	.irq_mask = s3c_irq_mask,
	99	.irq_unmask = s3c_irq_unmask,
	100	.irq_set_wake = s3c_irq_wake
a21765a7 BD	101	};
	102
	103	static void
57436c2d	104	s3c_irqext_mask(struct irq_data *data)
a21765a7	105	{
57436c2d	106	unsigned int irqno = data->irq - EXTINT_OFF;
a21765a7 BD	107	unsigned long mask;
a21765a7 BD	108
a21765a7 BD	109	mask = __raw_readl(S3C24XX_EINTMASK);
	110	mask \|= ( 1UL << irqno);
	111	__raw_writel(mask, S3C24XX_EINTMASK);
	112	}
	113
	114	static void
57436c2d	115	s3c_irqext_ack(struct irq_data *data)
a21765a7 BD	116	{
	117	unsigned long req;
	118	unsigned long bit;
	119	unsigned long mask;
	120
57436c2d	121	bit = 1UL << (data->irq - EXTINT_OFF);
a21765a7 BD	122
	123	mask = __raw_readl(S3C24XX_EINTMASK);
	124
	125	__raw_writel(bit, S3C24XX_EINTPEND);
	126
	127	req = __raw_readl(S3C24XX_EINTPEND);
	128	req &= ~mask;
	129
	130	/* not sure if we should be acking the parent irq... */
	131
57436c2d	132	if (data->irq <= IRQ_EINT7) {
a21765a7	133	if ((req & 0xf0) == 0)
57436c2d	134	s3c_irq_ack(irq_get_irq_data(IRQ_EINT4t7));
a21765a7 BD	135	} else {
a21765a7 BD	136	if ((req >> 8) == 0)
57436c2d	137	s3c_irq_ack(irq_get_irq_data(IRQ_EINT8t23));
a21765a7 BD	138	}
	139	}
	140
	141	static void
57436c2d	142	s3c_irqext_unmask(struct irq_data *data)
a21765a7	143	{
57436c2d	144	unsigned int irqno = data->irq - EXTINT_OFF;
a21765a7 BD	145	unsigned long mask;
a21765a7 BD	146
a21765a7	147	mask = __raw_readl(S3C24XX_EINTMASK);
57436c2d	148	mask &= ~(1UL << irqno);
a21765a7 BD	149	__raw_writel(mask, S3C24XX_EINTMASK);
	150	}
	151
	152	int
57436c2d	153	s3c_irqext_type(struct irq_data *data, unsigned int type)
a21765a7 BD	154	{
	155	void __iomem *extint_reg;
	156	void __iomem *gpcon_reg;
	157	unsigned long gpcon_offset, extint_offset;
	158	unsigned long newvalue = 0, value;
	159
57436c2d	160	if ((data->irq >= IRQ_EINT0) && (data->irq <= IRQ_EINT3)) {
a21765a7 BD	161	gpcon_reg = S3C2410_GPFCON;
a21765a7 BD	162	extint_reg = S3C24XX_EXTINT0;
57436c2d LB	163	gpcon_offset = (data->irq - IRQ_EINT0) * 2;
	164	extint_offset = (data->irq - IRQ_EINT0) * 4;
	165	} else if ((data->irq >= IRQ_EINT4) && (data->irq <= IRQ_EINT7)) {
a21765a7 BD	166	gpcon_reg = S3C2410_GPFCON;
a21765a7 BD	167	extint_reg = S3C24XX_EXTINT0;
57436c2d LB	168	gpcon_offset = (data->irq - (EXTINT_OFF)) * 2;
	169	extint_offset = (data->irq - (EXTINT_OFF)) * 4;
	170	} else if ((data->irq >= IRQ_EINT8) && (data->irq <= IRQ_EINT15)) {
a21765a7 BD	171	gpcon_reg = S3C2410_GPGCON;
a21765a7 BD	172	extint_reg = S3C24XX_EXTINT1;
57436c2d LB	173	gpcon_offset = (data->irq - IRQ_EINT8) * 2;
	174	extint_offset = (data->irq - IRQ_EINT8) * 4;
	175	} else if ((data->irq >= IRQ_EINT16) && (data->irq <= IRQ_EINT23)) {
a21765a7 BD	176	gpcon_reg = S3C2410_GPGCON;
a21765a7 BD	177	extint_reg = S3C24XX_EXTINT2;
57436c2d LB	178	gpcon_offset = (data->irq - IRQ_EINT8) * 2;
	179	extint_offset = (data->irq - IRQ_EINT16) * 4;
	180	} else {
a21765a7	181	return -1;
57436c2d	182	}
a21765a7 BD	183
	184	/* Set the GPIO to external interrupt mode */
	185	value = __raw_readl(gpcon_reg);
	186	value = (value & ~(3 << gpcon_offset)) \| (0x02 << gpcon_offset);
	187	__raw_writel(value, gpcon_reg);
	188
	189	/* Set the external interrupt to pointed trigger type */
	190	switch (type)
	191	{
6cab4860	192	case IRQ_TYPE_NONE:
a21765a7 BD	193	printk(KERN_WARNING "No edge setting!\n");
	194	break;
	195
6cab4860	196	case IRQ_TYPE_EDGE_RISING:
a21765a7 BD	197	newvalue = S3C2410_EXTINT_RISEEDGE;
	198	break;
	199
6cab4860	200	case IRQ_TYPE_EDGE_FALLING:
a21765a7 BD	201	newvalue = S3C2410_EXTINT_FALLEDGE;
	202	break;
	203
6cab4860	204	case IRQ_TYPE_EDGE_BOTH:
a21765a7 BD	205	newvalue = S3C2410_EXTINT_BOTHEDGE;
	206	break;
	207
6cab4860	208	case IRQ_TYPE_LEVEL_LOW:
a21765a7 BD	209	newvalue = S3C2410_EXTINT_LOWLEV;
	210	break;
	211
6cab4860	212	case IRQ_TYPE_LEVEL_HIGH:
a21765a7 BD	213	newvalue = S3C2410_EXTINT_HILEV;
	214	break;
	215
	216	default:
	217	printk(KERN_ERR "No such irq type %d", type);
	218	return -1;
	219	}
	220
	221	value = __raw_readl(extint_reg);
	222	value = (value & ~(7 << extint_offset)) \| (newvalue << extint_offset);
	223	__raw_writel(value, extint_reg);
	224
	225	return 0;
	226	}
	227
	228	static struct irq_chip s3c_irqext_chip = {
	229	.name = "s3c-ext",
57436c2d LB	230	.irq_mask = s3c_irqext_mask,
	231	.irq_unmask = s3c_irqext_unmask,
	232	.irq_ack = s3c_irqext_ack,
	233	.irq_set_type = s3c_irqext_type,
f5aeffb7	234	.irq_set_wake = s3c_irqext_wake
a21765a7 BD	235	};
	236
	237	static struct irq_chip s3c_irq_eint0t4 = {
	238	.name = "s3c-ext0",
57436c2d LB	239	.irq_ack = s3c_irq_ack,
	240	.irq_mask = s3c_irq_mask,
	241	.irq_unmask = s3c_irq_unmask,
	242	.irq_set_wake = s3c_irq_wake,
	243	.irq_set_type = s3c_irqext_type,
a21765a7 BD	244	};
	245
	246	/* mask values for the parent registers for each of the interrupt types */
	247
	248	#define INTMSK_UART0 (1UL << (IRQ_UART0 - IRQ_EINT0))
	249	#define INTMSK_UART1 (1UL << (IRQ_UART1 - IRQ_EINT0))
	250	#define INTMSK_UART2 (1UL << (IRQ_UART2 - IRQ_EINT0))
	251	#define INTMSK_ADCPARENT (1UL << (IRQ_ADCPARENT - IRQ_EINT0))
	252
	253
	254	/* UART0 */
	255
	256	static void
57436c2d	257	s3c_irq_uart0_mask(struct irq_data *data)
a21765a7	258	{
57436c2d	259	s3c_irqsub_mask(data->irq, INTMSK_UART0, 7);
a21765a7 BD	260	}
	261
	262	static void
57436c2d	263	s3c_irq_uart0_unmask(struct irq_data *data)
a21765a7	264	{
57436c2d	265	s3c_irqsub_unmask(data->irq, INTMSK_UART0);
a21765a7 BD	266	}
	267
	268	static void
57436c2d	269	s3c_irq_uart0_ack(struct irq_data *data)
a21765a7	270	{
57436c2d	271	s3c_irqsub_maskack(data->irq, INTMSK_UART0, 7);
a21765a7 BD	272	}
	273
	274	static struct irq_chip s3c_irq_uart0 = {
	275	.name = "s3c-uart0",
57436c2d LB	276	.irq_mask = s3c_irq_uart0_mask,
	277	.irq_unmask = s3c_irq_uart0_unmask,
	278	.irq_ack = s3c_irq_uart0_ack,
a21765a7 BD	279	};
	280
	281	/* UART1 */
	282
	283	static void
57436c2d	284	s3c_irq_uart1_mask(struct irq_data *data)
a21765a7	285	{
57436c2d	286	s3c_irqsub_mask(data->irq, INTMSK_UART1, 7 << 3);
a21765a7 BD	287	}
	288
	289	static void
57436c2d	290	s3c_irq_uart1_unmask(struct irq_data *data)
a21765a7	291	{
57436c2d	292	s3c_irqsub_unmask(data->irq, INTMSK_UART1);
a21765a7 BD	293	}
	294
	295	static void
57436c2d	296	s3c_irq_uart1_ack(struct irq_data *data)
a21765a7	297	{
57436c2d	298	s3c_irqsub_maskack(data->irq, INTMSK_UART1, 7 << 3);
a21765a7 BD	299	}
	300
	301	static struct irq_chip s3c_irq_uart1 = {
	302	.name = "s3c-uart1",
57436c2d LB	303	.irq_mask = s3c_irq_uart1_mask,
	304	.irq_unmask = s3c_irq_uart1_unmask,
	305	.irq_ack = s3c_irq_uart1_ack,
a21765a7 BD	306	};
	307
	308	/* UART2 */
	309
	310	static void
57436c2d	311	s3c_irq_uart2_mask(struct irq_data *data)
a21765a7	312	{
57436c2d	313	s3c_irqsub_mask(data->irq, INTMSK_UART2, 7 << 6);
a21765a7 BD	314	}
	315
	316	static void
57436c2d	317	s3c_irq_uart2_unmask(struct irq_data *data)
a21765a7	318	{
57436c2d	319	s3c_irqsub_unmask(data->irq, INTMSK_UART2);
a21765a7 BD	320	}
	321
	322	static void
57436c2d	323	s3c_irq_uart2_ack(struct irq_data *data)
a21765a7	324	{
57436c2d	325	s3c_irqsub_maskack(data->irq, INTMSK_UART2, 7 << 6);
a21765a7 BD	326	}
	327
	328	static struct irq_chip s3c_irq_uart2 = {
	329	.name = "s3c-uart2",
57436c2d LB	330	.irq_mask = s3c_irq_uart2_mask,
	331	.irq_unmask = s3c_irq_uart2_unmask,
	332	.irq_ack = s3c_irq_uart2_ack,
a21765a7 BD	333	};
	334
	335	/* ADC and Touchscreen */
	336
	337	static void
57436c2d	338	s3c_irq_adc_mask(struct irq_data *d)
a21765a7	339	{
57436c2d	340	s3c_irqsub_mask(d->irq, INTMSK_ADCPARENT, 3 << 9);
a21765a7 BD	341	}
	342
	343	static void
57436c2d	344	s3c_irq_adc_unmask(struct irq_data *d)
a21765a7	345	{
57436c2d	346	s3c_irqsub_unmask(d->irq, INTMSK_ADCPARENT);
a21765a7 BD	347	}
	348
	349	static void
57436c2d	350	s3c_irq_adc_ack(struct irq_data *d)
a21765a7	351	{
57436c2d	352	s3c_irqsub_ack(d->irq, INTMSK_ADCPARENT, 3 << 9);
a21765a7 BD	353	}
	354
	355	static struct irq_chip s3c_irq_adc = {
	356	.name = "s3c-adc",
57436c2d LB	357	.irq_mask = s3c_irq_adc_mask,
	358	.irq_unmask = s3c_irq_adc_unmask,
	359	.irq_ack = s3c_irq_adc_ack,
a21765a7 BD	360	};
	361
	362	/* irq demux for adc */
	363	static void s3c_irq_demux_adc(unsigned int irq,
	364	struct irq_desc *desc)
	365	{
	366	unsigned int subsrc, submsk;
	367	unsigned int offset = 9;
a21765a7 BD	368
	369	/* read the current pending interrupts, and the mask
	370	* for what it is available */
	371
	372	subsrc = __raw_readl(S3C2410_SUBSRCPND);
	373	submsk = __raw_readl(S3C2410_INTSUBMSK);
	374
	375	subsrc &= ~submsk;
	376	subsrc >>= offset;
	377	subsrc &= 3;
	378
	379	if (subsrc != 0) {
	380	if (subsrc & 1) {
d8aa0251	381	generic_handle_irq(IRQ_TC);
a21765a7 BD	382	}
a21765a7 BD	383	if (subsrc & 2) {
d8aa0251	384	generic_handle_irq(IRQ_ADC);
a21765a7 BD	385	}
	386	}
	387	}
	388
	389	static void s3c_irq_demux_uart(unsigned int start)
	390	{
	391	unsigned int subsrc, submsk;
	392	unsigned int offset = start - IRQ_S3CUART_RX0;
a21765a7 BD	393
	394	/* read the current pending interrupts, and the mask
	395	* for what it is available */
	396
	397	subsrc = __raw_readl(S3C2410_SUBSRCPND);
	398	submsk = __raw_readl(S3C2410_INTSUBMSK);
	399
	400	irqdbf2("s3c_irq_demux_uart: start=%d (%d), subsrc=0x%08x,0x%08x\n",
	401	start, offset, subsrc, submsk);
	402
	403	subsrc &= ~submsk;
	404	subsrc >>= offset;
	405	subsrc &= 7;
	406
	407	if (subsrc != 0) {
a21765a7	408	if (subsrc & 1)
d8aa0251	409	generic_handle_irq(start);
a21765a7 BD	410
a21765a7 BD	411	if (subsrc & 2)
d8aa0251	412	generic_handle_irq(start+1);
a21765a7 BD	413
a21765a7 BD	414	if (subsrc & 4)
d8aa0251	415	generic_handle_irq(start+2);
a21765a7 BD	416	}
	417	}
	418
	419	/* uart demux entry points */
	420
	421	static void
	422	s3c_irq_demux_uart0(unsigned int irq,
	423	struct irq_desc *desc)
	424	{
	425	irq = irq;
	426	s3c_irq_demux_uart(IRQ_S3CUART_RX0);
	427	}
	428
	429	static void
	430	s3c_irq_demux_uart1(unsigned int irq,
	431	struct irq_desc *desc)
	432	{
	433	irq = irq;
	434	s3c_irq_demux_uart(IRQ_S3CUART_RX1);
	435	}
	436
	437	static void
	438	s3c_irq_demux_uart2(unsigned int irq,
	439	struct irq_desc *desc)
	440	{
	441	irq = irq;
	442	s3c_irq_demux_uart(IRQ_S3CUART_RX2);
	443	}
	444
	445	static void
	446	s3c_irq_demux_extint8(unsigned int irq,
	447	struct irq_desc *desc)
	448	{
	449	unsigned long eintpnd = __raw_readl(S3C24XX_EINTPEND);
	450	unsigned long eintmsk = __raw_readl(S3C24XX_EINTMASK);
	451
	452	eintpnd &= ~eintmsk;
	453	eintpnd &= ~0xff; /* ignore lower irqs */
	454
	455	/* we may as well handle all the pending IRQs here */
	456
	457	while (eintpnd) {
	458	irq = __ffs(eintpnd);
	459	eintpnd &= ~(1<<irq);
	460
	461	irq += (IRQ_EINT4 - 4);
d8aa0251	462	generic_handle_irq(irq);
a21765a7 BD	463	}
	464
	465	}
	466
	467	static void
	468	s3c_irq_demux_extint4t7(unsigned int irq,
	469	struct irq_desc *desc)
	470	{
	471	unsigned long eintpnd = __raw_readl(S3C24XX_EINTPEND);
	472	unsigned long eintmsk = __raw_readl(S3C24XX_EINTMASK);
	473
	474	eintpnd &= ~eintmsk;
	475	eintpnd &= 0xff; /* only lower irqs */
	476
	477	/* we may as well handle all the pending IRQs here */
	478
	479	while (eintpnd) {
	480	irq = __ffs(eintpnd);
	481	eintpnd &= ~(1<<irq);
	482
	483	irq += (IRQ_EINT4 - 4);
	484
d8aa0251	485	generic_handle_irq(irq);
a21765a7 BD	486	}
	487	}
	488
229fd8ff BD	489	#ifdef CONFIG_FIQ
	490	/**
	491	* s3c24xx_set_fiq - set the FIQ routing
	492	* @irq: IRQ number to route to FIQ on processor.
	493	* @on: Whether to route @irq to the FIQ, or to remove the FIQ routing.
	494	*
	495	* Change the state of the IRQ to FIQ routing depending on @irq and @on. If
	496	* @on is true, the @irq is checked to see if it can be routed and the
	497	* interrupt controller updated to route the IRQ. If @on is false, the FIQ
	498	* routing is cleared, regardless of which @irq is specified.
	499	*/
	500	int s3c24xx_set_fiq(unsigned int irq, bool on)
	501	{
	502	u32 intmod;
	503	unsigned offs;
	504
	505	if (on) {
	506	offs = irq - FIQ_START;
	507	if (offs > 31)
	508	return -EINVAL;
	509
	510	intmod = 1 << offs;
	511	} else {
	512	intmod = 0;
	513	}
	514
	515	__raw_writel(intmod, S3C2410_INTMOD);
	516	return 0;
	517	}
0f13c824 BD	518
0f13c824 BD	519	EXPORT_SYMBOL_GPL(s3c24xx_set_fiq);
229fd8ff BD	520	#endif
	521
	522
a21765a7 BD	523	/* s3c24xx_init_irq
	524	*
	525	* Initialise S3C2410 IRQ system
	526	*/
	527
	528	void __init s3c24xx_init_irq(void)
	529	{
	530	unsigned long pend;
	531	unsigned long last;
	532	int irqno;
	533	int i;
	534
229fd8ff	535	#ifdef CONFIG_FIQ
bc89663a	536	init_FIQ(FIQ_START);
229fd8ff BD	537	#endif
229fd8ff BD	538
a21765a7 BD	539	irqdbf("s3c2410_init_irq: clearing interrupt status flags\n");
	540
	541	/* first, clear all interrupts pending... */
	542
	543	last = 0;
	544	for (i = 0; i < 4; i++) {
	545	pend = __raw_readl(S3C24XX_EINTPEND);
	546
	547	if (pend == 0 \|\| pend == last)
	548	break;
	549
	550	__raw_writel(pend, S3C24XX_EINTPEND);
	551	printk("irq: clearing pending ext status %08x\n", (int)pend);
	552	last = pend;
	553	}
	554
	555	last = 0;
	556	for (i = 0; i < 4; i++) {
	557	pend = __raw_readl(S3C2410_INTPND);
	558
	559	if (pend == 0 \|\| pend == last)
	560	break;
	561
	562	__raw_writel(pend, S3C2410_SRCPND);
	563	__raw_writel(pend, S3C2410_INTPND);
	564	printk("irq: clearing pending status %08x\n", (int)pend);
	565	last = pend;
	566	}
	567
	568	last = 0;
	569	for (i = 0; i < 4; i++) {
	570	pend = __raw_readl(S3C2410_SUBSRCPND);
	571
	572	if (pend == 0 \|\| pend == last)
	573	break;
	574
	575	printk("irq: clearing subpending status %08x\n", (int)pend);
	576	__raw_writel(pend, S3C2410_SUBSRCPND);
	577	last = pend;
	578	}
	579
	580	/* register the main interrupts */
	581
	582	irqdbf("s3c2410_init_irq: registering s3c2410 interrupt handlers\n");
	583
	584	for (irqno = IRQ_EINT4t7; irqno <= IRQ_ADCPARENT; irqno++) {
	585	/* set all the s3c2410 internal irqs */
	586
	587	switch (irqno) {
	588	/* deal with the special IRQs (cascaded) */
	589
	590	case IRQ_EINT4t7:
	591	case IRQ_EINT8t23:
	592	case IRQ_UART0:
	593	case IRQ_UART1:
	594	case IRQ_UART2:
	595	case IRQ_ADCPARENT:
f38c02f3 TG	596	irq_set_chip_and_handler(irqno, &s3c_irq_level_chip,
f38c02f3 TG	597	handle_level_irq);
a21765a7 BD	598	break;
	599
	600	case IRQ_RESERVED6:
	601	case IRQ_RESERVED24:
	602	/* no IRQ here */
	603	break;
	604
	605	default:
	606	//irqdbf("registering irq %d (s3c irq)\n", irqno);
f38c02f3 TG	607	irq_set_chip_and_handler(irqno, &s3c_irq_chip,
f38c02f3 TG	608	handle_edge_irq);
a21765a7 BD	609	set_irq_flags(irqno, IRQF_VALID);
	610	}
	611	}
	612
	613	/* setup the cascade irq handlers */
	614
6845664a TG	615	irq_set_chained_handler(IRQ_EINT4t7, s3c_irq_demux_extint4t7);
6845664a TG	616	irq_set_chained_handler(IRQ_EINT8t23, s3c_irq_demux_extint8);
a21765a7	617
6845664a TG	618	irq_set_chained_handler(IRQ_UART0, s3c_irq_demux_uart0);
	619	irq_set_chained_handler(IRQ_UART1, s3c_irq_demux_uart1);
	620	irq_set_chained_handler(IRQ_UART2, s3c_irq_demux_uart2);
	621	irq_set_chained_handler(IRQ_ADCPARENT, s3c_irq_demux_adc);
a21765a7 BD	622
	623	/* external interrupts */
	624
	625	for (irqno = IRQ_EINT0; irqno <= IRQ_EINT3; irqno++) {
	626	irqdbf("registering irq %d (ext int)\n", irqno);
f38c02f3 TG	627	irq_set_chip_and_handler(irqno, &s3c_irq_eint0t4,
f38c02f3 TG	628	handle_edge_irq);
a21765a7 BD	629	set_irq_flags(irqno, IRQF_VALID);
	630	}
	631
	632	for (irqno = IRQ_EINT4; irqno <= IRQ_EINT23; irqno++) {
	633	irqdbf("registering irq %d (extended s3c irq)\n", irqno);
f38c02f3 TG	634	irq_set_chip_and_handler(irqno, &s3c_irqext_chip,
f38c02f3 TG	635	handle_edge_irq);
a21765a7 BD	636	set_irq_flags(irqno, IRQF_VALID);
	637	}
	638
	639	/* register the uart interrupts */
	640
	641	irqdbf("s3c2410: registering external interrupts\n");
	642
	643	for (irqno = IRQ_S3CUART_RX0; irqno <= IRQ_S3CUART_ERR0; irqno++) {
	644	irqdbf("registering irq %d (s3c uart0 irq)\n", irqno);
f38c02f3 TG	645	irq_set_chip_and_handler(irqno, &s3c_irq_uart0,
f38c02f3 TG	646	handle_level_irq);
a21765a7 BD	647	set_irq_flags(irqno, IRQF_VALID);
	648	}
	649
	650	for (irqno = IRQ_S3CUART_RX1; irqno <= IRQ_S3CUART_ERR1; irqno++) {
	651	irqdbf("registering irq %d (s3c uart1 irq)\n", irqno);
f38c02f3 TG	652	irq_set_chip_and_handler(irqno, &s3c_irq_uart1,
f38c02f3 TG	653	handle_level_irq);
a21765a7 BD	654	set_irq_flags(irqno, IRQF_VALID);
	655	}
	656
	657	for (irqno = IRQ_S3CUART_RX2; irqno <= IRQ_S3CUART_ERR2; irqno++) {
	658	irqdbf("registering irq %d (s3c uart2 irq)\n", irqno);
f38c02f3 TG	659	irq_set_chip_and_handler(irqno, &s3c_irq_uart2,
f38c02f3 TG	660	handle_level_irq);
a21765a7 BD	661	set_irq_flags(irqno, IRQF_VALID);
	662	}
	663
	664	for (irqno = IRQ_TC; irqno <= IRQ_ADC; irqno++) {
	665	irqdbf("registering irq %d (s3c adc irq)\n", irqno);
f38c02f3	666	irq_set_chip_and_handler(irqno, &s3c_irq_adc, handle_edge_irq);
a21765a7 BD	667	set_irq_flags(irqno, IRQF_VALID);
	668	}
	669
	670	irqdbf("s3c2410: registered interrupt handlers\n");
	671	}
de11c585 HS	672
	673	struct syscore_ops s3c24xx_irq_syscore_ops = {
	674	.suspend = s3c24xx_irq_suspend,
	675	.resume = s3c24xx_irq_resume,
	676	};