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a21765a7 BD |
1 | /* linux/arch/arm/plat-s3c24xx/dma.c |
2 | * | |
3 | * Copyright (c) 2003-2005,2006 Simtec Electronics | |
4 | * Ben Dooks <ben@simtec.co.uk> | |
5 | * | |
6 | * S3C2410 DMA core | |
7 | * | |
8 | * http://armlinux.simtec.co.uk/ | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License version 2 as | |
12 | * published by the Free Software Foundation. | |
13 | */ | |
14 | ||
15 | ||
16 | #ifdef CONFIG_S3C2410_DMA_DEBUG | |
17 | #define DEBUG | |
18 | #endif | |
19 | ||
20 | #include <linux/module.h> | |
21 | #include <linux/init.h> | |
22 | #include <linux/sched.h> | |
23 | #include <linux/spinlock.h> | |
24 | #include <linux/interrupt.h> | |
25 | #include <linux/sysdev.h> | |
26 | #include <linux/slab.h> | |
27 | #include <linux/errno.h> | |
28 | #include <linux/delay.h> | |
29 | ||
30 | #include <asm/system.h> | |
31 | #include <asm/irq.h> | |
32 | #include <asm/hardware.h> | |
33 | #include <asm/io.h> | |
34 | #include <asm/dma.h> | |
35 | ||
36 | #include <asm/mach/dma.h> | |
37 | #include <asm/arch/map.h> | |
38 | ||
39 | #include <asm/plat-s3c24xx/dma.h> | |
40 | ||
41 | /* io map for dma */ | |
42 | static void __iomem *dma_base; | |
43 | static struct kmem_cache *dma_kmem; | |
44 | ||
48adbcf3 BD |
45 | static int dma_channels; |
46 | ||
a7717435 | 47 | static struct s3c24xx_dma_selection dma_sel; |
a21765a7 BD |
48 | |
49 | /* dma channel state information */ | |
50 | struct s3c2410_dma_chan s3c2410_chans[S3C2410_DMA_CHANNELS]; | |
51 | ||
52 | /* debugging functions */ | |
53 | ||
54 | #define BUF_MAGIC (0xcafebabe) | |
55 | ||
56 | #define dmawarn(fmt...) printk(KERN_DEBUG fmt) | |
57 | ||
58 | #define dma_regaddr(chan, reg) ((chan)->regs + (reg)) | |
59 | ||
60 | #if 1 | |
61 | #define dma_wrreg(chan, reg, val) writel((val), (chan)->regs + (reg)) | |
62 | #else | |
63 | static inline void | |
64 | dma_wrreg(struct s3c2410_dma_chan *chan, int reg, unsigned long val) | |
65 | { | |
66 | pr_debug("writing %08x to register %08x\n",(unsigned int)val,reg); | |
67 | writel(val, dma_regaddr(chan, reg)); | |
68 | } | |
69 | #endif | |
70 | ||
71 | #define dma_rdreg(chan, reg) readl((chan)->regs + (reg)) | |
72 | ||
73 | /* captured register state for debug */ | |
74 | ||
75 | struct s3c2410_dma_regstate { | |
76 | unsigned long dcsrc; | |
77 | unsigned long disrc; | |
78 | unsigned long dstat; | |
79 | unsigned long dcon; | |
80 | unsigned long dmsktrig; | |
81 | }; | |
82 | ||
83 | #ifdef CONFIG_S3C2410_DMA_DEBUG | |
84 | ||
85 | /* dmadbg_showregs | |
86 | * | |
87 | * simple debug routine to print the current state of the dma registers | |
88 | */ | |
89 | ||
90 | static void | |
91 | dmadbg_capture(struct s3c2410_dma_chan *chan, struct s3c2410_dma_regstate *regs) | |
92 | { | |
93 | regs->dcsrc = dma_rdreg(chan, S3C2410_DMA_DCSRC); | |
94 | regs->disrc = dma_rdreg(chan, S3C2410_DMA_DISRC); | |
95 | regs->dstat = dma_rdreg(chan, S3C2410_DMA_DSTAT); | |
96 | regs->dcon = dma_rdreg(chan, S3C2410_DMA_DCON); | |
97 | regs->dmsktrig = dma_rdreg(chan, S3C2410_DMA_DMASKTRIG); | |
98 | } | |
99 | ||
100 | static void | |
101 | dmadbg_dumpregs(const char *fname, int line, struct s3c2410_dma_chan *chan, | |
102 | struct s3c2410_dma_regstate *regs) | |
103 | { | |
104 | printk(KERN_DEBUG "dma%d: %s:%d: DCSRC=%08lx, DISRC=%08lx, DSTAT=%08lx DMT=%02lx, DCON=%08lx\n", | |
105 | chan->number, fname, line, | |
106 | regs->dcsrc, regs->disrc, regs->dstat, regs->dmsktrig, | |
107 | regs->dcon); | |
108 | } | |
109 | ||
110 | static void | |
111 | dmadbg_showchan(const char *fname, int line, struct s3c2410_dma_chan *chan) | |
112 | { | |
113 | struct s3c2410_dma_regstate state; | |
114 | ||
115 | dmadbg_capture(chan, &state); | |
116 | ||
117 | printk(KERN_DEBUG "dma%d: %s:%d: ls=%d, cur=%p, %p %p\n", | |
118 | chan->number, fname, line, chan->load_state, | |
119 | chan->curr, chan->next, chan->end); | |
120 | ||
121 | dmadbg_dumpregs(fname, line, chan, &state); | |
122 | } | |
123 | ||
124 | static void | |
125 | dmadbg_showregs(const char *fname, int line, struct s3c2410_dma_chan *chan) | |
126 | { | |
127 | struct s3c2410_dma_regstate state; | |
128 | ||
129 | dmadbg_capture(chan, &state); | |
130 | dmadbg_dumpregs(fname, line, chan, &state); | |
131 | } | |
132 | ||
133 | #define dbg_showregs(chan) dmadbg_showregs(__FUNCTION__, __LINE__, (chan)) | |
134 | #define dbg_showchan(chan) dmadbg_showchan(__FUNCTION__, __LINE__, (chan)) | |
135 | #else | |
136 | #define dbg_showregs(chan) do { } while(0) | |
137 | #define dbg_showchan(chan) do { } while(0) | |
138 | #endif /* CONFIG_S3C2410_DMA_DEBUG */ | |
139 | ||
140 | static struct s3c2410_dma_chan *dma_chan_map[DMACH_MAX]; | |
141 | ||
142 | /* lookup_dma_channel | |
143 | * | |
144 | * change the dma channel number given into a real dma channel id | |
145 | */ | |
146 | ||
147 | static struct s3c2410_dma_chan *lookup_dma_channel(unsigned int channel) | |
148 | { | |
149 | if (channel & DMACH_LOW_LEVEL) | |
150 | return &s3c2410_chans[channel & ~DMACH_LOW_LEVEL]; | |
151 | else | |
152 | return dma_chan_map[channel]; | |
153 | } | |
154 | ||
155 | /* s3c2410_dma_stats_timeout | |
156 | * | |
157 | * Update DMA stats from timeout info | |
158 | */ | |
159 | ||
160 | static void | |
161 | s3c2410_dma_stats_timeout(struct s3c2410_dma_stats *stats, int val) | |
162 | { | |
163 | if (stats == NULL) | |
164 | return; | |
165 | ||
166 | if (val > stats->timeout_longest) | |
167 | stats->timeout_longest = val; | |
168 | if (val < stats->timeout_shortest) | |
169 | stats->timeout_shortest = val; | |
170 | ||
171 | stats->timeout_avg += val; | |
172 | } | |
173 | ||
174 | /* s3c2410_dma_waitforload | |
175 | * | |
176 | * wait for the DMA engine to load a buffer, and update the state accordingly | |
177 | */ | |
178 | ||
179 | static int | |
180 | s3c2410_dma_waitforload(struct s3c2410_dma_chan *chan, int line) | |
181 | { | |
182 | int timeout = chan->load_timeout; | |
183 | int took; | |
184 | ||
185 | if (chan->load_state != S3C2410_DMALOAD_1LOADED) { | |
186 | printk(KERN_ERR "dma%d: s3c2410_dma_waitforload() called in loadstate %d from line %d\n", chan->number, chan->load_state, line); | |
187 | return 0; | |
188 | } | |
189 | ||
190 | if (chan->stats != NULL) | |
191 | chan->stats->loads++; | |
192 | ||
193 | while (--timeout > 0) { | |
194 | if ((dma_rdreg(chan, S3C2410_DMA_DSTAT) << (32-20)) != 0) { | |
195 | took = chan->load_timeout - timeout; | |
196 | ||
197 | s3c2410_dma_stats_timeout(chan->stats, took); | |
198 | ||
199 | switch (chan->load_state) { | |
200 | case S3C2410_DMALOAD_1LOADED: | |
201 | chan->load_state = S3C2410_DMALOAD_1RUNNING; | |
202 | break; | |
203 | ||
204 | default: | |
205 | printk(KERN_ERR "dma%d: unknown load_state in s3c2410_dma_waitforload() %d\n", chan->number, chan->load_state); | |
206 | } | |
207 | ||
208 | return 1; | |
209 | } | |
210 | } | |
211 | ||
212 | if (chan->stats != NULL) { | |
213 | chan->stats->timeout_failed++; | |
214 | } | |
215 | ||
216 | return 0; | |
217 | } | |
218 | ||
219 | ||
220 | ||
221 | /* s3c2410_dma_loadbuffer | |
222 | * | |
223 | * load a buffer, and update the channel state | |
224 | */ | |
225 | ||
226 | static inline int | |
227 | s3c2410_dma_loadbuffer(struct s3c2410_dma_chan *chan, | |
228 | struct s3c2410_dma_buf *buf) | |
229 | { | |
230 | unsigned long reload; | |
231 | ||
232 | pr_debug("s3c2410_chan_loadbuffer: loading buff %p (0x%08lx,0x%06x)\n", | |
233 | buf, (unsigned long)buf->data, buf->size); | |
234 | ||
235 | if (buf == NULL) { | |
236 | dmawarn("buffer is NULL\n"); | |
237 | return -EINVAL; | |
238 | } | |
239 | ||
240 | /* check the state of the channel before we do anything */ | |
241 | ||
242 | if (chan->load_state == S3C2410_DMALOAD_1LOADED) { | |
243 | dmawarn("load_state is S3C2410_DMALOAD_1LOADED\n"); | |
244 | } | |
245 | ||
246 | if (chan->load_state == S3C2410_DMALOAD_1LOADED_1RUNNING) { | |
247 | dmawarn("state is S3C2410_DMALOAD_1LOADED_1RUNNING\n"); | |
248 | } | |
249 | ||
250 | /* it would seem sensible if we are the last buffer to not bother | |
251 | * with the auto-reload bit, so that the DMA engine will not try | |
252 | * and load another transfer after this one has finished... | |
253 | */ | |
254 | if (chan->load_state == S3C2410_DMALOAD_NONE) { | |
255 | pr_debug("load_state is none, checking for noreload (next=%p)\n", | |
256 | buf->next); | |
257 | reload = (buf->next == NULL) ? S3C2410_DCON_NORELOAD : 0; | |
258 | } else { | |
259 | //pr_debug("load_state is %d => autoreload\n", chan->load_state); | |
260 | reload = S3C2410_DCON_AUTORELOAD; | |
261 | } | |
262 | ||
263 | if ((buf->data & 0xf0000000) != 0x30000000) { | |
264 | dmawarn("dmaload: buffer is %p\n", (void *)buf->data); | |
265 | } | |
266 | ||
267 | writel(buf->data, chan->addr_reg); | |
268 | ||
269 | dma_wrreg(chan, S3C2410_DMA_DCON, | |
270 | chan->dcon | reload | (buf->size/chan->xfer_unit)); | |
271 | ||
272 | chan->next = buf->next; | |
273 | ||
274 | /* update the state of the channel */ | |
275 | ||
276 | switch (chan->load_state) { | |
277 | case S3C2410_DMALOAD_NONE: | |
278 | chan->load_state = S3C2410_DMALOAD_1LOADED; | |
279 | break; | |
280 | ||
281 | case S3C2410_DMALOAD_1RUNNING: | |
282 | chan->load_state = S3C2410_DMALOAD_1LOADED_1RUNNING; | |
283 | break; | |
284 | ||
285 | default: | |
286 | dmawarn("dmaload: unknown state %d in loadbuffer\n", | |
287 | chan->load_state); | |
288 | break; | |
289 | } | |
290 | ||
291 | return 0; | |
292 | } | |
293 | ||
294 | /* s3c2410_dma_call_op | |
295 | * | |
296 | * small routine to call the op routine with the given op if it has been | |
297 | * registered | |
298 | */ | |
299 | ||
300 | static void | |
301 | s3c2410_dma_call_op(struct s3c2410_dma_chan *chan, enum s3c2410_chan_op op) | |
302 | { | |
303 | if (chan->op_fn != NULL) { | |
304 | (chan->op_fn)(chan, op); | |
305 | } | |
306 | } | |
307 | ||
308 | /* s3c2410_dma_buffdone | |
309 | * | |
310 | * small wrapper to check if callback routine needs to be called, and | |
311 | * if so, call it | |
312 | */ | |
313 | ||
314 | static inline void | |
315 | s3c2410_dma_buffdone(struct s3c2410_dma_chan *chan, struct s3c2410_dma_buf *buf, | |
316 | enum s3c2410_dma_buffresult result) | |
317 | { | |
318 | #if 0 | |
319 | pr_debug("callback_fn=%p, buf=%p, id=%p, size=%d, result=%d\n", | |
320 | chan->callback_fn, buf, buf->id, buf->size, result); | |
321 | #endif | |
322 | ||
323 | if (chan->callback_fn != NULL) { | |
324 | (chan->callback_fn)(chan, buf->id, buf->size, result); | |
325 | } | |
326 | } | |
327 | ||
328 | /* s3c2410_dma_start | |
329 | * | |
330 | * start a dma channel going | |
331 | */ | |
332 | ||
333 | static int s3c2410_dma_start(struct s3c2410_dma_chan *chan) | |
334 | { | |
335 | unsigned long tmp; | |
336 | unsigned long flags; | |
337 | ||
338 | pr_debug("s3c2410_start_dma: channel=%d\n", chan->number); | |
339 | ||
340 | local_irq_save(flags); | |
341 | ||
342 | if (chan->state == S3C2410_DMA_RUNNING) { | |
343 | pr_debug("s3c2410_start_dma: already running (%d)\n", chan->state); | |
344 | local_irq_restore(flags); | |
345 | return 0; | |
346 | } | |
347 | ||
348 | chan->state = S3C2410_DMA_RUNNING; | |
349 | ||
350 | /* check wether there is anything to load, and if not, see | |
351 | * if we can find anything to load | |
352 | */ | |
353 | ||
354 | if (chan->load_state == S3C2410_DMALOAD_NONE) { | |
355 | if (chan->next == NULL) { | |
356 | printk(KERN_ERR "dma%d: channel has nothing loaded\n", | |
357 | chan->number); | |
358 | chan->state = S3C2410_DMA_IDLE; | |
359 | local_irq_restore(flags); | |
360 | return -EINVAL; | |
361 | } | |
362 | ||
363 | s3c2410_dma_loadbuffer(chan, chan->next); | |
364 | } | |
365 | ||
366 | dbg_showchan(chan); | |
367 | ||
368 | /* enable the channel */ | |
369 | ||
370 | if (!chan->irq_enabled) { | |
371 | enable_irq(chan->irq); | |
372 | chan->irq_enabled = 1; | |
373 | } | |
374 | ||
375 | /* start the channel going */ | |
376 | ||
377 | tmp = dma_rdreg(chan, S3C2410_DMA_DMASKTRIG); | |
378 | tmp &= ~S3C2410_DMASKTRIG_STOP; | |
379 | tmp |= S3C2410_DMASKTRIG_ON; | |
380 | dma_wrreg(chan, S3C2410_DMA_DMASKTRIG, tmp); | |
381 | ||
382 | pr_debug("dma%d: %08lx to DMASKTRIG\n", chan->number, tmp); | |
383 | ||
384 | #if 0 | |
385 | /* the dma buffer loads should take care of clearing the AUTO | |
386 | * reloading feature */ | |
387 | tmp = dma_rdreg(chan, S3C2410_DMA_DCON); | |
388 | tmp &= ~S3C2410_DCON_NORELOAD; | |
389 | dma_wrreg(chan, S3C2410_DMA_DCON, tmp); | |
390 | #endif | |
391 | ||
392 | s3c2410_dma_call_op(chan, S3C2410_DMAOP_START); | |
393 | ||
394 | dbg_showchan(chan); | |
395 | ||
396 | /* if we've only loaded one buffer onto the channel, then chec | |
397 | * to see if we have another, and if so, try and load it so when | |
398 | * the first buffer is finished, the new one will be loaded onto | |
399 | * the channel */ | |
400 | ||
401 | if (chan->next != NULL) { | |
402 | if (chan->load_state == S3C2410_DMALOAD_1LOADED) { | |
403 | ||
404 | if (s3c2410_dma_waitforload(chan, __LINE__) == 0) { | |
405 | pr_debug("%s: buff not yet loaded, no more todo\n", | |
406 | __FUNCTION__); | |
407 | } else { | |
408 | chan->load_state = S3C2410_DMALOAD_1RUNNING; | |
409 | s3c2410_dma_loadbuffer(chan, chan->next); | |
410 | } | |
411 | ||
412 | } else if (chan->load_state == S3C2410_DMALOAD_1RUNNING) { | |
413 | s3c2410_dma_loadbuffer(chan, chan->next); | |
414 | } | |
415 | } | |
416 | ||
417 | ||
418 | local_irq_restore(flags); | |
419 | ||
420 | return 0; | |
421 | } | |
422 | ||
423 | /* s3c2410_dma_canload | |
424 | * | |
425 | * work out if we can queue another buffer into the DMA engine | |
426 | */ | |
427 | ||
428 | static int | |
429 | s3c2410_dma_canload(struct s3c2410_dma_chan *chan) | |
430 | { | |
431 | if (chan->load_state == S3C2410_DMALOAD_NONE || | |
432 | chan->load_state == S3C2410_DMALOAD_1RUNNING) | |
433 | return 1; | |
434 | ||
435 | return 0; | |
436 | } | |
437 | ||
438 | /* s3c2410_dma_enqueue | |
439 | * | |
440 | * queue an given buffer for dma transfer. | |
441 | * | |
442 | * id the device driver's id information for this buffer | |
443 | * data the physical address of the buffer data | |
444 | * size the size of the buffer in bytes | |
445 | * | |
446 | * If the channel is not running, then the flag S3C2410_DMAF_AUTOSTART | |
447 | * is checked, and if set, the channel is started. If this flag isn't set, | |
448 | * then an error will be returned. | |
449 | * | |
450 | * It is possible to queue more than one DMA buffer onto a channel at | |
451 | * once, and the code will deal with the re-loading of the next buffer | |
452 | * when necessary. | |
453 | */ | |
454 | ||
455 | int s3c2410_dma_enqueue(unsigned int channel, void *id, | |
456 | dma_addr_t data, int size) | |
457 | { | |
458 | struct s3c2410_dma_chan *chan = lookup_dma_channel(channel); | |
459 | struct s3c2410_dma_buf *buf; | |
460 | unsigned long flags; | |
461 | ||
462 | if (chan == NULL) | |
463 | return -EINVAL; | |
464 | ||
465 | pr_debug("%s: id=%p, data=%08x, size=%d\n", | |
466 | __FUNCTION__, id, (unsigned int)data, size); | |
467 | ||
468 | buf = kmem_cache_alloc(dma_kmem, GFP_ATOMIC); | |
469 | if (buf == NULL) { | |
470 | pr_debug("%s: out of memory (%ld alloc)\n", | |
471 | __FUNCTION__, (long)sizeof(*buf)); | |
472 | return -ENOMEM; | |
473 | } | |
474 | ||
475 | //pr_debug("%s: new buffer %p\n", __FUNCTION__, buf); | |
476 | //dbg_showchan(chan); | |
477 | ||
478 | buf->next = NULL; | |
479 | buf->data = buf->ptr = data; | |
480 | buf->size = size; | |
481 | buf->id = id; | |
482 | buf->magic = BUF_MAGIC; | |
483 | ||
484 | local_irq_save(flags); | |
485 | ||
486 | if (chan->curr == NULL) { | |
487 | /* we've got nothing loaded... */ | |
488 | pr_debug("%s: buffer %p queued onto empty channel\n", | |
489 | __FUNCTION__, buf); | |
490 | ||
491 | chan->curr = buf; | |
492 | chan->end = buf; | |
493 | chan->next = NULL; | |
494 | } else { | |
495 | pr_debug("dma%d: %s: buffer %p queued onto non-empty channel\n", | |
496 | chan->number, __FUNCTION__, buf); | |
497 | ||
498 | if (chan->end == NULL) | |
499 | pr_debug("dma%d: %s: %p not empty, and chan->end==NULL?\n", | |
500 | chan->number, __FUNCTION__, chan); | |
501 | ||
502 | chan->end->next = buf; | |
503 | chan->end = buf; | |
504 | } | |
505 | ||
506 | /* if necessary, update the next buffer field */ | |
507 | if (chan->next == NULL) | |
508 | chan->next = buf; | |
509 | ||
510 | /* check to see if we can load a buffer */ | |
511 | if (chan->state == S3C2410_DMA_RUNNING) { | |
512 | if (chan->load_state == S3C2410_DMALOAD_1LOADED && 1) { | |
513 | if (s3c2410_dma_waitforload(chan, __LINE__) == 0) { | |
514 | printk(KERN_ERR "dma%d: loadbuffer:" | |
515 | "timeout loading buffer\n", | |
516 | chan->number); | |
517 | dbg_showchan(chan); | |
518 | local_irq_restore(flags); | |
519 | return -EINVAL; | |
520 | } | |
521 | } | |
522 | ||
523 | while (s3c2410_dma_canload(chan) && chan->next != NULL) { | |
524 | s3c2410_dma_loadbuffer(chan, chan->next); | |
525 | } | |
526 | } else if (chan->state == S3C2410_DMA_IDLE) { | |
527 | if (chan->flags & S3C2410_DMAF_AUTOSTART) { | |
528 | s3c2410_dma_ctrl(chan->number, S3C2410_DMAOP_START); | |
529 | } | |
530 | } | |
531 | ||
532 | local_irq_restore(flags); | |
533 | return 0; | |
534 | } | |
535 | ||
536 | EXPORT_SYMBOL(s3c2410_dma_enqueue); | |
537 | ||
538 | static inline void | |
539 | s3c2410_dma_freebuf(struct s3c2410_dma_buf *buf) | |
540 | { | |
541 | int magicok = (buf->magic == BUF_MAGIC); | |
542 | ||
543 | buf->magic = -1; | |
544 | ||
545 | if (magicok) { | |
546 | kmem_cache_free(dma_kmem, buf); | |
547 | } else { | |
548 | printk("s3c2410_dma_freebuf: buff %p with bad magic\n", buf); | |
549 | } | |
550 | } | |
551 | ||
552 | /* s3c2410_dma_lastxfer | |
553 | * | |
554 | * called when the system is out of buffers, to ensure that the channel | |
555 | * is prepared for shutdown. | |
556 | */ | |
557 | ||
558 | static inline void | |
559 | s3c2410_dma_lastxfer(struct s3c2410_dma_chan *chan) | |
560 | { | |
561 | #if 0 | |
562 | pr_debug("dma%d: s3c2410_dma_lastxfer: load_state %d\n", | |
563 | chan->number, chan->load_state); | |
564 | #endif | |
565 | ||
566 | switch (chan->load_state) { | |
567 | case S3C2410_DMALOAD_NONE: | |
568 | break; | |
569 | ||
570 | case S3C2410_DMALOAD_1LOADED: | |
571 | if (s3c2410_dma_waitforload(chan, __LINE__) == 0) { | |
572 | /* flag error? */ | |
573 | printk(KERN_ERR "dma%d: timeout waiting for load (%s)\n", | |
574 | chan->number, __FUNCTION__); | |
575 | return; | |
576 | } | |
577 | break; | |
578 | ||
579 | case S3C2410_DMALOAD_1LOADED_1RUNNING: | |
580 | /* I belive in this case we do not have anything to do | |
581 | * until the next buffer comes along, and we turn off the | |
582 | * reload */ | |
583 | return; | |
584 | ||
585 | default: | |
586 | pr_debug("dma%d: lastxfer: unhandled load_state %d with no next\n", | |
587 | chan->number, chan->load_state); | |
588 | return; | |
589 | ||
590 | } | |
591 | ||
592 | /* hopefully this'll shut the damned thing up after the transfer... */ | |
593 | dma_wrreg(chan, S3C2410_DMA_DCON, chan->dcon | S3C2410_DCON_NORELOAD); | |
594 | } | |
595 | ||
596 | ||
597 | #define dmadbg2(x...) | |
598 | ||
599 | static irqreturn_t | |
600 | s3c2410_dma_irq(int irq, void *devpw) | |
601 | { | |
602 | struct s3c2410_dma_chan *chan = (struct s3c2410_dma_chan *)devpw; | |
603 | struct s3c2410_dma_buf *buf; | |
604 | ||
605 | buf = chan->curr; | |
606 | ||
607 | dbg_showchan(chan); | |
608 | ||
609 | /* modify the channel state */ | |
610 | ||
611 | switch (chan->load_state) { | |
612 | case S3C2410_DMALOAD_1RUNNING: | |
613 | /* TODO - if we are running only one buffer, we probably | |
614 | * want to reload here, and then worry about the buffer | |
615 | * callback */ | |
616 | ||
617 | chan->load_state = S3C2410_DMALOAD_NONE; | |
618 | break; | |
619 | ||
620 | case S3C2410_DMALOAD_1LOADED: | |
621 | /* iirc, we should go back to NONE loaded here, we | |
622 | * had a buffer, and it was never verified as being | |
623 | * loaded. | |
624 | */ | |
625 | ||
626 | chan->load_state = S3C2410_DMALOAD_NONE; | |
627 | break; | |
628 | ||
629 | case S3C2410_DMALOAD_1LOADED_1RUNNING: | |
630 | /* we'll worry about checking to see if another buffer is | |
631 | * ready after we've called back the owner. This should | |
632 | * ensure we do not wait around too long for the DMA | |
633 | * engine to start the next transfer | |
634 | */ | |
635 | ||
636 | chan->load_state = S3C2410_DMALOAD_1LOADED; | |
637 | break; | |
638 | ||
639 | case S3C2410_DMALOAD_NONE: | |
640 | printk(KERN_ERR "dma%d: IRQ with no loaded buffer?\n", | |
641 | chan->number); | |
642 | break; | |
643 | ||
644 | default: | |
645 | printk(KERN_ERR "dma%d: IRQ in invalid load_state %d\n", | |
646 | chan->number, chan->load_state); | |
647 | break; | |
648 | } | |
649 | ||
650 | if (buf != NULL) { | |
651 | /* update the chain to make sure that if we load any more | |
652 | * buffers when we call the callback function, things should | |
653 | * work properly */ | |
654 | ||
655 | chan->curr = buf->next; | |
656 | buf->next = NULL; | |
657 | ||
658 | if (buf->magic != BUF_MAGIC) { | |
659 | printk(KERN_ERR "dma%d: %s: buf %p incorrect magic\n", | |
660 | chan->number, __FUNCTION__, buf); | |
661 | return IRQ_HANDLED; | |
662 | } | |
663 | ||
664 | s3c2410_dma_buffdone(chan, buf, S3C2410_RES_OK); | |
665 | ||
666 | /* free resouces */ | |
667 | s3c2410_dma_freebuf(buf); | |
668 | } else { | |
669 | } | |
670 | ||
671 | /* only reload if the channel is still running... our buffer done | |
672 | * routine may have altered the state by requesting the dma channel | |
673 | * to stop or shutdown... */ | |
674 | ||
675 | /* todo: check that when the channel is shut-down from inside this | |
676 | * function, we cope with unsetting reload, etc */ | |
677 | ||
678 | if (chan->next != NULL && chan->state != S3C2410_DMA_IDLE) { | |
679 | unsigned long flags; | |
680 | ||
681 | switch (chan->load_state) { | |
682 | case S3C2410_DMALOAD_1RUNNING: | |
683 | /* don't need to do anything for this state */ | |
684 | break; | |
685 | ||
686 | case S3C2410_DMALOAD_NONE: | |
687 | /* can load buffer immediately */ | |
688 | break; | |
689 | ||
690 | case S3C2410_DMALOAD_1LOADED: | |
691 | if (s3c2410_dma_waitforload(chan, __LINE__) == 0) { | |
692 | /* flag error? */ | |
693 | printk(KERN_ERR "dma%d: timeout waiting for load (%s)\n", | |
694 | chan->number, __FUNCTION__); | |
695 | return IRQ_HANDLED; | |
696 | } | |
697 | ||
698 | break; | |
699 | ||
700 | case S3C2410_DMALOAD_1LOADED_1RUNNING: | |
701 | goto no_load; | |
702 | ||
703 | default: | |
704 | printk(KERN_ERR "dma%d: unknown load_state in irq, %d\n", | |
705 | chan->number, chan->load_state); | |
706 | return IRQ_HANDLED; | |
707 | } | |
708 | ||
709 | local_irq_save(flags); | |
710 | s3c2410_dma_loadbuffer(chan, chan->next); | |
711 | local_irq_restore(flags); | |
712 | } else { | |
713 | s3c2410_dma_lastxfer(chan); | |
714 | ||
715 | /* see if we can stop this channel.. */ | |
716 | if (chan->load_state == S3C2410_DMALOAD_NONE) { | |
717 | pr_debug("dma%d: end of transfer, stopping channel (%ld)\n", | |
718 | chan->number, jiffies); | |
719 | s3c2410_dma_ctrl(chan->number | DMACH_LOW_LEVEL, | |
720 | S3C2410_DMAOP_STOP); | |
721 | } | |
722 | } | |
723 | ||
724 | no_load: | |
725 | return IRQ_HANDLED; | |
726 | } | |
727 | ||
728 | static struct s3c2410_dma_chan *s3c2410_dma_map_channel(int channel); | |
729 | ||
730 | /* s3c2410_request_dma | |
731 | * | |
732 | * get control of an dma channel | |
733 | */ | |
734 | ||
735 | int s3c2410_dma_request(unsigned int channel, | |
736 | struct s3c2410_dma_client *client, | |
737 | void *dev) | |
738 | { | |
739 | struct s3c2410_dma_chan *chan; | |
740 | unsigned long flags; | |
741 | int err; | |
742 | ||
743 | pr_debug("dma%d: s3c2410_request_dma: client=%s, dev=%p\n", | |
744 | channel, client->name, dev); | |
745 | ||
746 | local_irq_save(flags); | |
747 | ||
748 | chan = s3c2410_dma_map_channel(channel); | |
749 | if (chan == NULL) { | |
750 | local_irq_restore(flags); | |
751 | return -EBUSY; | |
752 | } | |
753 | ||
754 | dbg_showchan(chan); | |
755 | ||
756 | chan->client = client; | |
757 | chan->in_use = 1; | |
758 | ||
759 | if (!chan->irq_claimed) { | |
760 | pr_debug("dma%d: %s : requesting irq %d\n", | |
761 | channel, __FUNCTION__, chan->irq); | |
762 | ||
763 | chan->irq_claimed = 1; | |
764 | local_irq_restore(flags); | |
765 | ||
766 | err = request_irq(chan->irq, s3c2410_dma_irq, IRQF_DISABLED, | |
767 | client->name, (void *)chan); | |
768 | ||
769 | local_irq_save(flags); | |
770 | ||
771 | if (err) { | |
772 | chan->in_use = 0; | |
773 | chan->irq_claimed = 0; | |
774 | local_irq_restore(flags); | |
775 | ||
776 | printk(KERN_ERR "%s: cannot get IRQ %d for DMA %d\n", | |
777 | client->name, chan->irq, chan->number); | |
778 | return err; | |
779 | } | |
780 | ||
781 | chan->irq_enabled = 1; | |
782 | } | |
783 | ||
784 | local_irq_restore(flags); | |
785 | ||
786 | /* need to setup */ | |
787 | ||
788 | pr_debug("%s: channel initialised, %p\n", __FUNCTION__, chan); | |
789 | ||
790 | return 0; | |
791 | } | |
792 | ||
793 | EXPORT_SYMBOL(s3c2410_dma_request); | |
794 | ||
795 | /* s3c2410_dma_free | |
796 | * | |
797 | * release the given channel back to the system, will stop and flush | |
798 | * any outstanding transfers, and ensure the channel is ready for the | |
799 | * next claimant. | |
800 | * | |
801 | * Note, although a warning is currently printed if the freeing client | |
802 | * info is not the same as the registrant's client info, the free is still | |
803 | * allowed to go through. | |
804 | */ | |
805 | ||
806 | int s3c2410_dma_free(dmach_t channel, struct s3c2410_dma_client *client) | |
807 | { | |
808 | struct s3c2410_dma_chan *chan = lookup_dma_channel(channel); | |
809 | unsigned long flags; | |
810 | ||
811 | if (chan == NULL) | |
812 | return -EINVAL; | |
813 | ||
814 | local_irq_save(flags); | |
815 | ||
816 | if (chan->client != client) { | |
817 | printk(KERN_WARNING "dma%d: possible free from different client (channel %p, passed %p)\n", | |
818 | channel, chan->client, client); | |
819 | } | |
820 | ||
821 | /* sort out stopping and freeing the channel */ | |
822 | ||
823 | if (chan->state != S3C2410_DMA_IDLE) { | |
824 | pr_debug("%s: need to stop dma channel %p\n", | |
825 | __FUNCTION__, chan); | |
826 | ||
827 | /* possibly flush the channel */ | |
828 | s3c2410_dma_ctrl(channel, S3C2410_DMAOP_STOP); | |
829 | } | |
830 | ||
831 | chan->client = NULL; | |
832 | chan->in_use = 0; | |
833 | ||
834 | if (chan->irq_claimed) | |
835 | free_irq(chan->irq, (void *)chan); | |
836 | ||
837 | chan->irq_claimed = 0; | |
838 | ||
839 | if (!(channel & DMACH_LOW_LEVEL)) | |
840 | dma_chan_map[channel] = NULL; | |
841 | ||
842 | local_irq_restore(flags); | |
843 | ||
844 | return 0; | |
845 | } | |
846 | ||
847 | EXPORT_SYMBOL(s3c2410_dma_free); | |
848 | ||
849 | static int s3c2410_dma_dostop(struct s3c2410_dma_chan *chan) | |
850 | { | |
851 | unsigned long flags; | |
852 | unsigned long tmp; | |
853 | ||
854 | pr_debug("%s:\n", __FUNCTION__); | |
855 | ||
856 | dbg_showchan(chan); | |
857 | ||
858 | local_irq_save(flags); | |
859 | ||
860 | s3c2410_dma_call_op(chan, S3C2410_DMAOP_STOP); | |
861 | ||
862 | tmp = dma_rdreg(chan, S3C2410_DMA_DMASKTRIG); | |
863 | tmp |= S3C2410_DMASKTRIG_STOP; | |
864 | //tmp &= ~S3C2410_DMASKTRIG_ON; | |
865 | dma_wrreg(chan, S3C2410_DMA_DMASKTRIG, tmp); | |
866 | ||
867 | #if 0 | |
868 | /* should also clear interrupts, according to WinCE BSP */ | |
869 | tmp = dma_rdreg(chan, S3C2410_DMA_DCON); | |
870 | tmp |= S3C2410_DCON_NORELOAD; | |
871 | dma_wrreg(chan, S3C2410_DMA_DCON, tmp); | |
872 | #endif | |
873 | ||
874 | /* should stop do this, or should we wait for flush? */ | |
875 | chan->state = S3C2410_DMA_IDLE; | |
876 | chan->load_state = S3C2410_DMALOAD_NONE; | |
877 | ||
878 | local_irq_restore(flags); | |
879 | ||
880 | return 0; | |
881 | } | |
882 | ||
a7717435 | 883 | static void s3c2410_dma_waitforstop(struct s3c2410_dma_chan *chan) |
a21765a7 BD |
884 | { |
885 | unsigned long tmp; | |
886 | unsigned int timeout = 0x10000; | |
887 | ||
888 | while (timeout-- > 0) { | |
889 | tmp = dma_rdreg(chan, S3C2410_DMA_DMASKTRIG); | |
890 | ||
891 | if (!(tmp & S3C2410_DMASKTRIG_ON)) | |
892 | return; | |
893 | } | |
894 | ||
895 | pr_debug("dma%d: failed to stop?\n", chan->number); | |
896 | } | |
897 | ||
898 | ||
899 | /* s3c2410_dma_flush | |
900 | * | |
901 | * stop the channel, and remove all current and pending transfers | |
902 | */ | |
903 | ||
904 | static int s3c2410_dma_flush(struct s3c2410_dma_chan *chan) | |
905 | { | |
906 | struct s3c2410_dma_buf *buf, *next; | |
907 | unsigned long flags; | |
908 | ||
909 | pr_debug("%s: chan %p (%d)\n", __FUNCTION__, chan, chan->number); | |
910 | ||
911 | dbg_showchan(chan); | |
912 | ||
913 | local_irq_save(flags); | |
914 | ||
915 | if (chan->state != S3C2410_DMA_IDLE) { | |
916 | pr_debug("%s: stopping channel...\n", __FUNCTION__ ); | |
917 | s3c2410_dma_ctrl(chan->number, S3C2410_DMAOP_STOP); | |
918 | } | |
919 | ||
920 | buf = chan->curr; | |
921 | if (buf == NULL) | |
922 | buf = chan->next; | |
923 | ||
924 | chan->curr = chan->next = chan->end = NULL; | |
925 | ||
926 | if (buf != NULL) { | |
927 | for ( ; buf != NULL; buf = next) { | |
928 | next = buf->next; | |
929 | ||
930 | pr_debug("%s: free buffer %p, next %p\n", | |
931 | __FUNCTION__, buf, buf->next); | |
932 | ||
933 | s3c2410_dma_buffdone(chan, buf, S3C2410_RES_ABORT); | |
934 | s3c2410_dma_freebuf(buf); | |
935 | } | |
936 | } | |
937 | ||
938 | dbg_showregs(chan); | |
939 | ||
940 | s3c2410_dma_waitforstop(chan); | |
941 | ||
942 | #if 0 | |
943 | /* should also clear interrupts, according to WinCE BSP */ | |
944 | { | |
945 | unsigned long tmp; | |
946 | ||
947 | tmp = dma_rdreg(chan, S3C2410_DMA_DCON); | |
948 | tmp |= S3C2410_DCON_NORELOAD; | |
949 | dma_wrreg(chan, S3C2410_DMA_DCON, tmp); | |
950 | } | |
951 | #endif | |
952 | ||
953 | dbg_showregs(chan); | |
954 | ||
955 | local_irq_restore(flags); | |
956 | ||
957 | return 0; | |
958 | } | |
959 | ||
a7717435 | 960 | static int s3c2410_dma_started(struct s3c2410_dma_chan *chan) |
a21765a7 BD |
961 | { |
962 | unsigned long flags; | |
963 | ||
964 | local_irq_save(flags); | |
965 | ||
966 | dbg_showchan(chan); | |
967 | ||
968 | /* if we've only loaded one buffer onto the channel, then chec | |
969 | * to see if we have another, and if so, try and load it so when | |
970 | * the first buffer is finished, the new one will be loaded onto | |
971 | * the channel */ | |
972 | ||
973 | if (chan->next != NULL) { | |
974 | if (chan->load_state == S3C2410_DMALOAD_1LOADED) { | |
975 | ||
976 | if (s3c2410_dma_waitforload(chan, __LINE__) == 0) { | |
977 | pr_debug("%s: buff not yet loaded, no more todo\n", | |
978 | __FUNCTION__); | |
979 | } else { | |
980 | chan->load_state = S3C2410_DMALOAD_1RUNNING; | |
981 | s3c2410_dma_loadbuffer(chan, chan->next); | |
982 | } | |
983 | ||
984 | } else if (chan->load_state == S3C2410_DMALOAD_1RUNNING) { | |
985 | s3c2410_dma_loadbuffer(chan, chan->next); | |
986 | } | |
987 | } | |
988 | ||
989 | ||
990 | local_irq_restore(flags); | |
991 | ||
992 | return 0; | |
993 | ||
994 | } | |
995 | ||
996 | int | |
997 | s3c2410_dma_ctrl(dmach_t channel, enum s3c2410_chan_op op) | |
998 | { | |
999 | struct s3c2410_dma_chan *chan = lookup_dma_channel(channel); | |
1000 | ||
1001 | if (chan == NULL) | |
1002 | return -EINVAL; | |
1003 | ||
1004 | switch (op) { | |
1005 | case S3C2410_DMAOP_START: | |
1006 | return s3c2410_dma_start(chan); | |
1007 | ||
1008 | case S3C2410_DMAOP_STOP: | |
1009 | return s3c2410_dma_dostop(chan); | |
1010 | ||
1011 | case S3C2410_DMAOP_PAUSE: | |
1012 | case S3C2410_DMAOP_RESUME: | |
1013 | return -ENOENT; | |
1014 | ||
1015 | case S3C2410_DMAOP_FLUSH: | |
1016 | return s3c2410_dma_flush(chan); | |
1017 | ||
1018 | case S3C2410_DMAOP_STARTED: | |
1019 | return s3c2410_dma_started(chan); | |
1020 | ||
1021 | case S3C2410_DMAOP_TIMEOUT: | |
1022 | return 0; | |
1023 | ||
1024 | } | |
1025 | ||
1026 | return -ENOENT; /* unknown, don't bother */ | |
1027 | } | |
1028 | ||
1029 | EXPORT_SYMBOL(s3c2410_dma_ctrl); | |
1030 | ||
1031 | /* DMA configuration for each channel | |
1032 | * | |
1033 | * DISRCC -> source of the DMA (AHB,APB) | |
1034 | * DISRC -> source address of the DMA | |
1035 | * DIDSTC -> destination of the DMA (AHB,APD) | |
1036 | * DIDST -> destination address of the DMA | |
1037 | */ | |
1038 | ||
1039 | /* s3c2410_dma_config | |
1040 | * | |
1041 | * xfersize: size of unit in bytes (1,2,4) | |
1042 | * dcon: base value of the DCONx register | |
1043 | */ | |
1044 | ||
1045 | int s3c2410_dma_config(dmach_t channel, | |
1046 | int xferunit, | |
1047 | int dcon) | |
1048 | { | |
1049 | struct s3c2410_dma_chan *chan = lookup_dma_channel(channel); | |
1050 | ||
1051 | pr_debug("%s: chan=%d, xfer_unit=%d, dcon=%08x\n", | |
1052 | __FUNCTION__, channel, xferunit, dcon); | |
1053 | ||
1054 | if (chan == NULL) | |
1055 | return -EINVAL; | |
1056 | ||
1057 | pr_debug("%s: Initial dcon is %08x\n", __FUNCTION__, dcon); | |
1058 | ||
1059 | dcon |= chan->dcon & dma_sel.dcon_mask; | |
1060 | ||
1061 | pr_debug("%s: New dcon is %08x\n", __FUNCTION__, dcon); | |
1062 | ||
1063 | switch (xferunit) { | |
1064 | case 1: | |
1065 | dcon |= S3C2410_DCON_BYTE; | |
1066 | break; | |
1067 | ||
1068 | case 2: | |
1069 | dcon |= S3C2410_DCON_HALFWORD; | |
1070 | break; | |
1071 | ||
1072 | case 4: | |
1073 | dcon |= S3C2410_DCON_WORD; | |
1074 | break; | |
1075 | ||
1076 | default: | |
1077 | pr_debug("%s: bad transfer size %d\n", __FUNCTION__, xferunit); | |
1078 | return -EINVAL; | |
1079 | } | |
1080 | ||
1081 | dcon |= S3C2410_DCON_HWTRIG; | |
1082 | dcon |= S3C2410_DCON_INTREQ; | |
1083 | ||
1084 | pr_debug("%s: dcon now %08x\n", __FUNCTION__, dcon); | |
1085 | ||
1086 | chan->dcon = dcon; | |
1087 | chan->xfer_unit = xferunit; | |
1088 | ||
1089 | return 0; | |
1090 | } | |
1091 | ||
1092 | EXPORT_SYMBOL(s3c2410_dma_config); | |
1093 | ||
1094 | int s3c2410_dma_setflags(dmach_t channel, unsigned int flags) | |
1095 | { | |
1096 | struct s3c2410_dma_chan *chan = lookup_dma_channel(channel); | |
1097 | ||
1098 | if (chan == NULL) | |
1099 | return -EINVAL; | |
1100 | ||
1101 | pr_debug("%s: chan=%p, flags=%08x\n", __FUNCTION__, chan, flags); | |
1102 | ||
1103 | chan->flags = flags; | |
1104 | ||
1105 | return 0; | |
1106 | } | |
1107 | ||
1108 | EXPORT_SYMBOL(s3c2410_dma_setflags); | |
1109 | ||
1110 | ||
1111 | /* do we need to protect the settings of the fields from | |
1112 | * irq? | |
1113 | */ | |
1114 | ||
1115 | int s3c2410_dma_set_opfn(dmach_t channel, s3c2410_dma_opfn_t rtn) | |
1116 | { | |
1117 | struct s3c2410_dma_chan *chan = lookup_dma_channel(channel); | |
1118 | ||
1119 | if (chan == NULL) | |
1120 | return -EINVAL; | |
1121 | ||
1122 | pr_debug("%s: chan=%p, op rtn=%p\n", __FUNCTION__, chan, rtn); | |
1123 | ||
1124 | chan->op_fn = rtn; | |
1125 | ||
1126 | return 0; | |
1127 | } | |
1128 | ||
1129 | EXPORT_SYMBOL(s3c2410_dma_set_opfn); | |
1130 | ||
1131 | int s3c2410_dma_set_buffdone_fn(dmach_t channel, s3c2410_dma_cbfn_t rtn) | |
1132 | { | |
1133 | struct s3c2410_dma_chan *chan = lookup_dma_channel(channel); | |
1134 | ||
1135 | if (chan == NULL) | |
1136 | return -EINVAL; | |
1137 | ||
1138 | pr_debug("%s: chan=%p, callback rtn=%p\n", __FUNCTION__, chan, rtn); | |
1139 | ||
1140 | chan->callback_fn = rtn; | |
1141 | ||
1142 | return 0; | |
1143 | } | |
1144 | ||
1145 | EXPORT_SYMBOL(s3c2410_dma_set_buffdone_fn); | |
1146 | ||
1147 | /* s3c2410_dma_devconfig | |
1148 | * | |
1149 | * configure the dma source/destination hardware type and address | |
1150 | * | |
1151 | * source: S3C2410_DMASRC_HW: source is hardware | |
1152 | * S3C2410_DMASRC_MEM: source is memory | |
1153 | * | |
1154 | * hwcfg: the value for xxxSTCn register, | |
1155 | * bit 0: 0=increment pointer, 1=leave pointer | |
6cbdc8c5 | 1156 | * bit 1: 0=source is AHB, 1=source is APB |
a21765a7 BD |
1157 | * |
1158 | * devaddr: physical address of the source | |
1159 | */ | |
1160 | ||
1161 | int s3c2410_dma_devconfig(int channel, | |
1162 | enum s3c2410_dmasrc source, | |
1163 | int hwcfg, | |
1164 | unsigned long devaddr) | |
1165 | { | |
1166 | struct s3c2410_dma_chan *chan = lookup_dma_channel(channel); | |
1167 | ||
1168 | if (chan == NULL) | |
1169 | return -EINVAL; | |
1170 | ||
1171 | pr_debug("%s: source=%d, hwcfg=%08x, devaddr=%08lx\n", | |
1172 | __FUNCTION__, (int)source, hwcfg, devaddr); | |
1173 | ||
1174 | chan->source = source; | |
1175 | chan->dev_addr = devaddr; | |
1176 | ||
1177 | switch (source) { | |
1178 | case S3C2410_DMASRC_HW: | |
1179 | /* source is hardware */ | |
1180 | pr_debug("%s: hw source, devaddr=%08lx, hwcfg=%d\n", | |
1181 | __FUNCTION__, devaddr, hwcfg); | |
1182 | dma_wrreg(chan, S3C2410_DMA_DISRCC, hwcfg & 3); | |
1183 | dma_wrreg(chan, S3C2410_DMA_DISRC, devaddr); | |
1184 | dma_wrreg(chan, S3C2410_DMA_DIDSTC, (0<<1) | (0<<0)); | |
1185 | ||
1186 | chan->addr_reg = dma_regaddr(chan, S3C2410_DMA_DIDST); | |
1187 | return 0; | |
1188 | ||
1189 | case S3C2410_DMASRC_MEM: | |
1190 | /* source is memory */ | |
1191 | pr_debug( "%s: mem source, devaddr=%08lx, hwcfg=%d\n", | |
1192 | __FUNCTION__, devaddr, hwcfg); | |
1193 | dma_wrreg(chan, S3C2410_DMA_DISRCC, (0<<1) | (0<<0)); | |
1194 | dma_wrreg(chan, S3C2410_DMA_DIDST, devaddr); | |
1195 | dma_wrreg(chan, S3C2410_DMA_DIDSTC, hwcfg & 3); | |
1196 | ||
1197 | chan->addr_reg = dma_regaddr(chan, S3C2410_DMA_DISRC); | |
1198 | return 0; | |
1199 | } | |
1200 | ||
1201 | printk(KERN_ERR "dma%d: invalid source type (%d)\n", channel, source); | |
1202 | return -EINVAL; | |
1203 | } | |
1204 | ||
1205 | EXPORT_SYMBOL(s3c2410_dma_devconfig); | |
1206 | ||
1207 | /* s3c2410_dma_getposition | |
1208 | * | |
1209 | * returns the current transfer points for the dma source and destination | |
1210 | */ | |
1211 | ||
1212 | int s3c2410_dma_getposition(dmach_t channel, dma_addr_t *src, dma_addr_t *dst) | |
1213 | { | |
1214 | struct s3c2410_dma_chan *chan = lookup_dma_channel(channel); | |
1215 | ||
1216 | if (chan == NULL) | |
1217 | return -EINVAL; | |
1218 | ||
1219 | if (src != NULL) | |
1220 | *src = dma_rdreg(chan, S3C2410_DMA_DCSRC); | |
1221 | ||
1222 | if (dst != NULL) | |
1223 | *dst = dma_rdreg(chan, S3C2410_DMA_DCDST); | |
1224 | ||
1225 | return 0; | |
1226 | } | |
1227 | ||
1228 | EXPORT_SYMBOL(s3c2410_dma_getposition); | |
1229 | ||
1230 | ||
1231 | /* system device class */ | |
1232 | ||
1233 | #ifdef CONFIG_PM | |
1234 | ||
1235 | static int s3c2410_dma_suspend(struct sys_device *dev, pm_message_t state) | |
1236 | { | |
1237 | struct s3c2410_dma_chan *cp = container_of(dev, struct s3c2410_dma_chan, dev); | |
1238 | ||
1239 | printk(KERN_DEBUG "suspending dma channel %d\n", cp->number); | |
1240 | ||
1241 | if (dma_rdreg(cp, S3C2410_DMA_DMASKTRIG) & S3C2410_DMASKTRIG_ON) { | |
1242 | /* the dma channel is still working, which is probably | |
1243 | * a bad thing to do over suspend/resume. We stop the | |
1244 | * channel and assume that the client is either going to | |
1245 | * retry after resume, or that it is broken. | |
1246 | */ | |
1247 | ||
1248 | printk(KERN_INFO "dma: stopping channel %d due to suspend\n", | |
1249 | cp->number); | |
1250 | ||
1251 | s3c2410_dma_dostop(cp); | |
1252 | } | |
1253 | ||
1254 | return 0; | |
1255 | } | |
1256 | ||
1257 | static int s3c2410_dma_resume(struct sys_device *dev) | |
1258 | { | |
1259 | return 0; | |
1260 | } | |
1261 | ||
1262 | #else | |
1263 | #define s3c2410_dma_suspend NULL | |
1264 | #define s3c2410_dma_resume NULL | |
1265 | #endif /* CONFIG_PM */ | |
1266 | ||
1267 | struct sysdev_class dma_sysclass = { | |
1268 | set_kset_name("s3c24xx-dma"), | |
1269 | .suspend = s3c2410_dma_suspend, | |
1270 | .resume = s3c2410_dma_resume, | |
1271 | }; | |
1272 | ||
1273 | /* kmem cache implementation */ | |
1274 | ||
1275 | static void s3c2410_dma_cache_ctor(void *p, struct kmem_cache *c, unsigned long f) | |
1276 | { | |
1277 | memset(p, 0, sizeof(struct s3c2410_dma_buf)); | |
1278 | } | |
1279 | ||
1280 | /* initialisation code */ | |
1281 | ||
a7717435 | 1282 | static int __init s3c24xx_dma_sysclass_init(void) |
48adbcf3 BD |
1283 | { |
1284 | int ret = sysdev_class_register(&dma_sysclass); | |
1285 | ||
1286 | if (ret != 0) | |
1287 | printk(KERN_ERR "dma sysclass registration failed\n"); | |
1288 | ||
1289 | return ret; | |
1290 | } | |
1291 | ||
1292 | core_initcall(s3c24xx_dma_sysclass_init); | |
1293 | ||
a7717435 | 1294 | static int __init s3c24xx_dma_sysdev_register(void) |
48adbcf3 BD |
1295 | { |
1296 | struct s3c2410_dma_chan *cp = s3c2410_chans; | |
1297 | int channel, ret; | |
1298 | ||
1299 | for (channel = 0; channel < dma_channels; cp++, channel++) { | |
1300 | cp->dev.cls = &dma_sysclass; | |
1301 | cp->dev.id = channel; | |
1302 | ret = sysdev_register(&cp->dev); | |
1303 | ||
1304 | if (ret) { | |
1305 | printk(KERN_ERR "error registering dev for dma %d\n", | |
1306 | channel); | |
1307 | return ret; | |
1308 | } | |
1309 | } | |
1310 | ||
1311 | return 0; | |
1312 | } | |
1313 | ||
1314 | late_initcall(s3c24xx_dma_sysdev_register); | |
1315 | ||
1316 | int __init s3c24xx_dma_init(unsigned int channels, unsigned int irq, | |
1317 | unsigned int stride) | |
a21765a7 BD |
1318 | { |
1319 | struct s3c2410_dma_chan *cp; | |
1320 | int channel; | |
1321 | int ret; | |
1322 | ||
1323 | printk("S3C24XX DMA Driver, (c) 2003-2004,2006 Simtec Electronics\n"); | |
1324 | ||
48adbcf3 BD |
1325 | dma_channels = channels; |
1326 | ||
1327 | dma_base = ioremap(S3C24XX_PA_DMA, stride * channels); | |
a21765a7 BD |
1328 | if (dma_base == NULL) { |
1329 | printk(KERN_ERR "dma failed to remap register block\n"); | |
1330 | return -ENOMEM; | |
1331 | } | |
1332 | ||
48adbcf3 BD |
1333 | dma_kmem = kmem_cache_create("dma_desc", |
1334 | sizeof(struct s3c2410_dma_buf), 0, | |
a21765a7 | 1335 | SLAB_HWCACHE_ALIGN, |
20c2df83 | 1336 | s3c2410_dma_cache_ctor); |
a21765a7 BD |
1337 | |
1338 | if (dma_kmem == NULL) { | |
1339 | printk(KERN_ERR "dma failed to make kmem cache\n"); | |
1340 | ret = -ENOMEM; | |
1341 | goto err; | |
1342 | } | |
1343 | ||
48adbcf3 | 1344 | for (channel = 0; channel < channels; channel++) { |
a21765a7 BD |
1345 | cp = &s3c2410_chans[channel]; |
1346 | ||
1347 | memset(cp, 0, sizeof(struct s3c2410_dma_chan)); | |
1348 | ||
1349 | /* dma channel irqs are in order.. */ | |
1350 | cp->number = channel; | |
48adbcf3 BD |
1351 | cp->irq = channel + irq; |
1352 | cp->regs = dma_base + (channel * stride); | |
a21765a7 BD |
1353 | |
1354 | /* point current stats somewhere */ | |
1355 | cp->stats = &cp->stats_store; | |
1356 | cp->stats_store.timeout_shortest = LONG_MAX; | |
1357 | ||
1358 | /* basic channel configuration */ | |
1359 | ||
1360 | cp->load_timeout = 1<<18; | |
1361 | ||
a21765a7 BD |
1362 | printk("DMA channel %d at %p, irq %d\n", |
1363 | cp->number, cp->regs, cp->irq); | |
1364 | } | |
1365 | ||
1366 | return 0; | |
1367 | ||
1368 | err: | |
1369 | kmem_cache_destroy(dma_kmem); | |
1370 | iounmap(dma_base); | |
1371 | dma_base = NULL; | |
1372 | return ret; | |
1373 | } | |
1374 | ||
48adbcf3 BD |
1375 | int s3c2410_dma_init(void) |
1376 | { | |
1377 | return s3c24xx_dma_init(4, IRQ_DMA0, 0x40); | |
1378 | } | |
a21765a7 BD |
1379 | |
1380 | static inline int is_channel_valid(unsigned int channel) | |
1381 | { | |
1382 | return (channel & DMA_CH_VALID); | |
1383 | } | |
1384 | ||
0c6022d4 BD |
1385 | static struct s3c24xx_dma_order *dma_order; |
1386 | ||
1387 | ||
a21765a7 BD |
1388 | /* s3c2410_dma_map_channel() |
1389 | * | |
1390 | * turn the virtual channel number into a real, and un-used hardware | |
1391 | * channel. | |
1392 | * | |
0c6022d4 BD |
1393 | * first, try the dma ordering given to us by either the relevant |
1394 | * dma code, or the board. Then just find the first usable free | |
1395 | * channel | |
a21765a7 BD |
1396 | */ |
1397 | ||
a7717435 | 1398 | static struct s3c2410_dma_chan *s3c2410_dma_map_channel(int channel) |
a21765a7 | 1399 | { |
0c6022d4 | 1400 | struct s3c24xx_dma_order_ch *ord = NULL; |
a21765a7 BD |
1401 | struct s3c24xx_dma_map *ch_map; |
1402 | struct s3c2410_dma_chan *dmach; | |
1403 | int ch; | |
1404 | ||
1405 | if (dma_sel.map == NULL || channel > dma_sel.map_size) | |
1406 | return NULL; | |
1407 | ||
1408 | ch_map = dma_sel.map + channel; | |
1409 | ||
0c6022d4 BD |
1410 | /* first, try the board mapping */ |
1411 | ||
1412 | if (dma_order) { | |
1413 | ord = &dma_order->channels[channel]; | |
1414 | ||
48adbcf3 | 1415 | for (ch = 0; ch < dma_channels; ch++) { |
0c6022d4 BD |
1416 | if (!is_channel_valid(ord->list[ch])) |
1417 | continue; | |
1418 | ||
1419 | if (s3c2410_chans[ord->list[ch]].in_use == 0) { | |
1420 | ch = ord->list[ch] & ~DMA_CH_VALID; | |
1421 | goto found; | |
1422 | } | |
1423 | } | |
1424 | ||
1425 | if (ord->flags & DMA_CH_NEVER) | |
1426 | return NULL; | |
1427 | } | |
1428 | ||
1429 | /* second, search the channel map for first free */ | |
1430 | ||
48adbcf3 | 1431 | for (ch = 0; ch < dma_channels; ch++) { |
a21765a7 BD |
1432 | if (!is_channel_valid(ch_map->channels[ch])) |
1433 | continue; | |
1434 | ||
1435 | if (s3c2410_chans[ch].in_use == 0) { | |
1436 | printk("mapped channel %d to %d\n", channel, ch); | |
1437 | break; | |
1438 | } | |
1439 | } | |
1440 | ||
48adbcf3 | 1441 | if (ch >= dma_channels) |
a21765a7 BD |
1442 | return NULL; |
1443 | ||
1444 | /* update our channel mapping */ | |
1445 | ||
0c6022d4 | 1446 | found: |
a21765a7 BD |
1447 | dmach = &s3c2410_chans[ch]; |
1448 | dma_chan_map[channel] = dmach; | |
1449 | ||
1450 | /* select the channel */ | |
1451 | ||
1452 | (dma_sel.select)(dmach, ch_map); | |
1453 | ||
1454 | return dmach; | |
1455 | } | |
1456 | ||
a21765a7 BD |
1457 | static int s3c24xx_dma_check_entry(struct s3c24xx_dma_map *map, int ch) |
1458 | { | |
a21765a7 BD |
1459 | return 0; |
1460 | } | |
1461 | ||
1462 | int __init s3c24xx_dma_init_map(struct s3c24xx_dma_selection *sel) | |
1463 | { | |
1464 | struct s3c24xx_dma_map *nmap; | |
1465 | size_t map_sz = sizeof(*nmap) * sel->map_size; | |
1466 | int ptr; | |
1467 | ||
1468 | nmap = kmalloc(map_sz, GFP_KERNEL); | |
1469 | if (nmap == NULL) | |
1470 | return -ENOMEM; | |
1471 | ||
1472 | memcpy(nmap, sel->map, map_sz); | |
1473 | memcpy(&dma_sel, sel, sizeof(*sel)); | |
1474 | ||
1475 | dma_sel.map = nmap; | |
1476 | ||
1477 | for (ptr = 0; ptr < sel->map_size; ptr++) | |
1478 | s3c24xx_dma_check_entry(nmap+ptr, ptr); | |
1479 | ||
1480 | return 0; | |
1481 | } | |
0c6022d4 BD |
1482 | |
1483 | int __init s3c24xx_dma_order_set(struct s3c24xx_dma_order *ord) | |
1484 | { | |
1485 | struct s3c24xx_dma_order *nord = dma_order; | |
1486 | ||
1487 | if (nord == NULL) | |
1488 | nord = kmalloc(sizeof(struct s3c24xx_dma_order), GFP_KERNEL); | |
1489 | ||
1490 | if (nord == NULL) { | |
1491 | printk(KERN_ERR "no memory to store dma channel order\n"); | |
1492 | return -ENOMEM; | |
1493 | } | |
1494 | ||
1495 | dma_order = nord; | |
1496 | memcpy(nord, ord, sizeof(struct s3c24xx_dma_order)); | |
1497 | return 0; | |
1498 | } |