[linux-2.6-block.git] / arch / arm / plat-orion / addr-map.c

/*
 * arch/arm/plat-orion/addr-map.c
 *
 * Address map functions for Marvell Orion based SoCs
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2.  This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/mbus.h>
#include <linux/io.h>
#include <plat/addr-map.h>

struct mbus_dram_target_info orion_mbus_dram_info;

const struct mbus_dram_target_info *mv_mbus_dram_info(void)
{
	return &orion_mbus_dram_info;
}
EXPORT_SYMBOL_GPL(mv_mbus_dram_info);

/*
 * DDR target is the same on all Orion platforms.
 */
#define TARGET_DDR		0

/*
 * Helpers to get DDR bank info
 */
#define DDR_BASE_CS_OFF(n)	(0x0000 + ((n) << 3))
#define DDR_SIZE_CS_OFF(n)	(0x0004 + ((n) << 3))

/*
 * CPU Address Decode Windows registers
 */
#define WIN_CTRL_OFF		0x0000
#define WIN_BASE_OFF		0x0004
#define WIN_REMAP_LO_OFF	0x0008
#define WIN_REMAP_HI_OFF	0x000c

#define ATTR_HW_COHERENCY	(0x1 << 4)

/*
 * Default implementation
 */
static void __init __iomem *
orion_win_cfg_base(const struct orion_addr_map_cfg *cfg, int win)
{
	return cfg->bridge_virt_base + (win << 4);
}

/*
 * Default implementation
 */
static int __init orion_cpu_win_can_remap(const struct orion_addr_map_cfg *cfg,
					  const int win)
{
	if (win < cfg->remappable_wins)
		return 1;

	return 0;
}

void __init orion_setup_cpu_win(const struct orion_addr_map_cfg *cfg,
				const int win, const u32 base,
				const u32 size, const u8 target,
				const u8 attr, const int remap)
{
	void __iomem *addr = cfg->win_cfg_base(cfg, win);
	u32 ctrl, base_high, remap_addr;

	if (win >= cfg->num_wins) {
		printk(KERN_ERR "setup_cpu_win: trying to allocate window "
		       "%d when only %d allowed\n", win, cfg->num_wins);
	}

	base_high = base & 0xffff0000;
	ctrl = ((size - 1) & 0xffff0000) | (attr << 8) | (target << 4) | 1;

	writel(base_high, addr + WIN_BASE_OFF);
	writel(ctrl, addr + WIN_CTRL_OFF);
	if (cfg->cpu_win_can_remap(cfg, win)) {
		if (remap < 0)
			remap_addr = base;
		else
			remap_addr = remap;
		writel(remap_addr & 0xffff0000, addr + WIN_REMAP_LO_OFF);
		writel(0, addr + WIN_REMAP_HI_OFF);
	}
}

/*
 * Configure a number of windows.
 */
static void __init orion_setup_cpu_wins(const struct orion_addr_map_cfg * cfg,
					const struct orion_addr_map_info *info)
{
	while (info->win != -1) {
		orion_setup_cpu_win(cfg, info->win, info->base, info->size,
				    info->target, info->attr, info->remap);
		info++;
	}
}

static void __init orion_disable_wins(const struct orion_addr_map_cfg * cfg)
{
	void __iomem *addr;
	int i;

	for (i = 0; i < cfg->num_wins; i++) {
		addr = cfg->win_cfg_base(cfg, i);

		writel(0, addr + WIN_BASE_OFF);
		writel(0, addr + WIN_CTRL_OFF);
		if (cfg->cpu_win_can_remap(cfg, i)) {
			writel(0, addr + WIN_REMAP_LO_OFF);
			writel(0, addr + WIN_REMAP_HI_OFF);
		}
	}
}

/*
 * Disable, clear and configure windows.
 */
void __init orion_config_wins(struct orion_addr_map_cfg * cfg,
			      const struct orion_addr_map_info *info)
{
	if (!cfg->cpu_win_can_remap)
		cfg->cpu_win_can_remap = orion_cpu_win_can_remap;

	if (!cfg->win_cfg_base)
		cfg->win_cfg_base = orion_win_cfg_base;

	orion_disable_wins(cfg);

	if (info)
		orion_setup_cpu_wins(cfg, info);
}

/*
 * Setup MBUS dram target info.
 */
void __init orion_setup_cpu_mbus_target(const struct orion_addr_map_cfg *cfg,
					const void __iomem *ddr_window_cpu_base)
{
	int i;
	int cs;

	orion_mbus_dram_info.mbus_dram_target_id = TARGET_DDR;

	for (i = 0, cs = 0; i < 4; i++) {
		u32 base = readl(ddr_window_cpu_base + DDR_BASE_CS_OFF(i));
		u32 size = readl(ddr_window_cpu_base + DDR_SIZE_CS_OFF(i));

		/*
		 * We only take care of entries for which the chip
		 * select is enabled, and that don't have high base
		 * address bits set (devices can only access the first
		 * 32 bits of the memory).
		 */
		if ((size & 1) && !(base & 0xF)) {
			struct mbus_dram_window *w;

			w = &orion_mbus_dram_info.cs[cs++];
			w->cs_index = i;
			w->mbus_attr = 0xf & ~(1 << i);
			if (cfg->hw_io_coherency)
				w->mbus_attr |= ATTR_HW_COHERENCY;
			w->base = base & 0xffff0000;
			w->size = (size | 0x0000ffff) + 1;
		}
	}
	orion_mbus_dram_info.num_cs = cs;
}
Commit	Line	Data
b6d1c33a AL	1	/*
	2	* arch/arm/plat-orion/addr-map.c
	3	*
	4	* Address map functions for Marvell Orion based SoCs
	5	*
	6	* This file is licensed under the terms of the GNU General Public
	7	* License version 2. This program is licensed "as is" without any
	8	* warranty of any kind, whether express or implied.
	9	*/
	10
	11	#include <linux/kernel.h>
63a9332b	12	#include <linux/module.h>
b6d1c33a AL	13	#include <linux/init.h>
	14	#include <linux/mbus.h>
	15	#include <linux/io.h>
	16	#include <plat/addr-map.h>
	17
45173d5e AL	18	struct mbus_dram_target_info orion_mbus_dram_info;
45173d5e AL	19
63a9332b AL	20	const struct mbus_dram_target_info *mv_mbus_dram_info(void)
	21	{
	22	return &orion_mbus_dram_info;
	23	}
	24	EXPORT_SYMBOL_GPL(mv_mbus_dram_info);
	25
b6d1c33a AL	26	/*
	27	* DDR target is the same on all Orion platforms.
	28	*/
	29	#define TARGET_DDR 0
	30
	31	/*
	32	* Helpers to get DDR bank info
	33	*/
	34	#define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3))
	35	#define DDR_SIZE_CS_OFF(n) (0x0004 + ((n) << 3))
	36
	37	/*
	38	* CPU Address Decode Windows registers
	39	*/
	40	#define WIN_CTRL_OFF 0x0000
	41	#define WIN_BASE_OFF 0x0004
	42	#define WIN_REMAP_LO_OFF 0x0008
	43	#define WIN_REMAP_HI_OFF 0x000c
	44
722202e1 GC	45	#define ATTR_HW_COHERENCY (0x1 << 4)
722202e1 GC	46
b6d1c33a AL	47	/*
	48	* Default implementation
	49	*/
	50	static void __init __iomem *
	51	orion_win_cfg_base(const struct orion_addr_map_cfg *cfg, int win)
	52	{
9b7b7d8b	53	return cfg->bridge_virt_base + (win << 4);
b6d1c33a AL	54	}
	55
	56	/*
	57	* Default implementation
	58	*/
	59	static int __init orion_cpu_win_can_remap(const struct orion_addr_map_cfg *cfg,
	60	const int win)
	61	{
	62	if (win < cfg->remappable_wins)
	63	return 1;
	64
	65	return 0;
	66	}
	67
	68	void __init orion_setup_cpu_win(const struct orion_addr_map_cfg *cfg,
	69	const int win, const u32 base,
	70	const u32 size, const u8 target,
	71	const u8 attr, const int remap)
	72	{
	73	void __iomem *addr = cfg->win_cfg_base(cfg, win);
	74	u32 ctrl, base_high, remap_addr;
	75
	76	if (win >= cfg->num_wins) {
	77	printk(KERN_ERR "setup_cpu_win: trying to allocate window "
	78	"%d when only %d allowed\n", win, cfg->num_wins);
	79	}
	80
	81	base_high = base & 0xffff0000;
	82	ctrl = ((size - 1) & 0xffff0000) \| (attr << 8) \| (target << 4) \| 1;
	83
	84	writel(base_high, addr + WIN_BASE_OFF);
	85	writel(ctrl, addr + WIN_CTRL_OFF);
	86	if (cfg->cpu_win_can_remap(cfg, win)) {
	87	if (remap < 0)
	88	remap_addr = base;
	89	else
	90	remap_addr = remap;
	91	writel(remap_addr & 0xffff0000, addr + WIN_REMAP_LO_OFF);
	92	writel(0, addr + WIN_REMAP_HI_OFF);
	93	}
	94	}
	95
	96	/*
	97	* Configure a number of windows.
	98	*/
	99	static void __init orion_setup_cpu_wins(const struct orion_addr_map_cfg * cfg,
	100	const struct orion_addr_map_info *info)
	101	{
	102	while (info->win != -1) {
	103	orion_setup_cpu_win(cfg, info->win, info->base, info->size,
	104	info->target, info->attr, info->remap);
	105	info++;
	106	}
	107	}
	108
	109	static void __init orion_disable_wins(const struct orion_addr_map_cfg * cfg)
	110	{
	111	void __iomem *addr;
	112	int i;
	113
	114	for (i = 0; i < cfg->num_wins; i++) {
	115	addr = cfg->win_cfg_base(cfg, i);
	116
	117	writel(0, addr + WIN_BASE_OFF);
118	writel(0, addr + WIN_CTRL_OFF);
119	if (cfg->cpu_win_can_remap(cfg, i)) {
120	writel(0, addr + WIN_REMAP_LO_OFF);
121	writel(0, addr + WIN_REMAP_HI_OFF);
122	}
123	}
124	}
125
126	/*
127	* Disable, clear and configure windows.
128	*/
129	void __init orion_config_wins(struct orion_addr_map_cfg * cfg,
130	const struct orion_addr_map_info *info)
131	{
132	if (!cfg->cpu_win_can_remap)
133	cfg->cpu_win_can_remap = orion_cpu_win_can_remap;
134
135	if (!cfg->win_cfg_base)
136	cfg->win_cfg_base = orion_win_cfg_base;
137
138	orion_disable_wins(cfg);
139
140	if (info)
141	orion_setup_cpu_wins(cfg, info);
142	}
143
144	/*
145	* Setup MBUS dram target info.
146	*/
147	void __init orion_setup_cpu_mbus_target(const struct orion_addr_map_cfg *cfg,
9b7b7d8b	148	const void __iomem *ddr_window_cpu_base)
b6d1c33a	149	{
b6d1c33a AL	150	int i;
	151	int cs;
	152
45173d5e	153	orion_mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
b6d1c33a	154
b6d1c33a	155	for (i = 0, cs = 0; i < 4; i++) {
9b7b7d8b TP	156	u32 base = readl(ddr_window_cpu_base + DDR_BASE_CS_OFF(i));
9b7b7d8b TP	157	u32 size = readl(ddr_window_cpu_base + DDR_SIZE_CS_OFF(i));
b6d1c33a AL	158
b6d1c33a AL	159	/*
217bef3d TP	160	* We only take care of entries for which the chip
	161	* select is enabled, and that don't have high base
	162	* address bits set (devices can only access the first
	163	* 32 bits of the memory).
b6d1c33a	164	*/
217bef3d	165	if ((size & 1) && !(base & 0xF)) {
b6d1c33a AL	166	struct mbus_dram_window *w;
b6d1c33a AL	167
45173d5e	168	w = &orion_mbus_dram_info.cs[cs++];
b6d1c33a AL	169	w->cs_index = i;
b6d1c33a AL	170	w->mbus_attr = 0xf & ~(1 << i);
722202e1 GC	171	if (cfg->hw_io_coherency)
722202e1 GC	172	w->mbus_attr \|= ATTR_HW_COHERENCY;
b6d1c33a AL	173	w->base = base & 0xffff0000;
	174	w->size = (size \| 0x0000ffff) + 1;
	175	}
	176	}
45173d5e	177	orion_mbus_dram_info.num_cs = cs;
b6d1c33a	178	}