[linux-block.git] / arch / arm / plat-omap / mux.c

/*
 * linux/arch/arm/plat-omap/mux.c
 *
 * Utility to set the Omap MUX and PULL_DWN registers from a table in mux.h
 *
 * Copyright (C) 2003 - 2005 Nokia Corporation
 *
 * Written by Tony Lindgren <tony.lindgren@nokia.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
 *
 */
#include <linux/module.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <asm/system.h>
#include <asm/io.h>
#include <linux/spinlock.h>
#include <asm/arch/mux.h>

#ifdef CONFIG_OMAP_MUX

#define OMAP24XX_L4_BASE	0x48000000
#define OMAP24XX_PULL_ENA	(1 << 3)
#define OMAP24XX_PULL_UP	(1 << 4)

static struct pin_config * pin_table;
static unsigned long pin_table_sz;

extern struct pin_config * omap730_pins;
extern struct pin_config * omap1xxx_pins;
extern struct pin_config * omap24xx_pins;

int __init omap_mux_register(struct pin_config * pins, unsigned long size)
{
	pin_table = pins;
	pin_table_sz = size;

	return 0;
}

/*
 * Sets the Omap MUX and PULL_DWN registers based on the table
 */
int __init_or_module omap_cfg_reg(const unsigned long index)
{
	static DEFINE_SPINLOCK(mux_spin_lock);

	unsigned long flags;
	struct pin_config *cfg;
	unsigned int reg_orig = 0, reg = 0, pu_pd_orig = 0, pu_pd = 0,
		pull_orig = 0, pull = 0;
	unsigned int mask, warn = 0;

	if (!pin_table)
		BUG();

	if (index >= pin_table_sz) {
		printk(KERN_ERR "Invalid pin mux index: %lu (%lu)\n",
		       index, pin_table_sz);
		dump_stack();
		return -ENODEV;
	}

	cfg = (struct pin_config *)&pin_table[index];
	if (cpu_is_omap24xx()) {
		u8 reg = 0;

		reg |= cfg->mask & 0x7;
		if (cfg->pull_val)
			reg |= OMAP24XX_PULL_ENA;
		if(cfg->pu_pd_val)
			reg |= OMAP24XX_PULL_UP;
#ifdef CONFIG_OMAP_MUX_DEBUG
		printk("Muxing %s (0x%08x): 0x%02x -> 0x%02x\n",
		       cfg->name, OMAP24XX_L4_BASE + cfg->mux_reg,
		       omap_readb(OMAP24XX_L4_BASE + cfg->mux_reg), reg);
#endif
		omap_writeb(reg, OMAP24XX_L4_BASE + cfg->mux_reg);

		return 0;
	}

	/* Check the mux register in question */
	if (cfg->mux_reg) {
		unsigned	tmp1, tmp2;

		spin_lock_irqsave(&mux_spin_lock, flags);
		reg_orig = omap_readl(cfg->mux_reg);

		/* The mux registers always seem to be 3 bits long */
		mask = (0x7 << cfg->mask_offset);
		tmp1 = reg_orig & mask;
		reg = reg_orig & ~mask;

		tmp2 = (cfg->mask << cfg->mask_offset);
		reg |= tmp2;

		if (tmp1 != tmp2)
			warn = 1;

		omap_writel(reg, cfg->mux_reg);
		spin_unlock_irqrestore(&mux_spin_lock, flags);
	}

	/* Check for pull up or pull down selection on 1610 */
	if (!cpu_is_omap15xx()) {
		if (cfg->pu_pd_reg && cfg->pull_val) {
			spin_lock_irqsave(&mux_spin_lock, flags);
			pu_pd_orig = omap_readl(cfg->pu_pd_reg);
			mask = 1 << cfg->pull_bit;

			if (cfg->pu_pd_val) {
				if (!(pu_pd_orig & mask))
					warn = 1;
				/* Use pull up */
				pu_pd = pu_pd_orig | mask;
			} else {
				if (pu_pd_orig & mask)
					warn = 1;
				/* Use pull down */
				pu_pd = pu_pd_orig & ~mask;
			}
			omap_writel(pu_pd, cfg->pu_pd_reg);
			spin_unlock_irqrestore(&mux_spin_lock, flags);
		}
	}

	/* Check for an associated pull down register */
	if (cfg->pull_reg) {
		spin_lock_irqsave(&mux_spin_lock, flags);
		pull_orig = omap_readl(cfg->pull_reg);
		mask = 1 << cfg->pull_bit;

		if (cfg->pull_val) {
			if (pull_orig & mask)
				warn = 1;
			/* Low bit = pull enabled */
			pull = pull_orig & ~mask;
		} else {
			if (!(pull_orig & mask))
				warn = 1;
			/* High bit = pull disabled */
			pull = pull_orig | mask;
		}

		omap_writel(pull, cfg->pull_reg);
		spin_unlock_irqrestore(&mux_spin_lock, flags);
	}

	if (warn) {
#ifdef CONFIG_OMAP_MUX_WARNINGS
		printk(KERN_WARNING "MUX: initialized %s\n", cfg->name);
#endif
	}

#ifdef CONFIG_OMAP_MUX_DEBUG
	if (cfg->debug || warn) {
		printk("MUX: Setting register %s\n", cfg->name);
		printk("      %s (0x%08x) = 0x%08x -> 0x%08x\n",
		       cfg->mux_reg_name, cfg->mux_reg, reg_orig, reg);

		if (!cpu_is_omap15xx()) {
			if (cfg->pu_pd_reg && cfg->pull_val) {
				printk("      %s (0x%08x) = 0x%08x -> 0x%08x\n",
				       cfg->pu_pd_name, cfg->pu_pd_reg,
				       pu_pd_orig, pu_pd);
			}
		}

		if (cfg->pull_reg)
			printk("      %s (0x%08x) = 0x%08x -> 0x%08x\n",
			       cfg->pull_name, cfg->pull_reg, pull_orig, pull);
	}
#endif

#ifdef CONFIG_OMAP_MUX_ERRORS
	return warn ? -ETXTBSY : 0;
#else
	return 0;
#endif
}
EXPORT_SYMBOL(omap_cfg_reg);
#else
#define omap_mux_init() do {} while(0)
#define omap_cfg_reg(x)	do {} while(0)
#endif	/* CONFIG_OMAP_MUX */
Commit	Line	Data
5e1c5ff4 TL	1	/*
	2	* linux/arch/arm/plat-omap/mux.c
	3	*
	4	* Utility to set the Omap MUX and PULL_DWN registers from a table in mux.h
	5	*
1a8bfa1e	6	* Copyright (C) 2003 - 2005 Nokia Corporation
5e1c5ff4 TL	7	*
	8	* Written by Tony Lindgren <tony.lindgren@nokia.com>
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License as published by
	12	* the Free Software Foundation; either version 2 of the License, or
	13	* (at your option) any later version.
	14	*
	15	* This program is distributed in the hope that it will be useful,
	16	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	18	* GNU General Public License for more details.
	19	*
	20	* You should have received a copy of the GNU General Public License
	21	* along with this program; if not, write to the Free Software
	22	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	23	*
	24	*/
5e1c5ff4 TL	25	#include <linux/module.h>
5e1c5ff4 TL	26	#include <linux/init.h>
1a8bfa1e	27	#include <linux/kernel.h>
5e1c5ff4 TL	28	#include <asm/system.h>
	29	#include <asm/io.h>
	30	#include <linux/spinlock.h>
5e1c5ff4 TL	31	#include <asm/arch/mux.h>
	32
	33	#ifdef CONFIG_OMAP_MUX
	34
1a8bfa1e TL	35	#define OMAP24XX_L4_BASE 0x48000000
	36	#define OMAP24XX_PULL_ENA (1 << 3)
	37	#define OMAP24XX_PULL_UP (1 << 4)
	38
	39	static struct pin_config * pin_table;
	40	static unsigned long pin_table_sz;
	41
	42	extern struct pin_config * omap730_pins;
	43	extern struct pin_config * omap1xxx_pins;
	44	extern struct pin_config * omap24xx_pins;
	45
	46	int __init omap_mux_register(struct pin_config * pins, unsigned long size)
	47	{
	48	pin_table = pins;
	49	pin_table_sz = size;
	50
	51	return 0;
	52	}
	53
5e1c5ff4 TL	54	/*
	55	* Sets the Omap MUX and PULL_DWN registers based on the table
	56	*/
1a8bfa1e	57	int __init_or_module omap_cfg_reg(const unsigned long index)
5e1c5ff4 TL	58	{
	59	static DEFINE_SPINLOCK(mux_spin_lock);
	60
	61	unsigned long flags;
1a8bfa1e	62	struct pin_config *cfg;
5e1c5ff4 TL	63	unsigned int reg_orig = 0, reg = 0, pu_pd_orig = 0, pu_pd = 0,
	64	pull_orig = 0, pull = 0;
	65	unsigned int mask, warn = 0;
	66
1a8bfa1e TL	67	if (!pin_table)
1a8bfa1e TL	68	BUG();
92105bb7	69
1a8bfa1e TL	70	if (index >= pin_table_sz) {
	71	printk(KERN_ERR "Invalid pin mux index: %lu (%lu)\n",
	72	index, pin_table_sz);
	73	dump_stack();
	74	return -ENODEV;
5e1c5ff4 TL	75	}
5e1c5ff4 TL	76
1a8bfa1e TL	77	cfg = (struct pin_config *)&pin_table[index];
	78	if (cpu_is_omap24xx()) {
	79	u8 reg = 0;
	80
	81	reg \|= cfg->mask & 0x7;
	82	if (cfg->pull_val)
	83	reg \|= OMAP24XX_PULL_ENA;
	84	if(cfg->pu_pd_val)
	85	reg \|= OMAP24XX_PULL_UP;
	86	#ifdef CONFIG_OMAP_MUX_DEBUG
	87	printk("Muxing %s (0x%08x): 0x%02x -> 0x%02x\n",
	88	cfg->name, OMAP24XX_L4_BASE + cfg->mux_reg,
	89	omap_readb(OMAP24XX_L4_BASE + cfg->mux_reg), reg);
	90	#endif
	91	omap_writeb(reg, OMAP24XX_L4_BASE + cfg->mux_reg);
	92
	93	return 0;
	94	}
5e1c5ff4 TL	95
	96	/* Check the mux register in question */
	97	if (cfg->mux_reg) {
	98	unsigned tmp1, tmp2;
	99
bb13b5fd	100	spin_lock_irqsave(&mux_spin_lock, flags);
5e1c5ff4 TL	101	reg_orig = omap_readl(cfg->mux_reg);
	102
	103	/* The mux registers always seem to be 3 bits long */
	104	mask = (0x7 << cfg->mask_offset);
	105	tmp1 = reg_orig & mask;
	106	reg = reg_orig & ~mask;
	107
	108	tmp2 = (cfg->mask << cfg->mask_offset);
	109	reg \|= tmp2;
	110
	111	if (tmp1 != tmp2)
	112	warn = 1;
	113
	114	omap_writel(reg, cfg->mux_reg);
bb13b5fd	115	spin_unlock_irqrestore(&mux_spin_lock, flags);
5e1c5ff4 TL	116	}
	117
	118	/* Check for pull up or pull down selection on 1610 */
99c658a6	119	if (!cpu_is_omap15xx()) {
5e1c5ff4	120	if (cfg->pu_pd_reg && cfg->pull_val) {
bb13b5fd	121	spin_lock_irqsave(&mux_spin_lock, flags);
5e1c5ff4 TL	122	pu_pd_orig = omap_readl(cfg->pu_pd_reg);
	123	mask = 1 << cfg->pull_bit;
	124
	125	if (cfg->pu_pd_val) {
	126	if (!(pu_pd_orig & mask))
	127	warn = 1;
	128	/* Use pull up */
	129	pu_pd = pu_pd_orig \| mask;
	130	} else {
	131	if (pu_pd_orig & mask)
	132	warn = 1;
	133	/* Use pull down */
	134	pu_pd = pu_pd_orig & ~mask;
	135	}
	136	omap_writel(pu_pd, cfg->pu_pd_reg);
bb13b5fd	137	spin_unlock_irqrestore(&mux_spin_lock, flags);
5e1c5ff4 TL	138	}
	139	}
	140
	141	/* Check for an associated pull down register */
	142	if (cfg->pull_reg) {
bb13b5fd	143	spin_lock_irqsave(&mux_spin_lock, flags);
5e1c5ff4 TL	144	pull_orig = omap_readl(cfg->pull_reg);
	145	mask = 1 << cfg->pull_bit;
	146
	147	if (cfg->pull_val) {
	148	if (pull_orig & mask)
	149	warn = 1;
	150	/* Low bit = pull enabled */
	151	pull = pull_orig & ~mask;
	152	} else {
	153	if (!(pull_orig & mask))
	154	warn = 1;
	155	/* High bit = pull disabled */
	156	pull = pull_orig \| mask;
	157	}
	158
	159	omap_writel(pull, cfg->pull_reg);
bb13b5fd	160	spin_unlock_irqrestore(&mux_spin_lock, flags);
5e1c5ff4 TL	161	}
	162
	163	if (warn) {
	164	#ifdef CONFIG_OMAP_MUX_WARNINGS
	165	printk(KERN_WARNING "MUX: initialized %s\n", cfg->name);
	166	#endif
	167	}
	168
	169	#ifdef CONFIG_OMAP_MUX_DEBUG
	170	if (cfg->debug \|\| warn) {
	171	printk("MUX: Setting register %s\n", cfg->name);
	172	printk(" %s (0x%08x) = 0x%08x -> 0x%08x\n",
	173	cfg->mux_reg_name, cfg->mux_reg, reg_orig, reg);
	174
99c658a6	175	if (!cpu_is_omap15xx()) {
5e1c5ff4 TL	176	if (cfg->pu_pd_reg && cfg->pull_val) {
	177	printk(" %s (0x%08x) = 0x%08x -> 0x%08x\n",
	178	cfg->pu_pd_name, cfg->pu_pd_reg,
	179	pu_pd_orig, pu_pd);
	180	}
	181	}
	182
	183	if (cfg->pull_reg)
	184	printk(" %s (0x%08x) = 0x%08x -> 0x%08x\n",
	185	cfg->pull_name, cfg->pull_reg, pull_orig, pull);
	186	}
	187	#endif
	188
5e1c5ff4 TL	189	#ifdef CONFIG_OMAP_MUX_ERRORS
	190	return warn ? -ETXTBSY : 0;
	191	#else
	192	return 0;
	193	#endif
	194	}
5e1c5ff4	195	EXPORT_SYMBOL(omap_cfg_reg);
1a8bfa1e TL	196	#else
	197	#define omap_mux_init() do {} while(0)
	198	#define omap_cfg_reg(x) do {} while(0)
5e1c5ff4	199	#endif /* CONFIG_OMAP_MUX */