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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tj/wq
[linux-2.6-block.git] / arch / arm / plat-omap / mcbsp.c
CommitLineData
5e1c5ff4
TL		 1/*
2 * linux/arch/arm/plat-omap/mcbsp.c
3 *
4 * Copyright (C) 2004 Nokia Corporation
5 * Author: Samuel Ortiz <samuel.ortiz@nokia.com>
6 *
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * Multichannel mode not supported.
13 */
14
15#include <linux/module.h>
16#include <linux/init.h>
17#include <linux/device.h>
bc5d0c89 18#include <linux/platform_device.h>
5e1c5ff4
TL		 19#include <linux/wait.h>
20#include <linux/completion.h>
21#include <linux/interrupt.h>
22#include <linux/err.h>
f8ce2547 23#include <linux/clk.h>
04fbf6a2 24#include <linux/delay.h>
fb78d808 25#include <linux/io.h>
5e1c5ff4 26
ce491cf8
TL		 27#include <plat/dma.h>
28#include <plat/mcbsp.h>
5e1c5ff4 29
b4b58f58
CS		 30struct omap_mcbsp **mcbsp_ptr;
31int omap_mcbsp_count;
bc5d0c89 32
b4b58f58
CS		 33void omap_mcbsp_write(void __iomem *io_base, u16 reg, u32 val)
34{
35 if (cpu_class_is_omap1() || cpu_is_omap2420())
36 __raw_writew((u16)val, io_base + reg);
37 else
38 __raw_writel(val, io_base + reg);
39}
40
41int omap_mcbsp_read(void __iomem *io_base, u16 reg)
42{
43 if (cpu_class_is_omap1() || cpu_is_omap2420())
44 return __raw_readw(io_base + reg);
45 else
46 return __raw_readl(io_base + reg);
47}
48
49#define OMAP_MCBSP_READ(base, reg) \
50 omap_mcbsp_read(base, OMAP_MCBSP_REG_##reg)
51#define OMAP_MCBSP_WRITE(base, reg, val) \
52 omap_mcbsp_write(base, OMAP_MCBSP_REG_##reg, val)
53
54#define omap_mcbsp_check_valid_id(id) (id < omap_mcbsp_count)
55#define id_to_mcbsp_ptr(id) mcbsp_ptr[id];
5e1c5ff4
TL		 56
57static void omap_mcbsp_dump_reg(u8 id)
58{
b4b58f58
CS		 59 struct omap_mcbsp *mcbsp = id_to_mcbsp_ptr(id);
60
61 dev_dbg(mcbsp->dev, "**** McBSP%d regs ****\n", mcbsp->id);
62 dev_dbg(mcbsp->dev, "DRR2: 0x%04x\n",
63 OMAP_MCBSP_READ(mcbsp->io_base, DRR2));
64 dev_dbg(mcbsp->dev, "DRR1: 0x%04x\n",
65 OMAP_MCBSP_READ(mcbsp->io_base, DRR1));
66 dev_dbg(mcbsp->dev, "DXR2: 0x%04x\n",
67 OMAP_MCBSP_READ(mcbsp->io_base, DXR2));
68 dev_dbg(mcbsp->dev, "DXR1: 0x%04x\n",
69 OMAP_MCBSP_READ(mcbsp->io_base, DXR1));
70 dev_dbg(mcbsp->dev, "SPCR2: 0x%04x\n",
71 OMAP_MCBSP_READ(mcbsp->io_base, SPCR2));
72 dev_dbg(mcbsp->dev, "SPCR1: 0x%04x\n",
73 OMAP_MCBSP_READ(mcbsp->io_base, SPCR1));
74 dev_dbg(mcbsp->dev, "RCR2: 0x%04x\n",
75 OMAP_MCBSP_READ(mcbsp->io_base, RCR2));
76 dev_dbg(mcbsp->dev, "RCR1: 0x%04x\n",
77 OMAP_MCBSP_READ(mcbsp->io_base, RCR1));
78 dev_dbg(mcbsp->dev, "XCR2: 0x%04x\n",
79 OMAP_MCBSP_READ(mcbsp->io_base, XCR2));
80 dev_dbg(mcbsp->dev, "XCR1: 0x%04x\n",
81 OMAP_MCBSP_READ(mcbsp->io_base, XCR1));
82 dev_dbg(mcbsp->dev, "SRGR2: 0x%04x\n",
83 OMAP_MCBSP_READ(mcbsp->io_base, SRGR2));
84 dev_dbg(mcbsp->dev, "SRGR1: 0x%04x\n",
85 OMAP_MCBSP_READ(mcbsp->io_base, SRGR1));
86 dev_dbg(mcbsp->dev, "PCR0: 0x%04x\n",
87 OMAP_MCBSP_READ(mcbsp->io_base, PCR0));
88 dev_dbg(mcbsp->dev, "***********************\n");
5e1c5ff4
TL		 89}
90
0cd61b68 91static irqreturn_t omap_mcbsp_tx_irq_handler(int irq, void *dev_id)
5e1c5ff4 92{
e8f2af17 93 struct omap_mcbsp *mcbsp_tx = dev_id;
d6d834b0 94 u16 irqst_spcr2;
5e1c5ff4 95
d6d834b0
EN		 96 irqst_spcr2 = OMAP_MCBSP_READ(mcbsp_tx->io_base, SPCR2);
97 dev_dbg(mcbsp_tx->dev, "TX IRQ callback : 0x%x\n", irqst_spcr2);
5e1c5ff4 98
d6d834b0
EN		 99 if (irqst_spcr2 & XSYNC_ERR) {
100 dev_err(mcbsp_tx->dev, "TX Frame Sync Error! : 0x%x\n",
101 irqst_spcr2);
102 /* Writing zero to XSYNC_ERR clears the IRQ */
103 OMAP_MCBSP_WRITE(mcbsp_tx->io_base, SPCR2,
104 irqst_spcr2 & ~(XSYNC_ERR));
105 } else {
106 complete(&mcbsp_tx->tx_irq_completion);
107 }
fb78d808 108
5e1c5ff4
TL		 109 return IRQ_HANDLED;
110}
111
0cd61b68 112static irqreturn_t omap_mcbsp_rx_irq_handler(int irq, void *dev_id)
5e1c5ff4 113{
e8f2af17 114 struct omap_mcbsp *mcbsp_rx = dev_id;
d6d834b0
EN		 115 u16 irqst_spcr1;
116
117 irqst_spcr1 = OMAP_MCBSP_READ(mcbsp_rx->io_base, SPCR1);
118 dev_dbg(mcbsp_rx->dev, "RX IRQ callback : 0x%x\n", irqst_spcr1);
119
120 if (irqst_spcr1 & RSYNC_ERR) {
121 dev_err(mcbsp_rx->dev, "RX Frame Sync Error! : 0x%x\n",
122 irqst_spcr1);
123 /* Writing zero to RSYNC_ERR clears the IRQ */
124 OMAP_MCBSP_WRITE(mcbsp_rx->io_base, SPCR1,
125 irqst_spcr1 & ~(RSYNC_ERR));
126 } else {
127 complete(&mcbsp_rx->tx_irq_completion);
128 }
fb78d808 129
5e1c5ff4
TL		 130 return IRQ_HANDLED;
131}
132
5e1c5ff4
TL		 133static void omap_mcbsp_tx_dma_callback(int lch, u16 ch_status, void *data)
134{
e8f2af17 135 struct omap_mcbsp *mcbsp_dma_tx = data;
5e1c5ff4 136
bc5d0c89
EV		 137 dev_dbg(mcbsp_dma_tx->dev, "TX DMA callback : 0x%x\n",
138 OMAP_MCBSP_READ(mcbsp_dma_tx->io_base, SPCR2));
5e1c5ff4
TL		 139
140 /* We can free the channels */
141 omap_free_dma(mcbsp_dma_tx->dma_tx_lch);
142 mcbsp_dma_tx->dma_tx_lch = -1;
143
144 complete(&mcbsp_dma_tx->tx_dma_completion);
145}
146
147static void omap_mcbsp_rx_dma_callback(int lch, u16 ch_status, void *data)
148{
e8f2af17 149 struct omap_mcbsp *mcbsp_dma_rx = data;
5e1c5ff4 150
bc5d0c89
EV		 151 dev_dbg(mcbsp_dma_rx->dev, "RX DMA callback : 0x%x\n",
152 OMAP_MCBSP_READ(mcbsp_dma_rx->io_base, SPCR2));
5e1c5ff4
TL		 153
154 /* We can free the channels */
155 omap_free_dma(mcbsp_dma_rx->dma_rx_lch);
156 mcbsp_dma_rx->dma_rx_lch = -1;
157
158 complete(&mcbsp_dma_rx->rx_dma_completion);
159}
160
5e1c5ff4
TL		 161/*
162 * omap_mcbsp_config simply write a config to the
163 * appropriate McBSP.
164 * You either call this function or set the McBSP registers
165 * by yourself before calling omap_mcbsp_start().
166 */
fb78d808 167void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg *config)
5e1c5ff4 168{
b4b58f58 169 struct omap_mcbsp *mcbsp;
d592dd1a 170 void __iomem *io_base;
5e1c5ff4 171
bc5d0c89
EV		 172 if (!omap_mcbsp_check_valid_id(id)) {
173 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
174 return;
175 }
b4b58f58 176 mcbsp = id_to_mcbsp_ptr(id);
bc5d0c89 177
b4b58f58
CS		 178 io_base = mcbsp->io_base;
179 dev_dbg(mcbsp->dev, "Configuring McBSP%d phys_base: 0x%08lx\n",
180 mcbsp->id, mcbsp->phys_base);
5e1c5ff4
TL		 181
182 /* We write the given config */
183 OMAP_MCBSP_WRITE(io_base, SPCR2, config->spcr2);
184 OMAP_MCBSP_WRITE(io_base, SPCR1, config->spcr1);
185 OMAP_MCBSP_WRITE(io_base, RCR2, config->rcr2);
186 OMAP_MCBSP_WRITE(io_base, RCR1, config->rcr1);
187 OMAP_MCBSP_WRITE(io_base, XCR2, config->xcr2);
188 OMAP_MCBSP_WRITE(io_base, XCR1, config->xcr1);
189 OMAP_MCBSP_WRITE(io_base, SRGR2, config->srgr2);
190 OMAP_MCBSP_WRITE(io_base, SRGR1, config->srgr1);
191 OMAP_MCBSP_WRITE(io_base, MCR2, config->mcr2);
192 OMAP_MCBSP_WRITE(io_base, MCR1, config->mcr1);
193 OMAP_MCBSP_WRITE(io_base, PCR0, config->pcr0);
a5b92cc3 194 if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
3127f8f8
TL		 195 OMAP_MCBSP_WRITE(io_base, XCCR, config->xccr);
196 OMAP_MCBSP_WRITE(io_base, RCCR, config->rccr);
197 }
5e1c5ff4 198}
fb78d808 199EXPORT_SYMBOL(omap_mcbsp_config);
5e1c5ff4 200
7aa9ff56
EV		 201#ifdef CONFIG_ARCH_OMAP34XX
202/*
203 * omap_mcbsp_set_tx_threshold configures how to deal
204 * with transmit threshold. the threshold value and handler can be
205 * configure in here.
206 */
207void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold)
208{
209 struct omap_mcbsp *mcbsp;
210 void __iomem *io_base;
211
212 if (!cpu_is_omap34xx())
213 return;
214
215 if (!omap_mcbsp_check_valid_id(id)) {
216 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
217 return;
218 }
219 mcbsp = id_to_mcbsp_ptr(id);
220 io_base = mcbsp->io_base;
221
222 OMAP_MCBSP_WRITE(io_base, THRSH2, threshold);
223}
224EXPORT_SYMBOL(omap_mcbsp_set_tx_threshold);
225
226/*
227 * omap_mcbsp_set_rx_threshold configures how to deal
228 * with receive threshold. the threshold value and handler can be
229 * configure in here.
230 */
231void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold)
232{
233 struct omap_mcbsp *mcbsp;
234 void __iomem *io_base;
235
236 if (!cpu_is_omap34xx())
237 return;
238
239 if (!omap_mcbsp_check_valid_id(id)) {
240 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
241 return;
242 }
243 mcbsp = id_to_mcbsp_ptr(id);
244 io_base = mcbsp->io_base;
245
246 OMAP_MCBSP_WRITE(io_base, THRSH1, threshold);
247}
248EXPORT_SYMBOL(omap_mcbsp_set_rx_threshold);
a1a56f5f
EV		 249
250/*
251 * omap_mcbsp_get_max_tx_thres just return the current configured
252 * maximum threshold for transmission
253 */
254u16 omap_mcbsp_get_max_tx_threshold(unsigned int id)
255{
256 struct omap_mcbsp *mcbsp;
257
258 if (!omap_mcbsp_check_valid_id(id)) {
259 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
260 return -ENODEV;
261 }
262 mcbsp = id_to_mcbsp_ptr(id);
263
264 return mcbsp->max_tx_thres;
265}
266EXPORT_SYMBOL(omap_mcbsp_get_max_tx_threshold);
267
268/*
269 * omap_mcbsp_get_max_rx_thres just return the current configured
270 * maximum threshold for reception
271 */
272u16 omap_mcbsp_get_max_rx_threshold(unsigned int id)
273{
274 struct omap_mcbsp *mcbsp;
275
276 if (!omap_mcbsp_check_valid_id(id)) {
277 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
278 return -ENODEV;
279 }
280 mcbsp = id_to_mcbsp_ptr(id);
281
282 return mcbsp->max_rx_thres;
283}
284EXPORT_SYMBOL(omap_mcbsp_get_max_rx_threshold);
98cb20e8
PU		 285
286/*
287 * omap_mcbsp_get_dma_op_mode just return the current configured
288 * operating mode for the mcbsp channel
289 */
290int omap_mcbsp_get_dma_op_mode(unsigned int id)
291{
292 struct omap_mcbsp *mcbsp;
293 int dma_op_mode;
294
295 if (!omap_mcbsp_check_valid_id(id)) {
296 printk(KERN_ERR "%s: Invalid id (%u)\n", __func__, id + 1);
297 return -ENODEV;
298 }
299 mcbsp = id_to_mcbsp_ptr(id);
300
98cb20e8 301 dma_op_mode = mcbsp->dma_op_mode;
98cb20e8
PU		 302
303 return dma_op_mode;
304}
305EXPORT_SYMBOL(omap_mcbsp_get_dma_op_mode);
2122fdc6
EN		 306
307static inline void omap34xx_mcbsp_request(struct omap_mcbsp *mcbsp)
308{
309 /*
310 * Enable wakup behavior, smart idle and all wakeups
311 * REVISIT: some wakeups may be unnecessary
312 */
313 if (cpu_is_omap34xx()) {
314 u16 syscon;
315
316 syscon = OMAP_MCBSP_READ(mcbsp->io_base, SYSCON);
2ba93f8f 317 syscon &= ~(ENAWAKEUP | SIDLEMODE(0x03) | CLOCKACTIVITY(0x03));
d99a7454 318
fa3935ba
EN		 319 if (mcbsp->dma_op_mode == MCBSP_DMA_MODE_THRESHOLD) {
320 syscon |= (ENAWAKEUP | SIDLEMODE(0x02) |
321 CLOCKACTIVITY(0x02));
322 OMAP_MCBSP_WRITE(mcbsp->io_base, WAKEUPEN,
323 XRDYEN | RRDYEN);
324 } else {
d99a7454 325 syscon |= SIDLEMODE(0x01);
fa3935ba 326 }
d99a7454 327
2122fdc6 328 OMAP_MCBSP_WRITE(mcbsp->io_base, SYSCON, syscon);
2122fdc6
EN		 329 }
330}
331
332static inline void omap34xx_mcbsp_free(struct omap_mcbsp *mcbsp)
333{
334 /*
335 * Disable wakup behavior, smart idle and all wakeups
336 */
337 if (cpu_is_omap34xx()) {
338 u16 syscon;
2122fdc6
EN		 339
340 syscon = OMAP_MCBSP_READ(mcbsp->io_base, SYSCON);
2ba93f8f 341 syscon &= ~(ENAWAKEUP | SIDLEMODE(0x03) | CLOCKACTIVITY(0x03));
72cc6d71
EN		 342 /*
343 * HW bug workaround - If no_idle mode is taken, we need to
344 * go to smart_idle before going to always_idle, or the
345 * device will not hit retention anymore.
346 */
347 syscon |= SIDLEMODE(0x02);
348 OMAP_MCBSP_WRITE(mcbsp->io_base, SYSCON, syscon);
349
350 syscon &= ~(SIDLEMODE(0x03));
2122fdc6
EN		 351 OMAP_MCBSP_WRITE(mcbsp->io_base, SYSCON, syscon);
352
d9a9b3f5 353 OMAP_MCBSP_WRITE(mcbsp->io_base, WAKEUPEN, 0);
2122fdc6
EN		 354 }
355}
356#else
357static inline void omap34xx_mcbsp_request(struct omap_mcbsp *mcbsp) {}
358static inline void omap34xx_mcbsp_free(struct omap_mcbsp *mcbsp) {}
7aa9ff56
EV		 359#endif
360
120db2cb
TL		 361/*
362 * We can choose between IRQ based or polled IO.
363 * This needs to be called before omap_mcbsp_request().
364 */
365int omap_mcbsp_set_io_type(unsigned int id, omap_mcbsp_io_type_t io_type)
366{
b4b58f58
CS		 367 struct omap_mcbsp *mcbsp;
368
bc5d0c89
EV		 369 if (!omap_mcbsp_check_valid_id(id)) {
370 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
371 return -ENODEV;
372 }
b4b58f58 373 mcbsp = id_to_mcbsp_ptr(id);
120db2cb 374
b4b58f58 375 spin_lock(&mcbsp->lock);
120db2cb 376
b4b58f58
CS		 377 if (!mcbsp->free) {
378 dev_err(mcbsp->dev, "McBSP%d is currently in use\n",
379 mcbsp->id);
380 spin_unlock(&mcbsp->lock);
120db2cb
TL		 381 return -EINVAL;
382 }
383
b4b58f58 384 mcbsp->io_type = io_type;
120db2cb 385
b4b58f58 386 spin_unlock(&mcbsp->lock);
120db2cb
TL		 387
388 return 0;
389}
fb78d808 390EXPORT_SYMBOL(omap_mcbsp_set_io_type);
5e1c5ff4 391
5e1c5ff4
TL		 392int omap_mcbsp_request(unsigned int id)
393{
b4b58f58 394 struct omap_mcbsp *mcbsp;
5e1c5ff4
TL		 395 int err;
396
bc5d0c89
EV		 397 if (!omap_mcbsp_check_valid_id(id)) {
398 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
399 return -ENODEV;
120db2cb 400 }
b4b58f58 401 mcbsp = id_to_mcbsp_ptr(id);
bc5d0c89 402
b4b58f58
CS		 403 spin_lock(&mcbsp->lock);
404 if (!mcbsp->free) {
405 dev_err(mcbsp->dev, "McBSP%d is currently in use\n",
406 mcbsp->id);
407 spin_unlock(&mcbsp->lock);
b820ce4e 408 return -EBUSY;
5e1c5ff4
TL		 409 }
410
b4b58f58
CS		 411 mcbsp->free = 0;
412 spin_unlock(&mcbsp->lock);
5e1c5ff4 413
b820ce4e
RK		 414 if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->request)
415 mcbsp->pdata->ops->request(id);
416
417 clk_enable(mcbsp->iclk);
418 clk_enable(mcbsp->fclk);
419
2122fdc6
EN		 420 /* Do procedure specific to omap34xx arch, if applicable */
421 omap34xx_mcbsp_request(mcbsp);
422
5a07055a
JN		 423 /*
424 * Make sure that transmitter, receiver and sample-rate generator are
425 * not running before activating IRQs.
426 */
427 OMAP_MCBSP_WRITE(mcbsp->io_base, SPCR1, 0);
428 OMAP_MCBSP_WRITE(mcbsp->io_base, SPCR2, 0);
429
b4b58f58 430 if (mcbsp->io_type == OMAP_MCBSP_IRQ_IO) {
120db2cb 431 /* We need to get IRQs here */
5a07055a 432 init_completion(&mcbsp->tx_irq_completion);
b4b58f58
CS		 433 err = request_irq(mcbsp->tx_irq, omap_mcbsp_tx_irq_handler,
434 0, "McBSP", (void *)mcbsp);
120db2cb 435 if (err != 0) {
b4b58f58
CS		 436 dev_err(mcbsp->dev, "Unable to request TX IRQ %d "
437 "for McBSP%d\n", mcbsp->tx_irq,
438 mcbsp->id);
120db2cb
TL		 439 return err;
440 }
5e1c5ff4 441
5a07055a 442 init_completion(&mcbsp->rx_irq_completion);
b4b58f58
CS		 443 err = request_irq(mcbsp->rx_irq, omap_mcbsp_rx_irq_handler,
444 0, "McBSP", (void *)mcbsp);
120db2cb 445 if (err != 0) {
b4b58f58
CS		 446 dev_err(mcbsp->dev, "Unable to request RX IRQ %d "
447 "for McBSP%d\n", mcbsp->rx_irq,
448 mcbsp->id);
449 free_irq(mcbsp->tx_irq, (void *)mcbsp);
120db2cb
TL		 450 return err;
451 }
5e1c5ff4
TL		 452 }
453
5e1c5ff4 454 return 0;
5e1c5ff4 455}
fb78d808 456EXPORT_SYMBOL(omap_mcbsp_request);
5e1c5ff4
TL		 457
458void omap_mcbsp_free(unsigned int id)
459{
b4b58f58
CS		 460 struct omap_mcbsp *mcbsp;
461
bc5d0c89
EV		 462 if (!omap_mcbsp_check_valid_id(id)) {
463 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
5e1c5ff4 464 return;
120db2cb 465 }
b4b58f58 466 mcbsp = id_to_mcbsp_ptr(id);
bc5d0c89 467
b4b58f58
CS		 468 if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->free)
469 mcbsp->pdata->ops->free(id);
bc5d0c89 470
2122fdc6
EN		 471 /* Do procedure specific to omap34xx arch, if applicable */
472 omap34xx_mcbsp_free(mcbsp);
473
b820ce4e
RK		 474 clk_disable(mcbsp->fclk);
475 clk_disable(mcbsp->iclk);
476
477 if (mcbsp->io_type == OMAP_MCBSP_IRQ_IO) {
478 /* Free IRQs */
479 free_irq(mcbsp->rx_irq, (void *)mcbsp);
480 free_irq(mcbsp->tx_irq, (void *)mcbsp);
481 }
5e1c5ff4 482
b4b58f58
CS		 483 spin_lock(&mcbsp->lock);
484 if (mcbsp->free) {
485 dev_err(mcbsp->dev, "McBSP%d was not reserved\n",
486 mcbsp->id);
487 spin_unlock(&mcbsp->lock);
5e1c5ff4
TL		 488 return;
489 }
490
b4b58f58
CS		 491 mcbsp->free = 1;
492 spin_unlock(&mcbsp->lock);
5e1c5ff4 493}
fb78d808 494EXPORT_SYMBOL(omap_mcbsp_free);
5e1c5ff4
TL		 495
496/*
c12abc01
JN		 497 * Here we start the McBSP, by enabling transmitter, receiver or both.
498 * If no transmitter or receiver is active prior calling, then sample-rate
499 * generator and frame sync are started.
5e1c5ff4 500 */
c12abc01 501void omap_mcbsp_start(unsigned int id, int tx, int rx)
5e1c5ff4 502{
b4b58f58 503 struct omap_mcbsp *mcbsp;
d592dd1a 504 void __iomem *io_base;
c12abc01 505 int idle;
5e1c5ff4
TL		 506 u16 w;
507
bc5d0c89
EV		 508 if (!omap_mcbsp_check_valid_id(id)) {
509 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
5e1c5ff4 510 return;
bc5d0c89 511 }
b4b58f58
CS		 512 mcbsp = id_to_mcbsp_ptr(id);
513 io_base = mcbsp->io_base;
5e1c5ff4 514
b4b58f58
CS		 515 mcbsp->rx_word_length = (OMAP_MCBSP_READ(io_base, RCR1) >> 5) & 0x7;
516 mcbsp->tx_word_length = (OMAP_MCBSP_READ(io_base, XCR1) >> 5) & 0x7;
5e1c5ff4 517
c12abc01
JN		 518 idle = !((OMAP_MCBSP_READ(io_base, SPCR2) |
519 OMAP_MCBSP_READ(io_base, SPCR1)) & 1);
520
521 if (idle) {
522 /* Start the sample generator */
523 w = OMAP_MCBSP_READ(io_base, SPCR2);
524 OMAP_MCBSP_WRITE(io_base, SPCR2, w | (1 << 6));
525 }
5e1c5ff4
TL		 526
527 /* Enable transmitter and receiver */
d09a2afc 528 tx &= 1;
5e1c5ff4 529 w = OMAP_MCBSP_READ(io_base, SPCR2);
d09a2afc 530 OMAP_MCBSP_WRITE(io_base, SPCR2, w | tx);
5e1c5ff4 531
d09a2afc 532 rx &= 1;
5e1c5ff4 533 w = OMAP_MCBSP_READ(io_base, SPCR1);
d09a2afc 534 OMAP_MCBSP_WRITE(io_base, SPCR1, w | rx);
5e1c5ff4 535
44a6311c
EV		 536 /*
537 * Worst case: CLKSRG*2 = 8000khz: (1/8000) * 2 * 2 usec
538 * REVISIT: 100us may give enough time for two CLKSRG, however
539 * due to some unknown PM related, clock gating etc. reason it
540 * is now at 500us.
541 */
542 udelay(500);
5e1c5ff4 543
c12abc01
JN		 544 if (idle) {
545 /* Start frame sync */
546 w = OMAP_MCBSP_READ(io_base, SPCR2);
547 OMAP_MCBSP_WRITE(io_base, SPCR2, w | (1 << 7));
548 }
5e1c5ff4 549
d09a2afc
JN		 550 if (cpu_is_omap2430() || cpu_is_omap34xx()) {
551 /* Release the transmitter and receiver */
552 w = OMAP_MCBSP_READ(io_base, XCCR);
553 w &= ~(tx ? XDISABLE : 0);
554 OMAP_MCBSP_WRITE(io_base, XCCR, w);
555 w = OMAP_MCBSP_READ(io_base, RCCR);
556 w &= ~(rx ? RDISABLE : 0);
557 OMAP_MCBSP_WRITE(io_base, RCCR, w);
558 }
559
5e1c5ff4
TL		 560 /* Dump McBSP Regs */
561 omap_mcbsp_dump_reg(id);
5e1c5ff4 562}
fb78d808 563EXPORT_SYMBOL(omap_mcbsp_start);
5e1c5ff4 564
c12abc01 565void omap_mcbsp_stop(unsigned int id, int tx, int rx)
5e1c5ff4 566{
b4b58f58 567 struct omap_mcbsp *mcbsp;
d592dd1a 568 void __iomem *io_base;
c12abc01 569 int idle;
5e1c5ff4
TL		 570 u16 w;
571
bc5d0c89
EV		 572 if (!omap_mcbsp_check_valid_id(id)) {
573 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
5e1c5ff4 574 return;
bc5d0c89 575 }
5e1c5ff4 576
b4b58f58
CS		 577 mcbsp = id_to_mcbsp_ptr(id);
578 io_base = mcbsp->io_base;
5e1c5ff4 579
fb78d808 580 /* Reset transmitter */
d09a2afc
JN		 581 tx &= 1;
582 if (cpu_is_omap2430() || cpu_is_omap34xx()) {
583 w = OMAP_MCBSP_READ(io_base, XCCR);
584 w |= (tx ? XDISABLE : 0);
585 OMAP_MCBSP_WRITE(io_base, XCCR, w);
586 }
5e1c5ff4 587 w = OMAP_MCBSP_READ(io_base, SPCR2);
d09a2afc 588 OMAP_MCBSP_WRITE(io_base, SPCR2, w & ~tx);
5e1c5ff4
TL		 589
590 /* Reset receiver */
d09a2afc
JN		 591 rx &= 1;
592 if (cpu_is_omap2430() || cpu_is_omap34xx()) {
593 w = OMAP_MCBSP_READ(io_base, RCCR);
a93d4ed2 594 w |= (rx ? RDISABLE : 0);
d09a2afc
JN		 595 OMAP_MCBSP_WRITE(io_base, RCCR, w);
596 }
5e1c5ff4 597 w = OMAP_MCBSP_READ(io_base, SPCR1);
d09a2afc 598 OMAP_MCBSP_WRITE(io_base, SPCR1, w & ~rx);
5e1c5ff4 599
c12abc01
JN		 600 idle = !((OMAP_MCBSP_READ(io_base, SPCR2) |
601 OMAP_MCBSP_READ(io_base, SPCR1)) & 1);
602
603 if (idle) {
604 /* Reset the sample rate generator */
605 w = OMAP_MCBSP_READ(io_base, SPCR2);
606 OMAP_MCBSP_WRITE(io_base, SPCR2, w & ~(1 << 6));
607 }
5e1c5ff4 608}
fb78d808 609EXPORT_SYMBOL(omap_mcbsp_stop);
5e1c5ff4 610
bb13b5fd
TL		 611/* polled mcbsp i/o operations */
612int omap_mcbsp_pollwrite(unsigned int id, u16 buf)
613{
b4b58f58 614 struct omap_mcbsp *mcbsp;
d592dd1a 615 void __iomem *base;
bc5d0c89
EV		 616
617 if (!omap_mcbsp_check_valid_id(id)) {
618 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
619 return -ENODEV;
620 }
621
b4b58f58
CS		 622 mcbsp = id_to_mcbsp_ptr(id);
623 base = mcbsp->io_base;
624
bb13b5fd
TL		 625 writew(buf, base + OMAP_MCBSP_REG_DXR1);
626 /* if frame sync error - clear the error */
627 if (readw(base + OMAP_MCBSP_REG_SPCR2) & XSYNC_ERR) {
628 /* clear error */
629 writew(readw(base + OMAP_MCBSP_REG_SPCR2) & (~XSYNC_ERR),
630 base + OMAP_MCBSP_REG_SPCR2);
631 /* resend */
632 return -1;
633 } else {
634 /* wait for transmit confirmation */
635 int attemps = 0;
636 while (!(readw(base + OMAP_MCBSP_REG_SPCR2) & XRDY)) {
637 if (attemps++ > 1000) {
638 writew(readw(base + OMAP_MCBSP_REG_SPCR2) &
639 (~XRST),
640 base + OMAP_MCBSP_REG_SPCR2);
641 udelay(10);
642 writew(readw(base + OMAP_MCBSP_REG_SPCR2) |
643 (XRST),
644 base + OMAP_MCBSP_REG_SPCR2);
645 udelay(10);
b4b58f58
CS		 646 dev_err(mcbsp->dev, "Could not write to"
647 " McBSP%d Register\n", mcbsp->id);
bb13b5fd
TL		 648 return -2;
649 }
650 }
651 }
fb78d808 652
bb13b5fd
TL		 653 return 0;
654}
fb78d808 655EXPORT_SYMBOL(omap_mcbsp_pollwrite);
bb13b5fd 656
fb78d808 657int omap_mcbsp_pollread(unsigned int id, u16 *buf)
bb13b5fd 658{
b4b58f58 659 struct omap_mcbsp *mcbsp;
d592dd1a 660 void __iomem *base;
bc5d0c89
EV		 661
662 if (!omap_mcbsp_check_valid_id(id)) {
663 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
664 return -ENODEV;
665 }
b4b58f58 666 mcbsp = id_to_mcbsp_ptr(id);
bc5d0c89 667
b4b58f58 668 base = mcbsp->io_base;
bb13b5fd
TL		 669 /* if frame sync error - clear the error */
670 if (readw(base + OMAP_MCBSP_REG_SPCR1) & RSYNC_ERR) {
671 /* clear error */
672 writew(readw(base + OMAP_MCBSP_REG_SPCR1) & (~RSYNC_ERR),
673 base + OMAP_MCBSP_REG_SPCR1);
674 /* resend */
675 return -1;
676 } else {
677 /* wait for recieve confirmation */
678 int attemps = 0;
679 while (!(readw(base + OMAP_MCBSP_REG_SPCR1) & RRDY)) {
680 if (attemps++ > 1000) {
681 writew(readw(base + OMAP_MCBSP_REG_SPCR1) &
682 (~RRST),
683 base + OMAP_MCBSP_REG_SPCR1);
684 udelay(10);
685 writew(readw(base + OMAP_MCBSP_REG_SPCR1) |
686 (RRST),
687 base + OMAP_MCBSP_REG_SPCR1);
688 udelay(10);
b4b58f58
CS		 689 dev_err(mcbsp->dev, "Could not read from"
690 " McBSP%d Register\n", mcbsp->id);
bb13b5fd
TL		 691 return -2;
692 }
693 }
694 }
695 *buf = readw(base + OMAP_MCBSP_REG_DRR1);
fb78d808 696
bb13b5fd
TL		 697 return 0;
698}
fb78d808 699EXPORT_SYMBOL(omap_mcbsp_pollread);
bb13b5fd 700
5e1c5ff4
TL		 701/*
702 * IRQ based word transmission.
703 */
704void omap_mcbsp_xmit_word(unsigned int id, u32 word)
705{
b4b58f58 706 struct omap_mcbsp *mcbsp;
d592dd1a 707 void __iomem *io_base;
bc5d0c89 708 omap_mcbsp_word_length word_length;
5e1c5ff4 709
bc5d0c89
EV		 710 if (!omap_mcbsp_check_valid_id(id)) {
711 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
5e1c5ff4 712 return;
bc5d0c89 713 }
5e1c5ff4 714
b4b58f58
CS		 715 mcbsp = id_to_mcbsp_ptr(id);
716 io_base = mcbsp->io_base;
717 word_length = mcbsp->tx_word_length;
5e1c5ff4 718
b4b58f58 719 wait_for_completion(&mcbsp->tx_irq_completion);
5e1c5ff4
TL		 720
721 if (word_length > OMAP_MCBSP_WORD_16)
722 OMAP_MCBSP_WRITE(io_base, DXR2, word >> 16);
723 OMAP_MCBSP_WRITE(io_base, DXR1, word & 0xffff);
724}
fb78d808 725EXPORT_SYMBOL(omap_mcbsp_xmit_word);
5e1c5ff4
TL		 726
727u32 omap_mcbsp_recv_word(unsigned int id)
728{
b4b58f58 729 struct omap_mcbsp *mcbsp;
d592dd1a 730 void __iomem *io_base;
5e1c5ff4 731 u16 word_lsb, word_msb = 0;
bc5d0c89 732 omap_mcbsp_word_length word_length;
5e1c5ff4 733
bc5d0c89
EV		 734 if (!omap_mcbsp_check_valid_id(id)) {
735 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
736 return -ENODEV;
737 }
b4b58f58 738 mcbsp = id_to_mcbsp_ptr(id);
5e1c5ff4 739
b4b58f58
CS		 740 word_length = mcbsp->rx_word_length;
741 io_base = mcbsp->io_base;
5e1c5ff4 742
b4b58f58 743 wait_for_completion(&mcbsp->rx_irq_completion);
5e1c5ff4
TL		 744
745 if (word_length > OMAP_MCBSP_WORD_16)
746 word_msb = OMAP_MCBSP_READ(io_base, DRR2);
747 word_lsb = OMAP_MCBSP_READ(io_base, DRR1);
748
749 return (word_lsb | (word_msb << 16));
750}
fb78d808 751EXPORT_SYMBOL(omap_mcbsp_recv_word);
5e1c5ff4 752
120db2cb
TL		 753int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word)
754{
b4b58f58 755 struct omap_mcbsp *mcbsp;
d592dd1a 756 void __iomem *io_base;
bc5d0c89
EV		 757 omap_mcbsp_word_length tx_word_length;
758 omap_mcbsp_word_length rx_word_length;
120db2cb
TL		 759 u16 spcr2, spcr1, attempts = 0, word_lsb, word_msb = 0;
760
bc5d0c89
EV		 761 if (!omap_mcbsp_check_valid_id(id)) {
762 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
763 return -ENODEV;
764 }
b4b58f58
CS		 765 mcbsp = id_to_mcbsp_ptr(id);
766 io_base = mcbsp->io_base;
767 tx_word_length = mcbsp->tx_word_length;
768 rx_word_length = mcbsp->rx_word_length;
bc5d0c89 769
120db2cb
TL		 770 if (tx_word_length != rx_word_length)
771 return -EINVAL;
772
773 /* First we wait for the transmitter to be ready */
774 spcr2 = OMAP_MCBSP_READ(io_base, SPCR2);
775 while (!(spcr2 & XRDY)) {
776 spcr2 = OMAP_MCBSP_READ(io_base, SPCR2);
777 if (attempts++ > 1000) {
778 /* We must reset the transmitter */
779 OMAP_MCBSP_WRITE(io_base, SPCR2, spcr2 & (~XRST));
780 udelay(10);
781 OMAP_MCBSP_WRITE(io_base, SPCR2, spcr2 | XRST);
782 udelay(10);
b4b58f58
CS		 783 dev_err(mcbsp->dev, "McBSP%d transmitter not "
784 "ready\n", mcbsp->id);
120db2cb
TL		 785 return -EAGAIN;
786 }
787 }
788
789 /* Now we can push the data */
790 if (tx_word_length > OMAP_MCBSP_WORD_16)
791 OMAP_MCBSP_WRITE(io_base, DXR2, word >> 16);
792 OMAP_MCBSP_WRITE(io_base, DXR1, word & 0xffff);
793
794 /* We wait for the receiver to be ready */
795 spcr1 = OMAP_MCBSP_READ(io_base, SPCR1);
796 while (!(spcr1 & RRDY)) {
797 spcr1 = OMAP_MCBSP_READ(io_base, SPCR1);
798 if (attempts++ > 1000) {
799 /* We must reset the receiver */
800 OMAP_MCBSP_WRITE(io_base, SPCR1, spcr1 & (~RRST));
801 udelay(10);
802 OMAP_MCBSP_WRITE(io_base, SPCR1, spcr1 | RRST);
803 udelay(10);
b4b58f58
CS		 804 dev_err(mcbsp->dev, "McBSP%d receiver not "
805 "ready\n", mcbsp->id);
120db2cb
TL		 806 return -EAGAIN;
807 }
808 }
809
810 /* Receiver is ready, let's read the dummy data */
811 if (rx_word_length > OMAP_MCBSP_WORD_16)
812 word_msb = OMAP_MCBSP_READ(io_base, DRR2);
813 word_lsb = OMAP_MCBSP_READ(io_base, DRR1);
814
815 return 0;
816}
fb78d808 817EXPORT_SYMBOL(omap_mcbsp_spi_master_xmit_word_poll);
120db2cb 818
fb78d808 819int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 *word)
120db2cb 820{
b4b58f58 821 struct omap_mcbsp *mcbsp;
d592dd1a
RK		 822 u32 clock_word = 0;
823 void __iomem *io_base;
bc5d0c89
EV		 824 omap_mcbsp_word_length tx_word_length;
825 omap_mcbsp_word_length rx_word_length;
120db2cb
TL		 826 u16 spcr2, spcr1, attempts = 0, word_lsb, word_msb = 0;
827
bc5d0c89
EV		 828 if (!omap_mcbsp_check_valid_id(id)) {
829 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
830 return -ENODEV;
831 }
832
b4b58f58
CS		 833 mcbsp = id_to_mcbsp_ptr(id);
834 io_base = mcbsp->io_base;
835
836 tx_word_length = mcbsp->tx_word_length;
837 rx_word_length = mcbsp->rx_word_length;
bc5d0c89 838
120db2cb
TL		 839 if (tx_word_length != rx_word_length)
840 return -EINVAL;
841
842 /* First we wait for the transmitter to be ready */
843 spcr2 = OMAP_MCBSP_READ(io_base, SPCR2);
844 while (!(spcr2 & XRDY)) {
845 spcr2 = OMAP_MCBSP_READ(io_base, SPCR2);
846 if (attempts++ > 1000) {
847 /* We must reset the transmitter */
848 OMAP_MCBSP_WRITE(io_base, SPCR2, spcr2 & (~XRST));
849 udelay(10);
850 OMAP_MCBSP_WRITE(io_base, SPCR2, spcr2 | XRST);
851 udelay(10);
b4b58f58
CS		 852 dev_err(mcbsp->dev, "McBSP%d transmitter not "
853 "ready\n", mcbsp->id);
120db2cb
TL		 854 return -EAGAIN;
855 }
856 }
857
858 /* We first need to enable the bus clock */
859 if (tx_word_length > OMAP_MCBSP_WORD_16)
860 OMAP_MCBSP_WRITE(io_base, DXR2, clock_word >> 16);
861 OMAP_MCBSP_WRITE(io_base, DXR1, clock_word & 0xffff);
862
863 /* We wait for the receiver to be ready */
864 spcr1 = OMAP_MCBSP_READ(io_base, SPCR1);
865 while (!(spcr1 & RRDY)) {
866 spcr1 = OMAP_MCBSP_READ(io_base, SPCR1);
867 if (attempts++ > 1000) {
868 /* We must reset the receiver */
869 OMAP_MCBSP_WRITE(io_base, SPCR1, spcr1 & (~RRST));
870 udelay(10);
871 OMAP_MCBSP_WRITE(io_base, SPCR1, spcr1 | RRST);
872 udelay(10);
b4b58f58
CS		 873 dev_err(mcbsp->dev, "McBSP%d receiver not "
874 "ready\n", mcbsp->id);
120db2cb
TL		 875 return -EAGAIN;
876 }
877 }
878
879 /* Receiver is ready, there is something for us */
880 if (rx_word_length > OMAP_MCBSP_WORD_16)
881 word_msb = OMAP_MCBSP_READ(io_base, DRR2);
882 word_lsb = OMAP_MCBSP_READ(io_base, DRR1);
883
884 word[0] = (word_lsb | (word_msb << 16));
885
886 return 0;
887}
fb78d808 888EXPORT_SYMBOL(omap_mcbsp_spi_master_recv_word_poll);
120db2cb 889
5e1c5ff4
TL		 890/*
891 * Simple DMA based buffer rx/tx routines.
892 * Nothing fancy, just a single buffer tx/rx through DMA.
893 * The DMA resources are released once the transfer is done.
894 * For anything fancier, you should use your own customized DMA
895 * routines and callbacks.
896 */
fb78d808
EV		 897int omap_mcbsp_xmit_buffer(unsigned int id, dma_addr_t buffer,
898 unsigned int length)
5e1c5ff4 899{
b4b58f58 900 struct omap_mcbsp *mcbsp;
5e1c5ff4 901 int dma_tx_ch;
120db2cb
TL		 902 int src_port = 0;
903 int dest_port = 0;
904 int sync_dev = 0;
5e1c5ff4 905
bc5d0c89
EV		 906 if (!omap_mcbsp_check_valid_id(id)) {
907 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
908 return -ENODEV;
909 }
b4b58f58 910 mcbsp = id_to_mcbsp_ptr(id);
5e1c5ff4 911
b4b58f58 912 if (omap_request_dma(mcbsp->dma_tx_sync, "McBSP TX",
fb78d808 913 omap_mcbsp_tx_dma_callback,
b4b58f58 914 mcbsp,
fb78d808 915 &dma_tx_ch)) {
b4b58f58 916 dev_err(mcbsp->dev, " Unable to request DMA channel for "
bc5d0c89 917 "McBSP%d TX. Trying IRQ based TX\n",
b4b58f58 918 mcbsp->id);
5e1c5ff4
TL		 919 return -EAGAIN;
920 }
b4b58f58 921 mcbsp->dma_tx_lch = dma_tx_ch;
5e1c5ff4 922
b4b58f58 923 dev_err(mcbsp->dev, "McBSP%d TX DMA on channel %d\n", mcbsp->id,
bc5d0c89 924 dma_tx_ch);
5e1c5ff4 925
b4b58f58 926 init_completion(&mcbsp->tx_dma_completion);
5e1c5ff4 927
120db2cb
TL		 928 if (cpu_class_is_omap1()) {
929 src_port = OMAP_DMA_PORT_TIPB;
930 dest_port = OMAP_DMA_PORT_EMIFF;
931 }
bc5d0c89 932 if (cpu_class_is_omap2())
b4b58f58 933 sync_dev = mcbsp->dma_tx_sync;
120db2cb 934
b4b58f58 935 omap_set_dma_transfer_params(mcbsp->dma_tx_lch,
5e1c5ff4
TL		 936 OMAP_DMA_DATA_TYPE_S16,
937 length >> 1, 1,
1a8bfa1e 938 OMAP_DMA_SYNC_ELEMENT,
120db2cb 939 sync_dev, 0);
5e1c5ff4 940
b4b58f58 941 omap_set_dma_dest_params(mcbsp->dma_tx_lch,
120db2cb 942 src_port,
5e1c5ff4 943 OMAP_DMA_AMODE_CONSTANT,
b4b58f58 944 mcbsp->phys_base + OMAP_MCBSP_REG_DXR1,
1a8bfa1e 945 0, 0);
5e1c5ff4 946
b4b58f58 947 omap_set_dma_src_params(mcbsp->dma_tx_lch,
120db2cb 948 dest_port,
5e1c5ff4 949 OMAP_DMA_AMODE_POST_INC,
1a8bfa1e
TL		 950 buffer,
951 0, 0);
5e1c5ff4 952
b4b58f58
CS		 953 omap_start_dma(mcbsp->dma_tx_lch);
954 wait_for_completion(&mcbsp->tx_dma_completion);
fb78d808 955
5e1c5ff4
TL		 956 return 0;
957}
fb78d808 958EXPORT_SYMBOL(omap_mcbsp_xmit_buffer);
5e1c5ff4 959
fb78d808
EV		 960int omap_mcbsp_recv_buffer(unsigned int id, dma_addr_t buffer,
961 unsigned int length)
5e1c5ff4 962{
b4b58f58 963 struct omap_mcbsp *mcbsp;
5e1c5ff4 964 int dma_rx_ch;
120db2cb
TL		 965 int src_port = 0;
966 int dest_port = 0;
967 int sync_dev = 0;
5e1c5ff4 968
bc5d0c89
EV		 969 if (!omap_mcbsp_check_valid_id(id)) {
970 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
971 return -ENODEV;
972 }
b4b58f58 973 mcbsp = id_to_mcbsp_ptr(id);
5e1c5ff4 974
b4b58f58 975 if (omap_request_dma(mcbsp->dma_rx_sync, "McBSP RX",
fb78d808 976 omap_mcbsp_rx_dma_callback,
b4b58f58 977 mcbsp,
fb78d808 978 &dma_rx_ch)) {
b4b58f58 979 dev_err(mcbsp->dev, "Unable to request DMA channel for "
bc5d0c89 980 "McBSP%d RX. Trying IRQ based RX\n",
b4b58f58 981 mcbsp->id);
5e1c5ff4
TL		 982 return -EAGAIN;
983 }
b4b58f58 984 mcbsp->dma_rx_lch = dma_rx_ch;
5e1c5ff4 985
b4b58f58 986 dev_err(mcbsp->dev, "McBSP%d RX DMA on channel %d\n", mcbsp->id,
bc5d0c89 987 dma_rx_ch);
5e1c5ff4 988
b4b58f58 989 init_completion(&mcbsp->rx_dma_completion);
5e1c5ff4 990
120db2cb
TL		 991 if (cpu_class_is_omap1()) {
992 src_port = OMAP_DMA_PORT_TIPB;
993 dest_port = OMAP_DMA_PORT_EMIFF;
994 }
bc5d0c89 995 if (cpu_class_is_omap2())
b4b58f58 996 sync_dev = mcbsp->dma_rx_sync;
120db2cb 997
b4b58f58 998 omap_set_dma_transfer_params(mcbsp->dma_rx_lch,
fb78d808
EV		 999 OMAP_DMA_DATA_TYPE_S16,
1000 length >> 1, 1,
1001 OMAP_DMA_SYNC_ELEMENT,
1002 sync_dev, 0);
5e1c5ff4 1003
b4b58f58 1004 omap_set_dma_src_params(mcbsp->dma_rx_lch,
120db2cb 1005 src_port,
5e1c5ff4 1006 OMAP_DMA_AMODE_CONSTANT,
b4b58f58 1007 mcbsp->phys_base + OMAP_MCBSP_REG_DRR1,
1a8bfa1e 1008 0, 0);
5e1c5ff4 1009
b4b58f58 1010 omap_set_dma_dest_params(mcbsp->dma_rx_lch,
fb78d808
EV		 1011 dest_port,
1012 OMAP_DMA_AMODE_POST_INC,
1013 buffer,
1014 0, 0);
5e1c5ff4 1015
b4b58f58
CS		 1016 omap_start_dma(mcbsp->dma_rx_lch);
1017 wait_for_completion(&mcbsp->rx_dma_completion);
fb78d808 1018
5e1c5ff4
TL		 1019 return 0;
1020}
fb78d808 1021EXPORT_SYMBOL(omap_mcbsp_recv_buffer);
5e1c5ff4
TL		 1022
1023/*
1024 * SPI wrapper.
1025 * Since SPI setup is much simpler than the generic McBSP one,
1026 * this wrapper just need an omap_mcbsp_spi_cfg structure as an input.
1027 * Once this is done, you can call omap_mcbsp_start().
1028 */
fb78d808
EV		 1029void omap_mcbsp_set_spi_mode(unsigned int id,
1030 const struct omap_mcbsp_spi_cfg *spi_cfg)
5e1c5ff4 1031{
b4b58f58 1032 struct omap_mcbsp *mcbsp;
5e1c5ff4
TL		 1033 struct omap_mcbsp_reg_cfg mcbsp_cfg;
1034
bc5d0c89
EV		 1035 if (!omap_mcbsp_check_valid_id(id)) {
1036 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
5e1c5ff4 1037 return;
bc5d0c89 1038 }
b4b58f58 1039 mcbsp = id_to_mcbsp_ptr(id);
5e1c5ff4
TL		 1040
1041 memset(&mcbsp_cfg, 0, sizeof(struct omap_mcbsp_reg_cfg));
1042
1043 /* SPI has only one frame */
1044 mcbsp_cfg.rcr1 |= (RWDLEN1(spi_cfg->word_length) | RFRLEN1(0));
1045 mcbsp_cfg.xcr1 |= (XWDLEN1(spi_cfg->word_length) | XFRLEN1(0));
1046
fb78d808 1047 /* Clock stop mode */
5e1c5ff4
TL		 1048 if (spi_cfg->clk_stp_mode == OMAP_MCBSP_CLK_STP_MODE_NO_DELAY)
1049 mcbsp_cfg.spcr1 |= (1 << 12);
1050 else
1051 mcbsp_cfg.spcr1 |= (3 << 11);
1052
1053 /* Set clock parities */
1054 if (spi_cfg->rx_clock_polarity == OMAP_MCBSP_CLK_RISING)
1055 mcbsp_cfg.pcr0 |= CLKRP;
1056 else
1057 mcbsp_cfg.pcr0 &= ~CLKRP;
1058
1059 if (spi_cfg->tx_clock_polarity == OMAP_MCBSP_CLK_RISING)
1060 mcbsp_cfg.pcr0 &= ~CLKXP;
1061 else
1062 mcbsp_cfg.pcr0 |= CLKXP;
1063
1064 /* Set SCLKME to 0 and CLKSM to 1 */
1065 mcbsp_cfg.pcr0 &= ~SCLKME;
1066 mcbsp_cfg.srgr2 |= CLKSM;
1067
1068 /* Set FSXP */
1069 if (spi_cfg->fsx_polarity == OMAP_MCBSP_FS_ACTIVE_HIGH)
1070 mcbsp_cfg.pcr0 &= ~FSXP;
1071 else
1072 mcbsp_cfg.pcr0 |= FSXP;
1073
1074 if (spi_cfg->spi_mode == OMAP_MCBSP_SPI_MASTER) {
1075 mcbsp_cfg.pcr0 |= CLKXM;
fb78d808 1076 mcbsp_cfg.srgr1 |= CLKGDV(spi_cfg->clk_div - 1);
5e1c5ff4
TL		 1077 mcbsp_cfg.pcr0 |= FSXM;
1078 mcbsp_cfg.srgr2 &= ~FSGM;
1079 mcbsp_cfg.xcr2 |= XDATDLY(1);
1080 mcbsp_cfg.rcr2 |= RDATDLY(1);
fb78d808 1081 } else {
5e1c5ff4
TL		 1082 mcbsp_cfg.pcr0 &= ~CLKXM;
1083 mcbsp_cfg.srgr1 |= CLKGDV(1);
1084 mcbsp_cfg.pcr0 &= ~FSXM;
1085 mcbsp_cfg.xcr2 &= ~XDATDLY(3);
1086 mcbsp_cfg.rcr2 &= ~RDATDLY(3);
1087 }
1088
1089 mcbsp_cfg.xcr2 &= ~XPHASE;
1090 mcbsp_cfg.rcr2 &= ~RPHASE;
1091
1092 omap_mcbsp_config(id, &mcbsp_cfg);
1093}
fb78d808 1094EXPORT_SYMBOL(omap_mcbsp_set_spi_mode);
5e1c5ff4 1095
a1a56f5f
EV		 1096#ifdef CONFIG_ARCH_OMAP34XX
1097#define max_thres(m) (mcbsp->pdata->buffer_size)
1098#define valid_threshold(m, val) ((val) <= max_thres(m))
1099#define THRESHOLD_PROP_BUILDER(prop) \
1100static ssize_t prop##_show(struct device *dev, \
1101 struct device_attribute *attr, char *buf) \
1102{ \
1103 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev); \
1104 \
1105 return sprintf(buf, "%u\n", mcbsp->prop); \
1106} \
1107 \
1108static ssize_t prop##_store(struct device *dev, \
1109 struct device_attribute *attr, \
1110 const char *buf, size_t size) \
1111{ \
1112 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev); \
1113 unsigned long val; \
1114 int status; \
1115 \
1116 status = strict_strtoul(buf, 0, &val); \
1117 if (status) \
1118 return status; \
1119 \
1120 if (!valid_threshold(mcbsp, val)) \
1121 return -EDOM; \
1122 \
1123 mcbsp->prop = val; \
1124 return size; \
1125} \
1126 \
1127static DEVICE_ATTR(prop, 0644, prop##_show, prop##_store);
1128
1129THRESHOLD_PROP_BUILDER(max_tx_thres);
1130THRESHOLD_PROP_BUILDER(max_rx_thres);
1131
9b300509
JN		 1132static const char *dma_op_modes[] = {
1133 "element", "threshold", "frame",
1134};
1135
98cb20e8
PU		 1136static ssize_t dma_op_mode_show(struct device *dev,
1137 struct device_attribute *attr, char *buf)
1138{
1139 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
9b300509
JN		 1140 int dma_op_mode, i = 0;
1141 ssize_t len = 0;
1142 const char * const *s;
98cb20e8 1143
98cb20e8 1144 dma_op_mode = mcbsp->dma_op_mode;
98cb20e8 1145
9b300509
JN		 1146 for (s = &dma_op_modes[i]; i < ARRAY_SIZE(dma_op_modes); s++, i++) {
1147 if (dma_op_mode == i)
1148 len += sprintf(buf + len, "[%s] ", *s);
1149 else
1150 len += sprintf(buf + len, "%s ", *s);
1151 }
1152 len += sprintf(buf + len, "\n");
1153
1154 return len;
98cb20e8
PU		 1155}
1156
1157static ssize_t dma_op_mode_store(struct device *dev,
1158 struct device_attribute *attr,
1159 const char *buf, size_t size)
1160{
1161 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
9b300509
JN		 1162 const char * const *s;
1163 int i = 0;
98cb20e8 1164
9b300509
JN		 1165 for (s = &dma_op_modes[i]; i < ARRAY_SIZE(dma_op_modes); s++, i++)
1166 if (sysfs_streq(buf, *s))
1167 break;
98cb20e8 1168
9b300509
JN		 1169 if (i == ARRAY_SIZE(dma_op_modes))
1170 return -EINVAL;
98cb20e8 1171
9b300509 1172 spin_lock_irq(&mcbsp->lock);
98cb20e8
PU		 1173 if (!mcbsp->free) {
1174 size = -EBUSY;
1175 goto unlock;
1176 }
9b300509 1177 mcbsp->dma_op_mode = i;
98cb20e8
PU		 1178
1179unlock:
1180 spin_unlock_irq(&mcbsp->lock);
1181
1182 return size;
1183}
1184
1185static DEVICE_ATTR(dma_op_mode, 0644, dma_op_mode_show, dma_op_mode_store);
1186
4c8200ae 1187static const struct attribute *additional_attrs[] = {
a1a56f5f
EV		 1188 &dev_attr_max_tx_thres.attr,
1189 &dev_attr_max_rx_thres.attr,
98cb20e8 1190 &dev_attr_dma_op_mode.attr,
a1a56f5f
EV		 1191 NULL,
1192};
1193
4c8200ae
EV		 1194static const struct attribute_group additional_attr_group = {
1195 .attrs = (struct attribute **)additional_attrs,
a1a56f5f
EV		 1196};
1197
4c8200ae 1198static inline int __devinit omap_additional_add(struct device *dev)
a1a56f5f 1199{
4c8200ae 1200 return sysfs_create_group(&dev->kobj, &additional_attr_group);
a1a56f5f
EV		 1201}
1202
4c8200ae 1203static inline void __devexit omap_additional_remove(struct device *dev)
a1a56f5f 1204{
4c8200ae 1205 sysfs_remove_group(&dev->kobj, &additional_attr_group);
a1a56f5f
EV		 1206}
1207
1208static inline void __devinit omap34xx_device_init(struct omap_mcbsp *mcbsp)
1209{
98cb20e8 1210 mcbsp->dma_op_mode = MCBSP_DMA_MODE_ELEMENT;
a1a56f5f
EV		 1211 if (cpu_is_omap34xx()) {
1212 mcbsp->max_tx_thres = max_thres(mcbsp);
1213 mcbsp->max_rx_thres = max_thres(mcbsp);
98cb20e8
PU		 1214 /*
1215 * REVISIT: Set dmap_op_mode to THRESHOLD as default
1216 * for mcbsp2 instances.
1217 */
4c8200ae 1218 if (omap_additional_add(mcbsp->dev))
a1a56f5f 1219 dev_warn(mcbsp->dev,
4c8200ae 1220 "Unable to create additional controls\n");
a1a56f5f
EV		 1221 } else {
1222 mcbsp->max_tx_thres = -EINVAL;
1223 mcbsp->max_rx_thres = -EINVAL;
1224 }
1225}
1226
1227static inline void __devexit omap34xx_device_exit(struct omap_mcbsp *mcbsp)
1228{
1229 if (cpu_is_omap34xx())
4c8200ae 1230 omap_additional_remove(mcbsp->dev);
a1a56f5f
EV		 1231}
1232#else
1233static inline void __devinit omap34xx_device_init(struct omap_mcbsp *mcbsp) {}
1234static inline void __devexit omap34xx_device_exit(struct omap_mcbsp *mcbsp) {}
1235#endif /* CONFIG_ARCH_OMAP34XX */
1236
5e1c5ff4
TL		 1237/*
1238 * McBSP1 and McBSP3 are directly mapped on 1610 and 1510.
1239 * 730 has only 2 McBSP, and both of them are MPU peripherals.
1240 */
25cef225 1241static int __devinit omap_mcbsp_probe(struct platform_device *pdev)
bc5d0c89
EV		 1242{
1243 struct omap_mcbsp_platform_data *pdata = pdev->dev.platform_data;
b4b58f58 1244 struct omap_mcbsp *mcbsp;
bc5d0c89
EV		 1245 int id = pdev->id - 1;
1246 int ret = 0;
5e1c5ff4 1247
bc5d0c89
EV		 1248 if (!pdata) {
1249 dev_err(&pdev->dev, "McBSP device initialized without"
1250 "platform data\n");
1251 ret = -EINVAL;
1252 goto exit;
1253 }
1254
1255 dev_dbg(&pdev->dev, "Initializing OMAP McBSP (%d).\n", pdev->id);
1256
b4b58f58 1257 if (id >= omap_mcbsp_count) {
bc5d0c89
EV		 1258 dev_err(&pdev->dev, "Invalid McBSP device id (%d)\n", id);
1259 ret = -EINVAL;
1260 goto exit;
1261 }
1262
b4b58f58
CS		 1263 mcbsp = kzalloc(sizeof(struct omap_mcbsp), GFP_KERNEL);
1264 if (!mcbsp) {
1265 ret = -ENOMEM;
1266 goto exit;
1267 }
b4b58f58
CS		 1268
1269 spin_lock_init(&mcbsp->lock);
1270 mcbsp->id = id + 1;
1271 mcbsp->free = 1;
1272 mcbsp->dma_tx_lch = -1;
1273 mcbsp->dma_rx_lch = -1;
bc5d0c89 1274
b4b58f58
CS		 1275 mcbsp->phys_base = pdata->phys_base;
1276 mcbsp->io_base = ioremap(pdata->phys_base, SZ_4K);
1277 if (!mcbsp->io_base) {
d592dd1a
RK		 1278 ret = -ENOMEM;
1279 goto err_ioremap;
1280 }
1281
bc5d0c89 1282 /* Default I/O is IRQ based */
b4b58f58
CS		 1283 mcbsp->io_type = OMAP_MCBSP_IRQ_IO;
1284 mcbsp->tx_irq = pdata->tx_irq;
1285 mcbsp->rx_irq = pdata->rx_irq;
1286 mcbsp->dma_rx_sync = pdata->dma_rx_sync;
1287 mcbsp->dma_tx_sync = pdata->dma_tx_sync;
bc5d0c89 1288
b820ce4e
RK		 1289 mcbsp->iclk = clk_get(&pdev->dev, "ick");
1290 if (IS_ERR(mcbsp->iclk)) {
1291 ret = PTR_ERR(mcbsp->iclk);
1292 dev_err(&pdev->dev, "unable to get ick: %d\n", ret);
1293 goto err_iclk;
1294 }
06151158 1295
b820ce4e
RK		 1296 mcbsp->fclk = clk_get(&pdev->dev, "fck");
1297 if (IS_ERR(mcbsp->fclk)) {
1298 ret = PTR_ERR(mcbsp->fclk);
1299 dev_err(&pdev->dev, "unable to get fck: %d\n", ret);
1300 goto err_fclk;
bc5d0c89
EV		 1301 }
1302
b4b58f58
CS		 1303 mcbsp->pdata = pdata;
1304 mcbsp->dev = &pdev->dev;
b820ce4e 1305 mcbsp_ptr[id] = mcbsp;
b4b58f58 1306 platform_set_drvdata(pdev, mcbsp);
a1a56f5f
EV		 1307
1308 /* Initialize mcbsp properties for OMAP34XX if needed / applicable */
1309 omap34xx_device_init(mcbsp);
1310
d592dd1a 1311 return 0;
bc5d0c89 1312
b820ce4e
RK		 1313err_fclk:
1314 clk_put(mcbsp->iclk);
1315err_iclk:
b4b58f58 1316 iounmap(mcbsp->io_base);
d592dd1a 1317err_ioremap:
b820ce4e 1318 kfree(mcbsp);
bc5d0c89
EV		 1319exit:
1320 return ret;
1321}
120db2cb 1322
25cef225 1323static int __devexit omap_mcbsp_remove(struct platform_device *pdev)
5e1c5ff4 1324{
bc5d0c89 1325 struct omap_mcbsp *mcbsp = platform_get_drvdata(pdev);
5e1c5ff4 1326
bc5d0c89
EV		 1327 platform_set_drvdata(pdev, NULL);
1328 if (mcbsp) {
5e1c5ff4 1329
bc5d0c89
EV		 1330 if (mcbsp->pdata && mcbsp->pdata->ops &&
1331 mcbsp->pdata->ops->free)
1332 mcbsp->pdata->ops->free(mcbsp->id);
5e1c5ff4 1333
a1a56f5f
EV		 1334 omap34xx_device_exit(mcbsp);
1335
b820ce4e
RK		 1336 clk_disable(mcbsp->fclk);
1337 clk_disable(mcbsp->iclk);
1338 clk_put(mcbsp->fclk);
1339 clk_put(mcbsp->iclk);
bc5d0c89 1340
d592dd1a
RK		 1341 iounmap(mcbsp->io_base);
1342
b820ce4e
RK		 1343 mcbsp->fclk = NULL;
1344 mcbsp->iclk = NULL;
bc5d0c89
EV		 1345 mcbsp->free = 0;
1346 mcbsp->dev = NULL;
5e1c5ff4
TL		 1347 }
1348
1349 return 0;
1350}
1351
bc5d0c89
EV		 1352static struct platform_driver omap_mcbsp_driver = {
1353 .probe = omap_mcbsp_probe,
25cef225 1354 .remove = __devexit_p(omap_mcbsp_remove),
bc5d0c89
EV		 1355 .driver = {
1356 .name = "omap-mcbsp",
1357 },
1358};
1359
1360int __init omap_mcbsp_init(void)
1361{
1362 /* Register the McBSP driver */
1363 return platform_driver_register(&omap_mcbsp_driver);
1364}
Linux 6.x block layer and io_uring tree(s)